Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (35 commits)
  ARM: Update (and cut down) mach-types
  ARM: 6771/1: vexpress: add support for multiple core tiles
  ARM: 6797/1: hw_breakpoint: Fix newlines in WARNings
  ARM: 6751/1: vexpress: select applicable errata workarounds in Kconfig
  ARM: 6753/1: omap4: Enable ARM local timers with OMAP4430 es1.0 exception
  ARM: 6759/1: smp: Select local timers vs broadcast timer support runtime
  ARM: pgtable: add pud-level code
  ARM: 6673/1: LPAE: use phys_addr_t instead of unsigned long for start of membanks
  ARM: Use long long format when printing meminfo physical addresses
  ARM: integrator: add Integrator/CP sched_clock support
  ARM: realview/vexpress: consolidate SMP bringup code
  ARM: realview/vexpress: consolidate localtimer support
  ARM: integrator/versatile: consolidate FPGA IRQ handling code
  ARM: rationalize versatile family Kconfig/Makefile
  ARM: realview: remove old AMBA device DMA definitions
  ARM: versatile: remove old AMBA device DMA definitions
  ARM: vexpress: use new init_early for clock tree and sched_clock init
  ARM: realview: use new init_early for clock tree and sched_clock init
  ARM: versatile: use new init_early for clock tree and sched_clock init
  ARM: integrator: use new init_early for clock tree init
  ...

11 files changed, 50 insertions, 462 deletions

diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index a01b76b7c956..541fa4c109ef 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -8,6 +8,5 @@ obj-$(CONFIG_MACH_REALVIEW_PB11MP)	+= realview_pb11mp.o
 obj-$(CONFIG_MACH_REALVIEW_PB1176)      += realview_pb1176.o
 obj-$(CONFIG_MACH_REALVIEW_PBA8)        += realview_pba8.o
 obj-$(CONFIG_MACH_REALVIEW_PBX)         += realview_pbx.o
-obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
+obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 1c6602cf50e4..75dbc8791d05 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -51,6 +51,7 @@
 #include <mach/irqs.h>
 #include <asm/hardware/timer-sp.h>
 
+#include <plat/clcd.h>
 #include <plat/sched_clock.h>
 
 #include "core.h"
@@ -359,18 +360,19 @@ static struct clk_lookup lookups[] = {
         }
 };
 
-static int __init clk_init(void)
+void __init realview_init_early(void)
 {
+        void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
+
         if (machine_is_realview_pb1176())
-                oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
+                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
         else
-                oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
+                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
-        return 0;
+        versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
 }
-core_initcall(clk_init);
 
 /*
  * CLCD support.
@@ -385,157 +387,6 @@ core_initcall(clk_init);
 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 
-static struct clcd_panel vga = {
-        .mode           = {
-                .name           = "VGA",
-                .refresh        = 60,
-                .xres           = 640,
-                .yres           = 480,
-                .pixclock       = 39721,
-                .left_margin    = 40,
-                .right_margin   = 24,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 96,
-                .vsync_len      = 2,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel xvga = {
-        .mode           = {
-                .name           = "XVGA",
-                .refresh        = 60,
-                .xres           = 1024,
-                .yres           = 768,
-                .pixclock       = 15748,
-                .left_margin    = 152,
-                .right_margin   = 48,
-                .upper_margin   = 23,
-                .lower_margin   = 3,
-                .hsync_len      = 104,
-                .vsync_len      = 4,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel sanyo_3_8_in = {
-        .mode           = {
-                .name           = "Sanyo QVGA",
-                .refresh        = 116,
-                .xres           = 320,
-                .yres           = 240,
-                .pixclock       = 100000,
-                .left_margin    = 6,
-                .right_margin   = 6,
-                .upper_margin   = 5,
-                .lower_margin   = 5,
-                .hsync_len      = 6,
-                .vsync_len      = 6,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel sanyo_2_5_in = {
-        .mode           = {
-                .name           = "Sanyo QVGA Portrait",
-                .refresh        = 116,
-                .xres           = 240,
-                .yres           = 320,
-                .pixclock       = 100000,
-                .left_margin    = 20,
-                .right_margin   = 10,
-                .upper_margin   = 2,
-                .lower_margin   = 2,
-                .hsync_len      = 10,
-                .vsync_len      = 2,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel epson_2_2_in = {
-        .mode           = {
-                .name           = "Epson QCIF",
-                .refresh        = 390,
-                .xres           = 176,
-                .yres           = 220,
-                .pixclock       = 62500,
-                .left_margin    = 3,
-                .right_margin   = 2,
-                .upper_margin   = 1,
-                .lower_margin   = 0,
-                .hsync_len      = 3,
-                .vsync_len      = 2,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-/*
- * Detect which LCD panel is connected, and return the appropriate
- * clcd_panel structure.  Note: we do not have any information on
- * the required timings for the 8.4in panel, so we presently assume
- * VGA timings.
- */
-static struct clcd_panel *realview_clcd_panel(void)
-{
-        void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
-        struct clcd_panel *vga_panel;
-        struct clcd_panel *panel;
-        u32 val;
-
-        if (machine_is_realview_eb())
-                vga_panel = &vga;
-        else
-                vga_panel = &xvga;
-
-        val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
-        if (val == SYS_CLCD_ID_SANYO_3_8)
-                panel = &sanyo_3_8_in;
-        else if (val == SYS_CLCD_ID_SANYO_2_5)
-                panel = &sanyo_2_5_in;
-        else if (val == SYS_CLCD_ID_EPSON_2_2)
-                panel = &epson_2_2_in;
-        else if (val == SYS_CLCD_ID_VGA)
-                panel = vga_panel;
-        else {
-                printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
-                        val);
-                panel = vga_panel;
-        }
-
-        return panel;
-}
-
 /*
  * Disable all display connectors on the interface module.
  */
@@ -565,56 +416,60 @@ static void realview_clcd_enable(struct clcd_fb *fb)
         writel(val, sys_clcd);
 }
 
+/*
+ * Detect which LCD panel is connected, and return the appropriate
+ * clcd_panel structure.  Note: we do not have any information on
+ * the required timings for the 8.4in panel, so we presently assume
+ * VGA timings.
+ */
 static int realview_clcd_setup(struct clcd_fb *fb)
 {
+        void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
+        const char *panel_name, *vga_panel_name;
         unsigned long framesize;
-        dma_addr_t dma;
+        u32 val;
 
-        if (machine_is_realview_eb())
+        if (machine_is_realview_eb()) {
                 /* VGA, 16bpp */
                 framesize = 640 * 480 * 2;
-        else
+                vga_panel_name = "VGA";
+        } else {
                 /* XVGA, 16bpp */
                 framesize = 1024 * 768 * 2;
-
-        fb->panel               = realview_clcd_panel();
-
-        fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
-                                                    &dma, GFP_KERNEL | GFP_DMA);
-        if (!fb->fb.screen_base) {
-                printk(KERN_ERR "CLCD: unable to map framebuffer\n");
-                return -ENOMEM;
+                vga_panel_name = "XVGA";
         }
 
-        fb->fb.fix.smem_start   = dma;
-        fb->fb.fix.smem_len     = framesize;
-
-        return 0;
-}
+        val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
+        if (val == SYS_CLCD_ID_SANYO_3_8)
+                panel_name = "Sanyo TM38QV67A02A";
+        else if (val == SYS_CLCD_ID_SANYO_2_5)
+                panel_name = "Sanyo QVGA Portrait";
+        else if (val == SYS_CLCD_ID_EPSON_2_2)
+                panel_name = "Epson L2F50113T00";
+        else if (val == SYS_CLCD_ID_VGA)
+                panel_name = vga_panel_name;
+        else {
+                pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
+                panel_name = vga_panel_name;
+        }
 
-static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-{
-        return dma_mmap_writecombine(&fb->dev->dev, vma,
-                                     fb->fb.screen_base,
-                                     fb->fb.fix.smem_start,
-                                     fb->fb.fix.smem_len);
-}
+        fb->panel = versatile_clcd_get_panel(panel_name);
+        if (!fb->panel)
+                return -EINVAL;
 
-static void realview_clcd_remove(struct clcd_fb *fb)
-{
-        dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
-                              fb->fb.screen_base, fb->fb.fix.smem_start);
+        return versatile_clcd_setup_dma(fb, framesize);
 }
 
 struct clcd_board clcd_plat_data = {
         .name           = "RealView",
+        .caps           = CLCD_CAP_ALL,
         .check          = clcdfb_check,
         .decode         = clcdfb_decode,
         .disable        = realview_clcd_disable,
         .enable         = realview_clcd_enable,
         .setup          = realview_clcd_setup,
-        .mmap           = realview_clcd_mmap,
-        .remove         = realview_clcd_remove,
+        .mmap           = versatile_clcd_mmap_dma,
+        .remove         = versatile_clcd_remove_dma,
 };
 
 #ifdef CONFIG_LEDS
@@ -656,12 +511,6 @@ void realview_leds_event(led_event_t ledevt)
 #endif  /* CONFIG_LEDS */
 
 /*
- * The sched_clock counter
- */
-#define REFCOUNTER              (__io_address(REALVIEW_SYS_BASE) + \
-                                 REALVIEW_SYS_24MHz_OFFSET)
-
-/*
  * Where is the timer (VA)?
  */
 void __iomem *timer0_va_base;
@@ -676,8 +525,6 @@ void __init realview_timer_init(unsigned int timer_irq)
 {
         u32 val;
 
-        versatile_sched_clock_init(REFCOUNTER, 24000000);
-
         /* 
          * set clock frequency: 
          *      REALVIEW_REFCLK is 32KHz
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 693239ddc39e..5c83d1e87a03 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -42,7 +42,6 @@ static struct amba_device name##_device = {			\
         },                                                      \
         .dma_mask       = ~0,                                   \
         .irq            = base##_IRQ,                           \
-        /* .dma         = base##_DMA,*/                         \
 }
 
 struct machine_desc;
@@ -63,6 +62,7 @@ extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
 extern int realview_usb_register(struct resource *res);
+extern void realview_init_early(void);
 extern void realview_fixup(struct machine_desc *mdesc, struct tag *tags,
                            char **from, struct meminfo *meminfo);
 extern void (*realview_reset)(char);
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
deleted file mode 100644
index b34be4554d40..000000000000
--- a/arch/arm/mach-realview/headsmp.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-        __INIT
-
-/*
- * Realview specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(realview_secondary_startup)
-        mrc     p15, 0, r0, c0, c0, 5
-        and     r0, r0, #15
-        adr     r4, 1f
-        ldmia   r4, {r5, r6}
-        sub     r4, r4, r5
-        add     r6, r6, r4
-pen:    ldr     r7, [r6]
-        cmp     r7, r0
-        bne     pen
-
-        /*
-         * we've been released from the holding pen: secondary_stack
-         * should now contain the SVC stack for this core
-         */
-        b       secondary_startup
-
-        .align
-1:      .long   .
-        .long   pen_release
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
deleted file mode 100644
index 60b4e111f459..000000000000
--- a/arch/arm/mach-realview/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-}
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 6959d13d908a..23919229e12d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -10,44 +10,21 @@
  */
 #include <linux/init.h>
 #include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
+#include <asm/smp_scu.h>
 #include <asm/unified.h>
 
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
 #include <mach/board-pbx.h>
-#include <asm/smp_scu.h>
 
 #include "core.h"
 
-extern void realview_secondary_startup(void);
-
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-
-/*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
- * or not.  This is necessary for the hotplug code to work reliably.
- */
-static void __cpuinit write_pen_release(int val)
-{
-        pen_release = val;
-        smp_wmb();
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-}
+extern void versatile_secondary_startup(void);
 
 static void __iomem *scu_base_addr(void)
 {
@@ -62,75 +39,6 @@ static void __iomem *scu_base_addr(void)
                 return (void __iomem *)0;
 }
 
-static DEFINE_SPINLOCK(boot_lock);
-
-void __cpuinit platform_secondary_init(unsigned int cpu)
-{
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
-         * let the primary processor know we're out of the
-         * pen, then head off into the C entry point
-         */
-        write_pen_release(-1);
-
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
-}
-
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        unsigned long timeout;
-
-        /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
-
-        /*
-         * The secondary processor is waiting to be released from
-         * the holding pen - release it, then wait for it to flag
-         * that it has been released by resetting pen_release.
-         *
-         * Note that "pen_release" is the hardware CPU ID, whereas
-         * "cpu" is Linux's internal ID.
-         */
-        write_pen_release(cpu);
-
-        /*
-         * Send the secondary CPU a soft interrupt, thereby causing
-         * the boot monitor to read the system wide flags register,
-         * and branch to the address found there.
-         */
-        smp_cross_call(cpumask_of(cpu), 1);
-
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout)) {
-                smp_rmb();
-                if (pen_release == -1)
-                        break;
-
-                udelay(10);
-        }
-
-        /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
-         */
-        spin_unlock(&boot_lock);
-
-        return pen_release != -1 ? -ENOSYS : 0;
-}
-
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
@@ -174,6 +82,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
+        __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
                      __io_address(REALVIEW_SYS_FLAGSSET));
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 8ede983b861c..2ecc1d94284e 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -144,60 +144,39 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * These devices are connected via the core APB bridge
  */
 #define GPIO2_IRQ       { IRQ_EB_GPIO2, NO_IRQ }
-#define GPIO2_DMA       { 0, 0 }
 #define GPIO3_IRQ       { IRQ_EB_GPIO3, NO_IRQ }
-#define GPIO3_DMA       { 0, 0 }
 
 #define AACI_IRQ        { IRQ_EB_AACI, NO_IRQ }
-#define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
-#define MMCI0_DMA       { 0x84, 0 }
 #define KMI0_IRQ        { IRQ_EB_KMI0, NO_IRQ }
-#define KMI0_DMA        { 0, 0 }
 #define KMI1_IRQ        { IRQ_EB_KMI1, NO_IRQ }
-#define KMI1_DMA        { 0, 0 }
 
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
 #define EB_SMC_IRQ      { NO_IRQ, NO_IRQ }
-#define EB_SMC_DMA      { 0, 0 }
 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define MPMC_DMA        { 0, 0 }
 #define EB_CLCD_IRQ     { IRQ_EB_CLCD, NO_IRQ }
-#define EB_CLCD_DMA     { 0, 0 }
 #define DMAC_IRQ        { IRQ_EB_DMA, NO_IRQ }
-#define DMAC_DMA        { 0, 0 }
 
 /*
  * These devices are connected via the core APB bridge
  */
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define SCTL_DMA        { 0, 0 }
 #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
-#define EB_WATCHDOG_DMA { 0, 0 }
 #define EB_GPIO0_IRQ    { IRQ_EB_GPIO0, NO_IRQ }
-#define EB_GPIO0_DMA    { 0, 0 }
 #define GPIO1_IRQ       { IRQ_EB_GPIO1, NO_IRQ }
-#define GPIO1_DMA       { 0, 0 }
 #define EB_RTC_IRQ      { IRQ_EB_RTC, NO_IRQ }
-#define EB_RTC_DMA      { 0, 0 }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
 #define SCI_IRQ         { IRQ_EB_SCI, NO_IRQ }
-#define SCI_DMA         { 7, 6 }
 #define EB_UART0_IRQ    { IRQ_EB_UART0, NO_IRQ }
-#define EB_UART0_DMA    { 15, 14 }
 #define EB_UART1_IRQ    { IRQ_EB_UART1, NO_IRQ }
-#define EB_UART1_DMA    { 13, 12 }
 #define EB_UART2_IRQ    { IRQ_EB_UART2, NO_IRQ }
-#define EB_UART2_DMA    { 11, 10 }
 #define EB_UART3_IRQ    { IRQ_EB_UART3, NO_IRQ }
-#define EB_UART3_DMA    { 0x86, 0x87 }
 #define EB_SSP_IRQ      { IRQ_EB_SSP, NO_IRQ }
-#define EB_SSP_DMA      { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,  "fpga:aaci",  AACI,     NULL);
@@ -487,6 +466,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
         .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_eb_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_eb_timer,
         .init_machine   = realview_eb_init,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 9f26369555c7..eab6070f66d0 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -134,47 +134,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PB1176 AMBA devices
  */
 #define GPIO2_IRQ       { IRQ_PB1176_GPIO2, NO_IRQ }
-#define GPIO2_DMA       { 0, 0 }
 #define GPIO3_IRQ       { IRQ_PB1176_GPIO3, NO_IRQ }
-#define GPIO3_DMA       { 0, 0 }
 #define AACI_IRQ        { IRQ_PB1176_AACI, NO_IRQ }
-#define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
-#define MMCI0_DMA       { 0x84, 0 }
 #define KMI0_IRQ        { IRQ_PB1176_KMI0, NO_IRQ }
-#define KMI0_DMA        { 0, 0 }
 #define KMI1_IRQ        { IRQ_PB1176_KMI1, NO_IRQ }
-#define KMI1_DMA        { 0, 0 }
 #define PB1176_SMC_IRQ  { NO_IRQ, NO_IRQ }
-#define PB1176_SMC_DMA  { 0, 0 }
 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define MPMC_DMA        { 0, 0 }
 #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
-#define PB1176_CLCD_DMA { 0, 0 }
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define SCTL_DMA        { 0, 0 }
 #define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
-#define PB1176_WATCHDOG_DMA     { 0, 0 }
 #define PB1176_GPIO0_IRQ        { IRQ_PB1176_GPIO0, NO_IRQ }
-#define PB1176_GPIO0_DMA        { 0, 0 }
 #define GPIO1_IRQ       { IRQ_PB1176_GPIO1, NO_IRQ }
-#define GPIO1_DMA       { 0, 0 }
 #define PB1176_RTC_IRQ  { IRQ_DC1176_RTC, NO_IRQ }
-#define PB1176_RTC_DMA  { 0, 0 }
 #define SCI_IRQ         { IRQ_PB1176_SCI, NO_IRQ }
-#define SCI_DMA         { 7, 6 }
 #define PB1176_UART0_IRQ        { IRQ_DC1176_UART0, NO_IRQ }
-#define PB1176_UART0_DMA        { 15, 14 }
 #define PB1176_UART1_IRQ        { IRQ_DC1176_UART1, NO_IRQ }
-#define PB1176_UART1_DMA        { 13, 12 }
 #define PB1176_UART2_IRQ        { IRQ_DC1176_UART2, NO_IRQ }
-#define PB1176_UART2_DMA        { 11, 10 }
 #define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
-#define PB1176_UART3_DMA        { 0x86, 0x87 }
 #define PB1176_UART4_IRQ        { IRQ_PB1176_UART4, NO_IRQ }
-#define PB1176_UART4_DMA        { 0, 0 }
 #define PB1176_SSP_IRQ          { IRQ_DC1176_SSP, NO_IRQ }
-#define PB1176_SSP_DMA          { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -382,6 +361,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
         .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_pb1176_fixup,
         .map_io         = realview_pb1176_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pb1176_timer,
         .init_machine   = realview_pb1176_init,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index dea06b2da3a2..b2985fc7cd4e 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -136,47 +136,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  */
 
 #define GPIO2_IRQ               { IRQ_PB11MP_GPIO2, NO_IRQ }
-#define GPIO2_DMA               { 0, 0 }
 #define GPIO3_IRQ               { IRQ_PB11MP_GPIO3, NO_IRQ }
-#define GPIO3_DMA               { 0, 0 }
 #define AACI_IRQ                { IRQ_TC11MP_AACI, NO_IRQ }
-#define AACI_DMA                { 0x80, 0x81 }
 #define MMCI0_IRQ               { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
-#define MMCI0_DMA               { 0x84, 0 }
 #define KMI0_IRQ                { IRQ_TC11MP_KMI0, NO_IRQ }
-#define KMI0_DMA                { 0, 0 }
 #define KMI1_IRQ                { IRQ_TC11MP_KMI1, NO_IRQ }
-#define KMI1_DMA                { 0, 0 }
 #define PB11MP_SMC_IRQ          { NO_IRQ, NO_IRQ }
-#define PB11MP_SMC_DMA          { 0, 0 }
 #define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define MPMC_DMA                { 0, 0 }
 #define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD, NO_IRQ }
-#define PB11MP_CLCD_DMA         { 0, 0 }
 #define DMAC_IRQ                { IRQ_PB11MP_DMAC, NO_IRQ }
-#define DMAC_DMA                { 0, 0 }
 #define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define SCTL_DMA                { 0, 0 }
 #define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG, NO_IRQ }
-#define PB11MP_WATCHDOG_DMA     { 0, 0 }
 #define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0, NO_IRQ }
-#define PB11MP_GPIO0_DMA        { 0, 0 }
 #define GPIO1_IRQ               { IRQ_PB11MP_GPIO1, NO_IRQ }
-#define GPIO1_DMA               { 0, 0 }
 #define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC, NO_IRQ }
-#define PB11MP_RTC_DMA          { 0, 0 }
 #define SCI_IRQ                 { IRQ_PB11MP_SCI, NO_IRQ }
-#define SCI_DMA                 { 7, 6 }
 #define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0, NO_IRQ }
-#define PB11MP_UART0_DMA        { 15, 14 }
 #define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1, NO_IRQ }
-#define PB11MP_UART1_DMA        { 13, 12 }
 #define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2, NO_IRQ }
-#define PB11MP_UART2_DMA        { 11, 10 }
 #define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3, NO_IRQ }
-#define PB11MP_UART3_DMA        { 0x86, 0x87 }
 #define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP, NO_IRQ }
-#define PB11MP_SSP_DMA          { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -384,6 +363,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
         .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_pb11mp_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pb11mp_timer,
         .init_machine   = realview_pb11mp_init,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 7d0f1734a217..fb6866558760 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -126,47 +126,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  */
 
 #define GPIO2_IRQ               { IRQ_PBA8_GPIO2, NO_IRQ }
-#define GPIO2_DMA               { 0, 0 }
 #define GPIO3_IRQ               { IRQ_PBA8_GPIO3, NO_IRQ }
-#define GPIO3_DMA               { 0, 0 }
 #define AACI_IRQ                { IRQ_PBA8_AACI, NO_IRQ }
-#define AACI_DMA                { 0x80, 0x81 }
 #define MMCI0_IRQ               { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
-#define MMCI0_DMA               { 0x84, 0 }
 #define KMI0_IRQ                { IRQ_PBA8_KMI0, NO_IRQ }
-#define KMI0_DMA                { 0, 0 }
 #define KMI1_IRQ                { IRQ_PBA8_KMI1, NO_IRQ }
-#define KMI1_DMA                { 0, 0 }
 #define PBA8_SMC_IRQ            { NO_IRQ, NO_IRQ }
-#define PBA8_SMC_DMA            { 0, 0 }
 #define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define MPMC_DMA                { 0, 0 }
 #define PBA8_CLCD_IRQ           { IRQ_PBA8_CLCD, NO_IRQ }
-#define PBA8_CLCD_DMA           { 0, 0 }
 #define DMAC_IRQ                { IRQ_PBA8_DMAC, NO_IRQ }
-#define DMAC_DMA                { 0, 0 }
 #define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define SCTL_DMA                { 0, 0 }
 #define PBA8_WATCHDOG_IRQ       { IRQ_PBA8_WATCHDOG, NO_IRQ }
-#define PBA8_WATCHDOG_DMA       { 0, 0 }
 #define PBA8_GPIO0_IRQ          { IRQ_PBA8_GPIO0, NO_IRQ }
-#define PBA8_GPIO0_DMA          { 0, 0 }
 #define GPIO1_IRQ               { IRQ_PBA8_GPIO1, NO_IRQ }
-#define GPIO1_DMA               { 0, 0 }
 #define PBA8_RTC_IRQ            { IRQ_PBA8_RTC, NO_IRQ }
-#define PBA8_RTC_DMA            { 0, 0 }
 #define SCI_IRQ                 { IRQ_PBA8_SCI, NO_IRQ }
-#define SCI_DMA                 { 7, 6 }
 #define PBA8_UART0_IRQ          { IRQ_PBA8_UART0, NO_IRQ }
-#define PBA8_UART0_DMA          { 15, 14 }
 #define PBA8_UART1_IRQ          { IRQ_PBA8_UART1, NO_IRQ }
-#define PBA8_UART1_DMA          { 13, 12 }
 #define PBA8_UART2_IRQ          { IRQ_PBA8_UART2, NO_IRQ }
-#define PBA8_UART2_DMA          { 11, 10 }
 #define PBA8_UART3_IRQ          { IRQ_PBA8_UART3, NO_IRQ }
-#define PBA8_UART3_DMA          { 0x86, 0x87 }
 #define PBA8_SSP_IRQ            { IRQ_PBA8_SSP, NO_IRQ }
-#define PBA8_SSP_DMA            { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -334,6 +313,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
         .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_pba8_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pba8_timer,
         .init_machine   = realview_pba8_init,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index b89e28f8853e..92ace2cf2b2c 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -148,47 +148,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  */
 
 #define GPIO2_IRQ               { IRQ_PBX_GPIO2, NO_IRQ }
-#define GPIO2_DMA               { 0, 0 }
 #define GPIO3_IRQ               { IRQ_PBX_GPIO3, NO_IRQ }
-#define GPIO3_DMA               { 0, 0 }
 #define AACI_IRQ                { IRQ_PBX_AACI, NO_IRQ }
-#define AACI_DMA                { 0x80, 0x81 }
 #define MMCI0_IRQ               { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
-#define MMCI0_DMA               { 0x84, 0 }
 #define KMI0_IRQ                { IRQ_PBX_KMI0, NO_IRQ }
-#define KMI0_DMA                { 0, 0 }
 #define KMI1_IRQ                { IRQ_PBX_KMI1, NO_IRQ }
-#define KMI1_DMA                { 0, 0 }
 #define PBX_SMC_IRQ             { NO_IRQ, NO_IRQ }
-#define PBX_SMC_DMA             { 0, 0 }
 #define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define MPMC_DMA                { 0, 0 }
 #define PBX_CLCD_IRQ            { IRQ_PBX_CLCD, NO_IRQ }
-#define PBX_CLCD_DMA            { 0, 0 }
 #define DMAC_IRQ                { IRQ_PBX_DMAC, NO_IRQ }
-#define DMAC_DMA                { 0, 0 }
 #define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define SCTL_DMA                { 0, 0 }
 #define PBX_WATCHDOG_IRQ        { IRQ_PBX_WATCHDOG, NO_IRQ }
-#define PBX_WATCHDOG_DMA        { 0, 0 }
 #define PBX_GPIO0_IRQ           { IRQ_PBX_GPIO0, NO_IRQ }
-#define PBX_GPIO0_DMA           { 0, 0 }
 #define GPIO1_IRQ               { IRQ_PBX_GPIO1, NO_IRQ }
-#define GPIO1_DMA               { 0, 0 }
 #define PBX_RTC_IRQ             { IRQ_PBX_RTC, NO_IRQ }
-#define PBX_RTC_DMA             { 0, 0 }
 #define SCI_IRQ                 { IRQ_PBX_SCI, NO_IRQ }
-#define SCI_DMA                 { 7, 6 }
 #define PBX_UART0_IRQ           { IRQ_PBX_UART0, NO_IRQ }
-#define PBX_UART0_DMA           { 15, 14 }
 #define PBX_UART1_IRQ           { IRQ_PBX_UART1, NO_IRQ }
-#define PBX_UART1_DMA           { 13, 12 }
 #define PBX_UART2_IRQ           { IRQ_PBX_UART2, NO_IRQ }
-#define PBX_UART2_DMA           { 11, 10 }
 #define PBX_UART3_IRQ           { IRQ_PBX_UART3, NO_IRQ }
-#define PBX_UART3_DMA           { 0x86, 0x87 }
 #define PBX_SSP_IRQ             { IRQ_PBX_SSP, NO_IRQ }
-#define PBX_SSP_DMA             { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -417,6 +396,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
         .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_pbx_fixup,
         .map_io         = realview_pbx_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pbx_timer,
         .init_machine   = realview_pbx_init,