aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-realview
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-05-17 11:23:45 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-05-17 11:23:45 -0400
commit78d236c2b30d4712c1fd8c9768b163c94b39e77d (patch)
treeae74765abee1ed88941a5dfc82cffc4d3af25be7 /arch/arm/mach-realview
parent826681043d7184b4d650cab5b007b9a86b628eb5 (diff)
[ARM] realview: remove useless smp_cross_call_done()
smp_cross_call_done() is a no-op for MPCore, and since it's only used by platform code, there's no point in having it unless it's doing something. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-realview')
-rw-r--r--arch/arm/mach-realview/include/mach/smp.h7
-rw-r--r--arch/arm/mach-realview/platsmp.c7
2 files changed, 0 insertions, 14 deletions
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index e2ff53402f8c..dd53892d44a7 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -20,11 +20,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
20 gic_raise_softirq(mask, 1); 20 gic_raise_softirq(mask, 1);
21} 21}
22 22
23/*
24 * Do nothing on MPcore.
25 */
26static inline void smp_cross_call_done(const struct cpumask *mask)
27{
28}
29
30#endif 23#endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index a5730466dff5..b037fd6c82dc 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -78,13 +78,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
78 trace_hardirqs_off(); 78 trace_hardirqs_off();
79 79
80 /* 80 /*
81 * the primary core may have used a "cross call" soft interrupt
82 * to get this processor out of WFI in the BootMonitor - make
83 * sure that we are no longer being sent this soft interrupt
84 */
85 smp_cross_call_done(cpumask_of(cpu));
86
87 /*
88 * if any interrupts are already enabled for the primary 81 * if any interrupts are already enabled for the primary
89 * core (e.g. timer irq), then they will not have been enabled 82 * core (e.g. timer irq), then they will not have been enabled
90 * for us: do so 83 * for us: do so