Merge Realview GIC code

3 files changed, 34 insertions, 5 deletions

diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 17f5f4439fe7..68bc6b226ec7 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -16,4 +16,14 @@ config REALVIEW_MPCORE
           kernel built with this option enabled is not compatible with
           other tiles.
 
+config REALVIEW_MPCORE_REVB
+        bool "Support MPcore RevB tile"
+        depends on REALVIEW_MPCORE
+        default n
+        help
+          Enable support for the MPCore RevB tile on the Realview platform.
+          Since there are device address differences, a
+          kernel built with this option enabled is not compatible with
+          other tiles.
+
 endmenu
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index b8484e15dacb..709a9b1ac634 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -52,7 +52,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
+        gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
 
         /*
          * let the primary processor know we're out of the
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 9741b4d3c9cf..effe243454e0 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -57,7 +57,21 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
+        },
+#ifdef CONFIG_REALVIEW_MPCORE
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
         }, {
+                .virtual        = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+#endif
+        {
                 .virtual        = IO_ADDRESS(REALVIEW_SCTL_BASE),
                 .pfn            = __phys_to_pfn(REALVIEW_SCTL_BASE),
                 .length         = SZ_4K,
@@ -138,13 +152,18 @@ static void __init gic_init_irq(void)
 #ifdef CONFIG_REALVIEW_MPCORE
         unsigned int pldctrl;
         writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
-        pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
+        pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
         pldctrl |= 0x00800000;  /* New irq mode */
-        writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
+        writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
         writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 #endif
-        gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
-        gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
+        gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
+        gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
+#ifdef CONFIG_REALVIEW_MPCORE
+        gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64);
+        gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE));
+        gic_cascade_irq(1, IRQ_EB_IRQ1);
+#endif
 }
 
 static void __init realview_eb_init(void)