ARM: l2c: realview: improve commentry about the L2 cache requirements

Add better commentry about the L2 cache requirements on these platforms.
Unfortunately, the auxiliary control register is not pre-set to indicate
the correct cache parameters, so we have to manually program these.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 7 insertions, 2 deletions

diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index f4b0962578fe..101deaf2630b 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -337,8 +337,13 @@ static void __init realview_pb11mp_init(void)
         int i;
 
 #ifdef CONFIG_CACHE_L2X0
-        /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
-         * Bits:  .... ...0 0111 1001 0000 .... .... .... */
+        /*
+         * The PL220 needs to be manually configured as the hardware
+         * doesn't report the correct sizes.
+         * 1MB (128KB/way), 8-way associativity, event monitor and
+         * parity enabled, ignore share bit, no force write allocate
+         * Bits:  .... ...0 0111 1001 0000 .... .... ....
+         */
         l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
 #endif