[ARM] 4108/2: Allow multiple GIC interrupt controllers in a system

The current implementation only assumes one GIC to be present in the
system. However, there are platforms with more than one cascaded interrupt
controllers (RealView/EB MPCore for example).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 9741b4d3c9cf..b6a6f68cb699 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -143,8 +143,8 @@ static void __init gic_init_irq(void)
         writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
         writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 #endif
-        gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
-        gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
+        gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
+        gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
 }
 
 static void __init realview_eb_init(void)