diff options
author | Jon Callan <Jon.Callan@arm.com> | 2008-12-01 09:54:56 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2008-12-01 09:54:56 -0500 |
commit | 4c3ea3717103ffcccfaebedb98c2dadfb54e0482 (patch) | |
tree | aeef9b14e999051c9b1e3cb01c0dae48428f16d8 /arch/arm/mach-realview/platsmp.c | |
parent | 8aa2da872a492a2196397603ed756a4c48677122 (diff) |
RealView: Add Cortex-A9 support to the EB board
This patch adds the necessary definitions and Kconfig entries to enable
Cortex-A9 (ARMv7 SMP) tiles on the RealView/EB board.
Signed-off-by: Jon Callan <Jon.Callan@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mach-realview/platsmp.c')
-rw-r--r-- | arch/arm/mach-realview/platsmp.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index e102aeb0f76e..8dcb085dca4e 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c | |||
@@ -36,7 +36,8 @@ static unsigned int __init get_core_count(void) | |||
36 | unsigned int ncores; | 36 | unsigned int ncores; |
37 | void __iomem *scu_base = 0; | 37 | void __iomem *scu_base = 0; |
38 | 38 | ||
39 | if (machine_is_realview_eb() && core_tile_eb11mp()) | 39 | if (machine_is_realview_eb() && |
40 | (core_tile_eb11mp() || core_tile_a9mp())) | ||
40 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); | 41 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); |
41 | else if (machine_is_realview_pb11mp()) | 42 | else if (machine_is_realview_pb11mp()) |
42 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); | 43 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); |
@@ -58,7 +59,8 @@ static void scu_enable(void) | |||
58 | u32 scu_ctrl; | 59 | u32 scu_ctrl; |
59 | void __iomem *scu_base; | 60 | void __iomem *scu_base; |
60 | 61 | ||
61 | if (machine_is_realview_eb() && core_tile_eb11mp()) | 62 | if (machine_is_realview_eb() && |
63 | (core_tile_eb11mp() || core_tile_a9mp())) | ||
62 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); | 64 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); |
63 | else if (machine_is_realview_pb11mp()) | 65 | else if (machine_is_realview_pb11mp()) |
64 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); | 66 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); |
@@ -88,7 +90,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) | |||
88 | * core (e.g. timer irq), then they will not have been enabled | 90 | * core (e.g. timer irq), then they will not have been enabled |
89 | * for us: do so | 91 | * for us: do so |
90 | */ | 92 | */ |
91 | if (machine_is_realview_eb() && core_tile_eb11mp()) | 93 | if (machine_is_realview_eb() && |
94 | (core_tile_eb11mp() || core_tile_a9mp())) | ||
92 | gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); | 95 | gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); |
93 | else if (machine_is_realview_pb11mp()) | 96 | else if (machine_is_realview_pb11mp()) |
94 | gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); | 97 | gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); |
@@ -232,7 +235,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
232 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in | 235 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in |
233 | * realview_timer_init | 236 | * realview_timer_init |
234 | */ | 237 | */ |
235 | if ((machine_is_realview_eb() && core_tile_eb11mp()) || | 238 | if ((machine_is_realview_eb() && |
239 | (core_tile_eb11mp() || core_tile_a9mp())) || | ||
236 | machine_is_realview_pb11mp()) | 240 | machine_is_realview_pb11mp()) |
237 | local_timer_setup(cpu); | 241 | local_timer_setup(cpu); |
238 | #endif | 242 | #endif |