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authorroot <root@dyn-67.arm.linux.org.uk>2009-03-24 18:04:25 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-24 18:04:25 -0400
commit9a38e989b8ce04923f919fc2a8a24eb07fb484e2 (patch)
tree6b99638dc32b99420ada46ca8d1373ad7aa5a208 /arch/arm/mach-pxa
parent7d83f8fca517b123cf0136503a9e50974f65ec49 (diff)
parent5fa82eb8ff06cd3ac4d64c6875922ae1dfa003c5 (diff)
Merge branch 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
Diffstat (limited to 'arch/arm/mach-pxa')
-rw-r--r--arch/arm/mach-pxa/Kconfig12
-rw-r--r--arch/arm/mach-pxa/Makefile8
-rw-r--r--arch/arm/mach-pxa/clock.c4
-rw-r--r--arch/arm/mach-pxa/clock.h2
-rw-r--r--arch/arm/mach-pxa/colibri-pxa270.c (renamed from arch/arm/mach-pxa/colibri.c)50
-rw-r--r--arch/arm/mach-pxa/colibri-pxa300.c190
-rw-r--r--arch/arm/mach-pxa/colibri-pxa320.c187
-rw-r--r--arch/arm/mach-pxa/colibri-pxa3xx.c121
-rw-r--r--arch/arm/mach-pxa/dma.c144
-rw-r--r--arch/arm/mach-pxa/e740.c2
-rw-r--r--arch/arm/mach-pxa/e750.c2
-rw-r--r--arch/arm/mach-pxa/e800.c2
-rw-r--r--arch/arm/mach-pxa/gpio.c365
-rw-r--r--arch/arm/mach-pxa/include/mach/colibri.h32
-rw-r--r--arch/arm/mach-pxa/include/mach/dma.h83
-rw-r--r--arch/arm/mach-pxa/include/mach/gpio.h32
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa27x.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa300.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa320.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h130
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa930.h1
-rw-r--r--arch/arm/mach-pxa/mfp-pxa3xx.c189
-rw-r--r--arch/arm/mach-pxa/pxa300.c10
-rw-r--r--arch/arm/mach-pxa/pxa320.c6
-rw-r--r--arch/arm/mach-pxa/pxa930.c6
-rw-r--r--arch/arm/mach-pxa/tosa.c2
28 files changed, 608 insertions, 980 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index d13282d773aa..96a2006cb597 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -262,9 +262,19 @@ config MACH_EXEDA
262 select PXA27x 262 select PXA27x
263 263
264config MACH_COLIBRI 264config MACH_COLIBRI
265 bool "Toradex Colibri PX27x" 265 bool "Toradex Colibri PXA270"
266 select PXA27x 266 select PXA27x
267 267
268config MACH_COLIBRI300
269 bool "Toradex Colibri PXA300/310"
270 select PXA3xx
271 select CPU_PXA300
272
273config MACH_COLIBRI320
274 bool "Toradex Colibri PXA320"
275 select PXA3xx
276 select CPU_PXA320
277
268config MACH_ZYLONITE 278config MACH_ZYLONITE
269 bool "PXA3xx Development Platform (aka Zylonite)" 279 bool "PXA3xx Development Platform (aka Zylonite)"
270 select PXA3xx 280 select PXA3xx
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 8da8e63d048b..c80e1bac4945 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,8 +3,8 @@
3# 3#
4 4
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o devices.o generic.o irq.o dma.o \ 6obj-y += clock.o devices.o generic.o irq.o \
7 time.o gpio.o reset.o 7 time.o reset.o
8obj-$(CONFIG_PM) += pm.o sleep.o standby.o 8obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9 9
10ifeq ($(CONFIG_CPU_FREQ),y) 10ifeq ($(CONFIG_CPU_FREQ),y)
@@ -35,7 +35,9 @@ obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
35obj-$(CONFIG_MACH_MP900C) += mp900.o 35obj-$(CONFIG_MACH_MP900C) += mp900.o
36obj-$(CONFIG_ARCH_PXA_IDP) += idp.o 36obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
37obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o 37obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
38obj-$(CONFIG_MACH_COLIBRI) += colibri.o 38obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o
39obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o
40obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o
39obj-$(CONFIG_MACH_H5000) += h5000.o 41obj-$(CONFIG_MACH_H5000) += h5000.o
40obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o 42obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o
41obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o 43obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 40b774084514..db52d2c4791d 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -87,7 +87,7 @@ void clks_register(struct clk_lookup *clks, size_t num)
87 clkdev_add(&clks[i]); 87 clkdev_add(&clks[i]);
88} 88}
89 89
90int clk_add_alias(char *alias, struct device *alias_dev, char *id, 90int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
91 struct device *dev) 91 struct device *dev)
92{ 92{
93 struct clk *r = clk_get(dev, id); 93 struct clk *r = clk_get(dev, id);
@@ -96,7 +96,7 @@ int clk_add_alias(char *alias, struct device *alias_dev, char *id,
96 if (!r) 96 if (!r)
97 return -ENODEV; 97 return -ENODEV;
98 98
99 l = clkdev_alloc(r, alias, alias_dev ? dev_name(alias_dev) : NULL); 99 l = clkdev_alloc(r, alias, alias_dev_name);
100 clk_put(r); 100 clk_put(r);
101 if (!l) 101 if (!l)
102 return -ENODEV; 102 return -ENODEV;
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 4e9c613c6767..5599bceff738 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -69,6 +69,6 @@ extern void clk_pxa3xx_cken_disable(struct clk *);
69#endif 69#endif
70 70
71void clks_register(struct clk_lookup *clks, size_t num); 71void clks_register(struct clk_lookup *clks, size_t num);
72int clk_add_alias(char *alias, struct device *alias_dev, char *id, 72int clk_add_alias(const char *alias, const char *alias_name, char *id,
73 struct device *dev); 73 struct device *dev);
74 74
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 26493ae2889e..01bcfaae75bc 100644
--- a/arch/arm/mach-pxa/colibri.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-pxa/colibri.c 2 * linux/arch/arm/mach-pxa/colibri-pxa270.c
3 * 3 *
4 * Support for Toradex PXA27x based Colibri module 4 * Support for Toradex PXA270 based Colibri module
5 * Daniel Mack <daniel@caiaq.de> 5 * Daniel Mack <daniel@caiaq.de>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -20,6 +20,7 @@
20#include <linux/mtd/mtd.h> 20#include <linux/mtd/mtd.h>
21#include <linux/mtd/partitions.h> 21#include <linux/mtd/partitions.h>
22#include <linux/mtd/physmap.h> 22#include <linux/mtd/physmap.h>
23#include <linux/gpio.h>
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24#include <mach/hardware.h> 25#include <mach/hardware.h>
25#include <asm/irq.h> 26#include <asm/irq.h>
@@ -35,13 +36,16 @@
35#include "generic.h" 36#include "generic.h"
36#include "devices.h" 37#include "devices.h"
37 38
38static unsigned long colibri_pin_config[] __initdata = { 39/*
40 * GPIO configuration
41 */
42static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = {
39 GPIO78_nCS_2, /* Ethernet CS */ 43 GPIO78_nCS_2, /* Ethernet CS */
40 GPIO114_GPIO, /* Ethernet IRQ */ 44 GPIO114_GPIO, /* Ethernet IRQ */
41}; 45};
42 46
43/* 47/*
44 * Flash 48 * NOR flash
45 */ 49 */
46static struct mtd_partition colibri_partitions[] = { 50static struct mtd_partition colibri_partitions[] = {
47 { 51 {
@@ -70,39 +74,40 @@ static struct physmap_flash_data colibri_flash_data[] = {
70 } 74 }
71}; 75};
72 76
73static struct resource flash_resource = { 77static struct resource colibri_pxa270_flash_resource = {
74 .start = PXA_CS0_PHYS, 78 .start = PXA_CS0_PHYS,
75 .end = PXA_CS0_PHYS + SZ_32M - 1, 79 .end = PXA_CS0_PHYS + SZ_32M - 1,
76 .flags = IORESOURCE_MEM, 80 .flags = IORESOURCE_MEM,
77}; 81};
78 82
79static struct platform_device flash_device = { 83static struct platform_device colibri_pxa270_flash_device = {
80 .name = "physmap-flash", 84 .name = "physmap-flash",
81 .id = 0, 85 .id = 0,
82 .dev = { 86 .dev = {
83 .platform_data = colibri_flash_data, 87 .platform_data = colibri_flash_data,
84 }, 88 },
85 .resource = &flash_resource, 89 .resource = &colibri_pxa270_flash_resource,
86 .num_resources = 1, 90 .num_resources = 1,
87}; 91};
88 92
89/* 93/*
90 * DM9000 Ethernet 94 * DM9000 Ethernet
91 */ 95 */
96#if defined(CONFIG_DM9000)
92static struct resource dm9000_resources[] = { 97static struct resource dm9000_resources[] = {
93 [0] = { 98 [0] = {
94 .start = COLIBRI_ETH_PHYS, 99 .start = COLIBRI_PXA270_ETH_PHYS,
95 .end = COLIBRI_ETH_PHYS + 3, 100 .end = COLIBRI_PXA270_ETH_PHYS + 3,
96 .flags = IORESOURCE_MEM, 101 .flags = IORESOURCE_MEM,
97 }, 102 },
98 [1] = { 103 [1] = {
99 .start = COLIBRI_ETH_PHYS + 4, 104 .start = COLIBRI_PXA270_ETH_PHYS + 4,
100 .end = COLIBRI_ETH_PHYS + 4 + 500, 105 .end = COLIBRI_PXA270_ETH_PHYS + 4 + 500,
101 .flags = IORESOURCE_MEM, 106 .flags = IORESOURCE_MEM,
102 }, 107 },
103 [2] = { 108 [2] = {
104 .start = COLIBRI_ETH_IRQ, 109 .start = COLIBRI_PXA270_ETH_IRQ,
105 .end = COLIBRI_ETH_IRQ, 110 .end = COLIBRI_PXA270_ETH_IRQ,
106 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, 111 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
107 }, 112 },
108}; 113};
@@ -113,25 +118,28 @@ static struct platform_device dm9000_device = {
113 .num_resources = ARRAY_SIZE(dm9000_resources), 118 .num_resources = ARRAY_SIZE(dm9000_resources),
114 .resource = dm9000_resources, 119 .resource = dm9000_resources,
115}; 120};
121#endif /* CONFIG_DM9000 */
116 122
117static struct platform_device *colibri_devices[] __initdata = { 123static struct platform_device *colibri_pxa270_devices[] __initdata = {
118 &flash_device, 124 &colibri_pxa270_flash_device,
125#if defined(CONFIG_DM9000)
119 &dm9000_device, 126 &dm9000_device,
127#endif
120}; 128};
121 129
122static void __init colibri_init(void) 130static void __init colibri_pxa270_init(void)
123{ 131{
124 pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pin_config)); 132 pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config));
125 133 platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices));
126 platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
127} 134}
128 135
129MACHINE_START(COLIBRI, "Toradex Colibri PXA27x") 136MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
130 .phys_io = 0x40000000, 137 .phys_io = 0x40000000,
131 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, 138 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
132 .boot_params = COLIBRI_SDRAM_BASE + 0x100, 139 .boot_params = COLIBRI_SDRAM_BASE + 0x100,
133 .init_machine = colibri_init, 140 .init_machine = colibri_pxa270_init,
134 .map_io = pxa_map_io, 141 .map_io = pxa_map_io,
135 .init_irq = pxa27x_init_irq, 142 .init_irq = pxa27x_init_irq,
136 .timer = &pxa_timer, 143 .timer = &pxa_timer,
137MACHINE_END 144MACHINE_END
145
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
new file mode 100644
index 000000000000..169ab552c21a
--- /dev/null
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -0,0 +1,190 @@
1/*
2 * arch/arm/mach-pxa/colibri-pxa300.c
3 *
4 * Support for Toradex PXA300/310 based Colibri module
5 *
6 * Daniel Mack <daniel@caiaq.de>
7 * Matthias Meier <matthias.j.meier@gmx.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <net/ax88796.h>
19
20#include <asm/mach-types.h>
21#include <asm/sizes.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/irq.h>
24
25#include <mach/pxa300.h>
26#include <mach/colibri.h>
27#include <mach/ohci.h>
28#include <mach/pxafb.h>
29
30#include "generic.h"
31#include "devices.h"
32
33#if defined(CONFIG_AX88796)
34#define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO)
35/*
36 * Asix AX88796 Ethernet
37 */
38static struct ax_plat_data colibri_asix_platdata = {
39 .flags = AXFLG_MAC_FROMDEV,
40 .wordlength = 2
41};
42
43static struct resource colibri_asix_resource[] = {
44 [0] = {
45 .start = PXA3xx_CS2_PHYS,
46 .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1,
47 .flags = IORESOURCE_MEM,
48 },
49 [1] = {
50 .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
51 .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
52 .flags = IORESOURCE_IRQ
53 }
54};
55
56static struct platform_device asix_device = {
57 .name = "ax88796",
58 .id = 0,
59 .num_resources = ARRAY_SIZE(colibri_asix_resource),
60 .resource = colibri_asix_resource,
61 .dev = {
62 .platform_data = &colibri_asix_platdata
63 }
64};
65
66static mfp_cfg_t colibri_pxa300_eth_pin_config[] __initdata = {
67 GPIO1_nCS2, /* AX88796 chip select */
68 GPIO26_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */
69};
70
71static void __init colibri_pxa300_init_eth(void)
72{
73 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_eth_pin_config));
74 set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING);
75 platform_device_register(&asix_device);
76}
77#else
78static inline void __init colibri_pxa300_init_eth(void) {}
79#endif /* CONFIG_AX88796 */
80
81#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
82static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = {
83 GPIO0_2_USBH_PEN,
84 GPIO1_2_USBH_PWR,
85};
86
87static struct pxaohci_platform_data colibri_pxa300_ohci_info = {
88 .port_mode = PMM_GLOBAL_MODE,
89 .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
90};
91
92void __init colibri_pxa300_init_ohci(void)
93{
94 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config));
95 pxa_set_ohci_info(&colibri_pxa300_ohci_info);
96}
97#else
98static inline void colibri_pxa300_init_ohci(void) {}
99#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
100
101static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = {
102 GPIO7_MMC1_CLK,
103 GPIO14_MMC1_CMD,
104 GPIO3_MMC1_DAT0,
105 GPIO4_MMC1_DAT1,
106 GPIO5_MMC1_DAT2,
107 GPIO6_MMC1_DAT3,
108};
109
110#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
111static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = {
112 GPIO54_LCD_LDD_0,
113 GPIO55_LCD_LDD_1,
114 GPIO56_LCD_LDD_2,
115 GPIO57_LCD_LDD_3,
116 GPIO58_LCD_LDD_4,
117 GPIO59_LCD_LDD_5,
118 GPIO60_LCD_LDD_6,
119 GPIO61_LCD_LDD_7,
120 GPIO62_LCD_LDD_8,
121 GPIO63_LCD_LDD_9,
122 GPIO64_LCD_LDD_10,
123 GPIO65_LCD_LDD_11,
124 GPIO66_LCD_LDD_12,
125 GPIO67_LCD_LDD_13,
126 GPIO68_LCD_LDD_14,
127 GPIO69_LCD_LDD_15,
128 GPIO70_LCD_LDD_16,
129 GPIO71_LCD_LDD_17,
130 GPIO62_LCD_CS_N,
131 GPIO72_LCD_FCLK,
132 GPIO73_LCD_LCLK,
133 GPIO74_LCD_PCLK,
134 GPIO75_LCD_BIAS,
135 GPIO76_LCD_VSYNC,
136};
137
138static void __init colibri_pxa300_init_lcd(void)
139{
140 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_lcd_pin_config));
141}
142
143#else
144static inline void colibri_pxa300_init_lcd(void) {}
145#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
146
147#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE)
148static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = {
149 GPIO24_AC97_SYSCLK,
150 GPIO23_AC97_nACRESET,
151 GPIO25_AC97_SDATA_IN_0,
152 GPIO27_AC97_SDATA_OUT,
153 GPIO28_AC97_SYNC,
154 GPIO29_AC97_BITCLK
155};
156
157static inline void __init colibri_pxa310_init_ac97(void)
158{
159 /* no AC97 codec on Colibri PXA300 */
160 if (!cpu_is_pxa310())
161 return;
162
163 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa310_ac97_pin_config));
164 pxa_set_ac97_info(NULL);
165}
166#else
167static inline void colibri_pxa310_init_ac97(void) {}
168#endif
169
170void __init colibri_pxa300_init(void)
171{
172 colibri_pxa300_init_eth();
173 colibri_pxa300_init_ohci();
174 colibri_pxa300_init_lcd();
175 colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO));
176 colibri_pxa310_init_ac97();
177 colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config),
178 mfp_to_gpio(MFP_PIN_GPIO13));
179}
180
181MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
182 .phys_io = 0x40000000,
183 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
184 .boot_params = COLIBRI_SDRAM_BASE + 0x100,
185 .init_machine = colibri_pxa300_init,
186 .map_io = pxa_map_io,
187 .init_irq = pxa3xx_init_irq,
188 .timer = &pxa_timer,
189MACHINE_END
190
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
new file mode 100644
index 000000000000..573a9a1dd529
--- /dev/null
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -0,0 +1,187 @@
1/*
2 * arch/arm/mach-pxa/colibri-pxa320.c
3 *
4 * Support for Toradex PXA320/310 based Colibri module
5 *
6 * Daniel Mack <daniel@caiaq.de>
7 * Matthias Meier <matthias.j.meier@gmx.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <net/ax88796.h>
19
20#include <asm/mach-types.h>
21#include <asm/sizes.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/irq.h>
24
25#include <mach/pxa3xx-regs.h>
26#include <mach/mfp-pxa320.h>
27#include <mach/colibri.h>
28#include <mach/pxafb.h>
29#include <mach/ohci.h>
30
31#include "generic.h"
32#include "devices.h"
33
34#if defined(CONFIG_AX88796)
35#define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO)
36
37/*
38 * Asix AX88796 Ethernet
39 */
40static struct ax_plat_data colibri_asix_platdata = {
41 .flags = AXFLG_MAC_FROMDEV,
42 .wordlength = 2
43};
44
45static struct resource colibri_asix_resource[] = {
46 [0] = {
47 .start = PXA3xx_CS2_PHYS,
48 .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1,
49 .flags = IORESOURCE_MEM,
50 },
51 [1] = {
52 .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
53 .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
54 .flags = IORESOURCE_IRQ
55 }
56};
57
58static struct platform_device asix_device = {
59 .name = "ax88796",
60 .id = 0,
61 .num_resources = ARRAY_SIZE(colibri_asix_resource),
62 .resource = colibri_asix_resource,
63 .dev = {
64 .platform_data = &colibri_asix_platdata
65 }
66};
67
68static mfp_cfg_t colibri_pxa320_eth_pin_config[] __initdata = {
69 GPIO3_nCS2, /* AX88796 chip select */
70 GPIO36_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */
71};
72
73static void __init colibri_pxa320_init_eth(void)
74{
75 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_eth_pin_config));
76 set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING);
77 platform_device_register(&asix_device);
78}
79#else
80static inline void __init colibri_pxa320_init_eth(void) {}
81#endif /* CONFIG_AX88796 */
82
83#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
84static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = {
85 GPIO2_2_USBH_PEN,
86 GPIO3_2_USBH_PWR,
87};
88
89static struct pxaohci_platform_data colibri_pxa320_ohci_info = {
90 .port_mode = PMM_GLOBAL_MODE,
91 .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
92};
93
94void __init colibri_pxa320_init_ohci(void)
95{
96 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config));
97 pxa_set_ohci_info(&colibri_pxa320_ohci_info);
98}
99#else
100static inline void colibri_pxa320_init_ohci(void) {}
101#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
102
103static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
104 GPIO22_MMC1_CLK,
105 GPIO23_MMC1_CMD,
106 GPIO18_MMC1_DAT0,
107 GPIO19_MMC1_DAT1,
108 GPIO20_MMC1_DAT2,
109 GPIO21_MMC1_DAT3
110};
111
112#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
113static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = {
114 GPIO6_2_LCD_LDD_0,
115 GPIO7_2_LCD_LDD_1,
116 GPIO8_2_LCD_LDD_2,
117 GPIO9_2_LCD_LDD_3,
118 GPIO10_2_LCD_LDD_4,
119 GPIO11_2_LCD_LDD_5,
120 GPIO12_2_LCD_LDD_6,
121 GPIO13_2_LCD_LDD_7,
122 GPIO63_LCD_LDD_8,
123 GPIO64_LCD_LDD_9,
124 GPIO65_LCD_LDD_10,
125 GPIO66_LCD_LDD_11,
126 GPIO67_LCD_LDD_12,
127 GPIO68_LCD_LDD_13,
128 GPIO69_LCD_LDD_14,
129 GPIO70_LCD_LDD_15,
130 GPIO71_LCD_LDD_16,
131 GPIO72_LCD_LDD_17,
132 GPIO73_LCD_CS_N,
133 GPIO74_LCD_VSYNC,
134 GPIO14_2_LCD_FCLK,
135 GPIO15_2_LCD_LCLK,
136 GPIO16_2_LCD_PCLK,
137 GPIO17_2_LCD_BIAS,
138};
139
140static void __init colibri_pxa320_init_lcd(void)
141{
142 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_lcd_pin_config));
143}
144#else
145static inline void colibri_pxa320_init_lcd(void) {}
146#endif
147
148#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE)
149static mfp_cfg_t colibri_pxa320_ac97_pin_config[] __initdata = {
150 GPIO34_AC97_SYSCLK,
151 GPIO35_AC97_SDATA_IN_0,
152 GPIO37_AC97_SDATA_OUT,
153 GPIO38_AC97_SYNC,
154 GPIO39_AC97_BITCLK,
155 GPIO40_AC97_nACRESET
156};
157
158static inline void __init colibri_pxa320_init_ac97(void)
159{
160 pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_ac97_pin_config));
161 pxa_set_ac97_info(NULL);
162}
163#else
164static inline void colibri_pxa320_init_ac97(void) {}
165#endif
166
167void __init colibri_pxa320_init(void)
168{
169 colibri_pxa320_init_eth();
170 colibri_pxa320_init_ohci();
171 colibri_pxa320_init_lcd();
172 colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO));
173 colibri_pxa320_init_ac97();
174 colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
175 mfp_to_gpio(MFP_PIN_GPIO28));
176}
177
178MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
179 .phys_io = 0x40000000,
180 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
181 .boot_params = COLIBRI_SDRAM_BASE + 0x100,
182 .init_machine = colibri_pxa320_init,
183 .map_io = pxa_map_io,
184 .init_irq = pxa3xx_init_irq,
185 .timer = &pxa_timer,
186MACHINE_END
187
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
new file mode 100644
index 000000000000..12d0afc54aa5
--- /dev/null
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -0,0 +1,121 @@
1/*
2 * arch/arm/mach-pxa/colibri-pxa3xx.c
3 *
4 * Common functions for all Toradex PXA3xx modules
5 *
6 * Daniel Mack <daniel@caiaq.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/gpio.h>
17#include <asm/mach-types.h>
18#include <mach/hardware.h>
19#include <asm/sizes.h>
20#include <asm/mach/arch.h>
21#include <asm/mach/irq.h>
22#include <mach/pxa3xx-regs.h>
23#include <mach/mfp-pxa300.h>
24#include <mach/colibri.h>
25#include <mach/mmc.h>
26#include <mach/pxafb.h>
27
28#include "generic.h"
29#include "devices.h"
30
31#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
32static int mmc_detect_pin;
33
34static int colibri_pxa3xx_mci_init(struct device *dev,
35 irq_handler_t colibri_mmc_detect_int,
36 void *data)
37{
38 int ret;
39
40 ret = gpio_request(mmc_detect_pin, "mmc card detect");
41 if (ret)
42 return ret;
43
44 gpio_direction_input(mmc_detect_pin);
45 ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int,
46 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
47 "MMC card detect", data);
48 if (ret) {
49 gpio_free(mmc_detect_pin);
50 return ret;
51 }
52
53 return 0;
54}
55
56static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
57{
58 free_irq(mmc_detect_pin, data);
59 gpio_free(gpio_to_irq(mmc_detect_pin));
60}
61
62static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
63 .detect_delay = 20,
64 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
65 .init = colibri_pxa3xx_mci_init,
66 .exit = colibri_pxa3xx_mci_exit,
67};
68
69void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin)
70{
71 pxa3xx_mfp_config(pins, len);
72 mmc_detect_pin = detect_pin;
73 pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data);
74}
75#endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */
76
77#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
78static int lcd_bl_pin;
79
80/*
81 * LCD panel (Sharp LQ043T3DX02)
82 */
83static void colibri_lcd_backlight(int on)
84{
85 gpio_set_value(lcd_bl_pin, !!on);
86}
87
88static struct pxafb_mode_info sharp_lq43_mode = {
89 .pixclock = 101936,
90 .xres = 480,
91 .yres = 272,
92 .bpp = 32,
93 .depth = 18,
94 .hsync_len = 41,
95 .left_margin = 2,
96 .right_margin = 2,
97 .vsync_len = 10,
98 .upper_margin = 2,
99 .lower_margin = 2,
100 .sync = 0,
101 .cmap_greyscale = 0,
102};
103
104static struct pxafb_mach_info sharp_lq43_info = {
105 .modes = &sharp_lq43_mode,
106 .num_modes = 1,
107 .cmap_inverse = 0,
108 .cmap_static = 0,
109 .lcd_conn = LCD_COLOR_TFT_18BPP,
110 .pxafb_backlight_power = colibri_lcd_backlight,
111};
112
113void __init colibri_pxa3xx_init_lcd(int bl_pin)
114{
115 lcd_bl_pin = bl_pin;
116 gpio_request(bl_pin, "lcd backlight");
117 gpio_direction_output(bl_pin, 0);
118 set_pxa_fb_info(&sharp_lq43_info);
119}
120#endif
121
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c
deleted file mode 100644
index 01217e01f7d2..000000000000
--- a/arch/arm/mach-pxa/dma.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * linux/arch/arm/mach-pxa/dma.c
3 *
4 * PXA DMA registration and IRQ dispatching
5 *
6 * Author: Nicolas Pitre
7 * Created: Nov 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/errno.h>
20
21#include <asm/system.h>
22#include <asm/irq.h>
23#include <mach/hardware.h>
24#include <mach/dma.h>
25
26struct dma_channel {
27 char *name;
28 pxa_dma_prio prio;
29 void (*irq_handler)(int, void *);
30 void *data;
31};
32
33static struct dma_channel *dma_channels;
34static int num_dma_channels;
35
36int pxa_request_dma (char *name, pxa_dma_prio prio,
37 void (*irq_handler)(int, void *),
38 void *data)
39{
40 unsigned long flags;
41 int i, found = 0;
42
43 /* basic sanity checks */
44 if (!name || !irq_handler)
45 return -EINVAL;
46
47 local_irq_save(flags);
48
49 do {
50 /* try grabbing a DMA channel with the requested priority */
51 for (i = 0; i < num_dma_channels; i++) {
52 if ((dma_channels[i].prio == prio) &&
53 !dma_channels[i].name) {
54 found = 1;
55 break;
56 }
57 }
58 /* if requested prio group is full, try a hier priority */
59 } while (!found && prio--);
60
61 if (found) {
62 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
63 dma_channels[i].name = name;
64 dma_channels[i].irq_handler = irq_handler;
65 dma_channels[i].data = data;
66 } else {
67 printk (KERN_WARNING "No more available DMA channels for %s\n", name);
68 i = -ENODEV;
69 }
70
71 local_irq_restore(flags);
72 return i;
73}
74
75void pxa_free_dma (int dma_ch)
76{
77 unsigned long flags;
78
79 if (!dma_channels[dma_ch].name) {
80 printk (KERN_CRIT
81 "%s: trying to free channel %d which is already freed\n",
82 __func__, dma_ch);
83 return;
84 }
85
86 local_irq_save(flags);
87 DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
88 dma_channels[dma_ch].name = NULL;
89 local_irq_restore(flags);
90}
91
92static irqreturn_t dma_irq_handler(int irq, void *dev_id)
93{
94 int i, dint = DINT;
95
96 for (i = 0; i < num_dma_channels; i++) {
97 if (dint & (1 << i)) {
98 struct dma_channel *channel = &dma_channels[i];
99 if (channel->name && channel->irq_handler) {
100 channel->irq_handler(i, channel->data);
101 } else {
102 /*
103 * IRQ for an unregistered DMA channel:
104 * let's clear the interrupts and disable it.
105 */
106 printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i);
107 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
108 }
109 }
110 }
111 return IRQ_HANDLED;
112}
113
114int __init pxa_init_dma(int irq, int num_ch)
115{
116 int i, ret;
117
118 dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL);
119 if (dma_channels == NULL)
120 return -ENOMEM;
121
122 /* dma channel priorities on pxa2xx processors:
123 * ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
124 * ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
125 * ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
126 */
127 for (i = 0; i < num_ch; i++) {
128 DCSR(i) = 0;
129 dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
130 }
131
132 ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
133 if (ret) {
134 printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
135 kfree(dma_channels);
136 return ret;
137 }
138
139 num_dma_channels = num_ch;
140 return 0;
141}
142
143EXPORT_SYMBOL(pxa_request_dma);
144EXPORT_SYMBOL(pxa_free_dma);
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
index e0c3aaf1ecb3..54af7ed1397e 100644
--- a/arch/arm/mach-pxa/e740.c
+++ b/arch/arm/mach-pxa/e740.c
@@ -187,7 +187,7 @@ static void __init e740_init(void)
187{ 187{
188 pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); 188 pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
189 eseries_register_clks(); 189 eseries_register_clks();
190 clk_add_alias("CLK_CK48M", &e740_t7l66xb_device.dev, 190 clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
191 "UDCCLK", &pxa25x_device_udc.dev), 191 "UDCCLK", &pxa25x_device_udc.dev),
192 eseries_get_tmio_gpios(); 192 eseries_get_tmio_gpios();
193 platform_add_devices(devices, ARRAY_SIZE(devices)); 193 platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c
index 84b050f1a996..16ae72150b1b 100644
--- a/arch/arm/mach-pxa/e750.c
+++ b/arch/arm/mach-pxa/e750.c
@@ -188,7 +188,7 @@ static struct platform_device *devices[] __initdata = {
188static void __init e750_init(void) 188static void __init e750_init(void)
189{ 189{
190 pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); 190 pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config));
191 clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev, 191 clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name,
192 "GPIO11_CLK", NULL), 192 "GPIO11_CLK", NULL),
193 eseries_get_tmio_gpios(); 193 eseries_get_tmio_gpios();
194 platform_add_devices(devices, ARRAY_SIZE(devices)); 194 platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c
index f8924f6ca544..74ab09812a72 100644
--- a/arch/arm/mach-pxa/e800.c
+++ b/arch/arm/mach-pxa/e800.c
@@ -194,7 +194,7 @@ static struct platform_device *devices[] __initdata = {
194 194
195static void __init e800_init(void) 195static void __init e800_init(void)
196{ 196{
197 clk_add_alias("CLK_CK3P6MI", &e800_tc6393xb_device.dev, 197 clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
198 "GPIO11_CLK", NULL), 198 "GPIO11_CLK", NULL),
199 eseries_get_tmio_gpios(); 199 eseries_get_tmio_gpios();
200 platform_add_devices(devices, ARRAY_SIZE(devices)); 200 platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
deleted file mode 100644
index 7c2267036bf1..000000000000
--- a/arch/arm/mach-pxa/gpio.c
+++ /dev/null
@@ -1,365 +0,0 @@
1/*
2 * linux/arch/arm/mach-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/sysdev.h>
19#include <linux/bootmem.h>
20
21#include <mach/gpio.h>
22
23int pxa_last_gpio;
24
25/*
26 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
27 * one set of registers. The register offsets are organized below:
28 *
29 * GPLR GPDR GPSR GPCR GRER GFER GEDR
30 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
31 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
32 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
33 *
34 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
35 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
36 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
37 *
38 * NOTE:
39 * BANK 3 is only available on PXA27x and later processors.
40 * BANK 4 and 5 are only available on PXA935
41 */
42
43#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
44
45#define GPLR_OFFSET 0x00
46#define GPDR_OFFSET 0x0C
47#define GPSR_OFFSET 0x18
48#define GPCR_OFFSET 0x24
49#define GRER_OFFSET 0x30
50#define GFER_OFFSET 0x3C
51#define GEDR_OFFSET 0x48
52
53struct pxa_gpio_chip {
54 struct gpio_chip chip;
55 void __iomem *regbase;
56 char label[10];
57
58 unsigned long irq_mask;
59 unsigned long irq_edge_rise;
60 unsigned long irq_edge_fall;
61
62#ifdef CONFIG_PM
63 unsigned long saved_gplr;
64 unsigned long saved_gpdr;
65 unsigned long saved_grer;
66 unsigned long saved_gfer;
67#endif
68};
69
70static DEFINE_SPINLOCK(gpio_lock);
71static struct pxa_gpio_chip *pxa_gpio_chips;
72
73#define for_each_gpio_chip(i, c) \
74 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
75
76static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
77{
78 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
79}
80
81static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio)
82{
83 return &pxa_gpio_chips[gpio_to_bank(gpio)];
84}
85
86static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
87{
88 void __iomem *base = gpio_chip_base(chip);
89 uint32_t value, mask = 1 << offset;
90 unsigned long flags;
91
92 spin_lock_irqsave(&gpio_lock, flags);
93
94 value = __raw_readl(base + GPDR_OFFSET);
95 if (__gpio_is_inverted(chip->base + offset))
96 value |= mask;
97 else
98 value &= ~mask;
99 __raw_writel(value, base + GPDR_OFFSET);
100
101 spin_unlock_irqrestore(&gpio_lock, flags);
102 return 0;
103}
104
105static int pxa_gpio_direction_output(struct gpio_chip *chip,
106 unsigned offset, int value)
107{
108 void __iomem *base = gpio_chip_base(chip);
109 uint32_t tmp, mask = 1 << offset;
110 unsigned long flags;
111
112 __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
113
114 spin_lock_irqsave(&gpio_lock, flags);
115
116 tmp = __raw_readl(base + GPDR_OFFSET);
117 if (__gpio_is_inverted(chip->base + offset))
118 tmp &= ~mask;
119 else
120 tmp |= mask;
121 __raw_writel(tmp, base + GPDR_OFFSET);
122
123 spin_unlock_irqrestore(&gpio_lock, flags);
124 return 0;
125}
126
127static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
128{
129 return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
130}
131
132static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
133{
134 __raw_writel(1 << offset, gpio_chip_base(chip) +
135 (value ? GPSR_OFFSET : GPCR_OFFSET));
136}
137
138static int __init pxa_init_gpio_chip(int gpio_end)
139{
140 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
141 struct pxa_gpio_chip *chips;
142
143 /* this is early, we have to use bootmem allocator, and we really
144 * want this to be allocated dynamically for different 'gpio_end'
145 */
146 chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip));
147 if (chips == NULL) {
148 pr_err("%s: failed to allocate GPIO chips\n", __func__);
149 return -ENOMEM;
150 }
151
152 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
153 struct gpio_chip *c = &chips[i].chip;
154
155 sprintf(chips[i].label, "gpio-%d", i);
156 chips[i].regbase = (void __iomem *)GPIO_BANK(i);
157
158 c->base = gpio;
159 c->label = chips[i].label;
160
161 c->direction_input = pxa_gpio_direction_input;
162 c->direction_output = pxa_gpio_direction_output;
163 c->get = pxa_gpio_get;
164 c->set = pxa_gpio_set;
165
166 /* number of GPIOs on last bank may be less than 32 */
167 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
168 gpiochip_add(c);
169 }
170 pxa_gpio_chips = chips;
171 return 0;
172}
173
174static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
175{
176 struct pxa_gpio_chip *c;
177 int gpio = irq_to_gpio(irq);
178 unsigned long gpdr, mask = GPIO_bit(gpio);
179
180 c = gpio_to_chip(gpio);
181
182 if (type == IRQ_TYPE_PROBE) {
183 /* Don't mess with enabled GPIOs using preconfigured edges or
184 * GPIOs set to alternate function or to output during probe
185 */
186 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
187 return 0;
188
189 if (__gpio_is_occupied(gpio))
190 return 0;
191
192 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
193 }
194
195 gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
196
197 if (__gpio_is_inverted(gpio))
198 __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET);
199 else
200 __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
201
202 if (type & IRQ_TYPE_EDGE_RISING)
203 c->irq_edge_rise |= mask;
204 else
205 c->irq_edge_rise &= ~mask;
206
207 if (type & IRQ_TYPE_EDGE_FALLING)
208 c->irq_edge_fall |= mask;
209 else
210 c->irq_edge_fall &= ~mask;
211
212 __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET);
213 __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
214
215 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
216 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
217 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
218 return 0;
219}
220
221static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
222{
223 struct pxa_gpio_chip *c;
224 int loop, gpio, gpio_base, n;
225 unsigned long gedr;
226
227 do {
228 loop = 0;
229 for_each_gpio_chip(gpio, c) {
230 gpio_base = c->chip.base;
231
232 gedr = __raw_readl(c->regbase + GEDR_OFFSET);
233 gedr = gedr & c->irq_mask;
234 __raw_writel(gedr, c->regbase + GEDR_OFFSET);
235
236 n = find_first_bit(&gedr, BITS_PER_LONG);
237 while (n < BITS_PER_LONG) {
238 loop = 1;
239
240 generic_handle_irq(gpio_to_irq(gpio_base + n));
241 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
242 }
243 }
244 } while (loop);
245}
246
247static void pxa_ack_muxed_gpio(unsigned int irq)
248{
249 int gpio = irq_to_gpio(irq);
250 struct pxa_gpio_chip *c = gpio_to_chip(gpio);
251
252 __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
253}
254
255static void pxa_mask_muxed_gpio(unsigned int irq)
256{
257 int gpio = irq_to_gpio(irq);
258 struct pxa_gpio_chip *c = gpio_to_chip(gpio);
259 uint32_t grer, gfer;
260
261 c->irq_mask &= ~GPIO_bit(gpio);
262
263 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
264 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
265 __raw_writel(grer, c->regbase + GRER_OFFSET);
266 __raw_writel(gfer, c->regbase + GFER_OFFSET);
267}
268
269static void pxa_unmask_muxed_gpio(unsigned int irq)
270{
271 int gpio = irq_to_gpio(irq);
272 struct pxa_gpio_chip *c = gpio_to_chip(gpio);
273
274 c->irq_mask |= GPIO_bit(gpio);
275 __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET);
276 __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
277}
278
279static struct irq_chip pxa_muxed_gpio_chip = {
280 .name = "GPIO",
281 .ack = pxa_ack_muxed_gpio,
282 .mask = pxa_mask_muxed_gpio,
283 .unmask = pxa_unmask_muxed_gpio,
284 .set_type = pxa_gpio_irq_type,
285};
286
287void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
288{
289 struct pxa_gpio_chip *c;
290 int gpio, irq;
291
292 pxa_last_gpio = end;
293
294 /* Initialize GPIO chips */
295 pxa_init_gpio_chip(end);
296
297 /* clear all GPIO edge detects */
298 for_each_gpio_chip(gpio, c) {
299 __raw_writel(0, c->regbase + GFER_OFFSET);
300 __raw_writel(0, c->regbase + GRER_OFFSET);
301 __raw_writel(~0,c->regbase + GEDR_OFFSET);
302 }
303
304 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
305 set_irq_chip(irq, &pxa_muxed_gpio_chip);
306 set_irq_handler(irq, handle_edge_irq);
307 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
308 }
309
310 /* Install handler for GPIO>=2 edge detect interrupts */
311 set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
312 pxa_muxed_gpio_chip.set_wake = fn;
313}
314
315#ifdef CONFIG_PM
316static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
317{
318 struct pxa_gpio_chip *c;
319 int gpio;
320
321 for_each_gpio_chip(gpio, c) {
322 c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
323 c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
324 c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
325 c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
326
327 /* Clear GPIO transition detect bits */
328 __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
329 }
330 return 0;
331}
332
333static int pxa_gpio_resume(struct sys_device *dev)
334{
335 struct pxa_gpio_chip *c;
336 int gpio;
337
338 for_each_gpio_chip(gpio, c) {
339 /* restore level with set/clear */
340 __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
341 __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
342
343 __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
344 __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
345 __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
346 }
347 return 0;
348}
349#else
350#define pxa_gpio_suspend NULL
351#define pxa_gpio_resume NULL
352#endif
353
354struct sysdev_class pxa_gpio_sysclass = {
355 .name = "gpio",
356 .suspend = pxa_gpio_suspend,
357 .resume = pxa_gpio_resume,
358};
359
360static int __init pxa_gpio_init(void)
361{
362 return sysdev_class_register(&pxa_gpio_sysclass);
363}
364
365core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 2ae373fb5675..3f2a01d6a03c 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -1,19 +1,31 @@
1#ifndef _COLIBRI_H_ 1#ifndef _COLIBRI_H_
2#define _COLIBRI_H_ 2#define _COLIBRI_H_
3/*
4 * common settings for all modules
5 */
6
7#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
8extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin);
9#else
10static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *, int, int) {}
11#endif
12
13#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
14extern void colibri_pxa3xx_init_lcd(int bl_pin);
15#else
16static inline void colibri_pxa3xx_init_lcd(int) {}
17#endif
3 18
4/* physical memory regions */ 19/* physical memory regions */
5#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
6#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
7#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ 20#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
8 21
9/* virtual memory regions */ 22/* definitions for Colibri PXA270 */
10#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */
11 23
12/* size of flash */ 24#define COLIBRI_PXA270_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
13#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ 25#define COLIBRI_PXA270_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet */
14 26#define COLIBRI_PXA270_ETH_IRQ_GPIO 114
15/* Ethernet Controller Davicom DM9000 */ 27#define COLIBRI_PXA270_ETH_IRQ \
16#define GPIO_DM9000 114 28 gpio_to_irq(mfp_to_gpio(COLIBRI_PXA270_ETH_IRQ_GPIO))
17#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
18 29
19#endif /* _COLIBRI_H_ */ 30#endif /* _COLIBRI_H_ */
31
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index b0812f59d3f8..5bd55894a48d 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -16,87 +16,6 @@
16 16
17/* DMA Controller Registers Definitions */ 17/* DMA Controller Registers Definitions */
18#define DMAC_REGS_VIRT io_p2v(0x40000000) 18#define DMAC_REGS_VIRT io_p2v(0x40000000)
19#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
20
21#define DCSR(n) DMAC_REG((n) << 2)
22#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
23#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
24#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
25#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
26#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
27#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
28#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
29 (((n) & 0x3f) << 2))
30
31#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
32#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
33#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
34#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
35#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
36#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
37#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
38#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
39
40#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
41#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
42#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
43#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
44#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
45#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
46#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
47#define DCSR_EORINTR (1 << 9) /* The end of Receive */
48#endif
49
50#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
51#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
52
53#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
54#define DDADR_STOP (1 << 0) /* Stop (read / write) */
55
56#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
57#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
58#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
59#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
60#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
61#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
62#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
63#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
64#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
65#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
66#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
67#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
68#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
69#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
70
71/*
72 * Descriptor structure for PXA's DMA engine
73 * Note: this structure must always be aligned to a 16-byte boundary.
74 */
75
76typedef struct pxa_dma_desc {
77 volatile u32 ddadr; /* Points to the next descriptor + flags */
78 volatile u32 dsadr; /* DSADR value for the current transfer */
79 volatile u32 dtadr; /* DTADR value for the current transfer */
80 volatile u32 dcmd; /* DCMD value for the current transfer */
81} pxa_dma_desc;
82
83typedef enum {
84 DMA_PRIO_HIGH = 0,
85 DMA_PRIO_MEDIUM = 1,
86 DMA_PRIO_LOW = 2
87} pxa_dma_prio;
88
89/*
90 * DMA registration
91 */
92
93int __init pxa_init_dma(int irq, int num_ch);
94
95int pxa_request_dma (char *name,
96 pxa_dma_prio prio,
97 void (*irq_handler)(int, void *),
98 void *data);
99
100void pxa_free_dma (int dma_ch);
101 19
20#include <plat/dma.h>
102#endif /* _ASM_ARCH_DMA_H */ 21#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index c72c89a2285e..b024a8b37439 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -99,40 +99,12 @@
99#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) 99#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
100 100
101 101
102/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
103 * Those cases currently cause holes in the GPIO number space, the
104 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
105 */
106extern int pxa_last_gpio;
107
108#define NR_BUILTIN_GPIO 128 102#define NR_BUILTIN_GPIO 128
109 103
110static inline int gpio_get_value(unsigned gpio)
111{
112 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
113 return GPLR(gpio) & GPIO_bit(gpio);
114 else
115 return __gpio_get_value(gpio);
116}
117
118static inline void gpio_set_value(unsigned gpio, int value)
119{
120 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
121 if (value)
122 GPSR(gpio) = GPIO_bit(gpio);
123 else
124 GPCR(gpio) = GPIO_bit(gpio);
125 } else {
126 __gpio_set_value(gpio, value);
127 }
128}
129
130#define gpio_cansleep __gpio_cansleep
131#define gpio_to_bank(gpio) ((gpio) >> 5) 104#define gpio_to_bank(gpio) ((gpio) >> 5)
132#define gpio_to_irq(gpio) IRQ_GPIO(gpio) 105#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
133#define irq_to_gpio(irq) IRQ_TO_GPIO(irq) 106#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
134 107
135
136#ifdef CONFIG_CPU_PXA26x 108#ifdef CONFIG_CPU_PXA26x
137/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, 109/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
138 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 110 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
@@ -165,7 +137,5 @@ static inline int __gpio_is_occupied(unsigned gpio)
165 return GPDR(gpio) & GPIO_bit(gpio); 137 return GPDR(gpio) & GPIO_bit(gpio);
166} 138}
167 139
168typedef int (*set_wake_t)(unsigned int irq, unsigned int on); 140#include <plat/gpio.h>
169
170extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
171#endif 141#endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index a72869b73ee3..b13dc0269a6d 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -1,7 +1,6 @@
1#ifndef __ASM_ARCH_MFP_PXA25X_H 1#ifndef __ASM_ARCH_MFP_PXA25X_H
2#define __ASM_ARCH_MFP_PXA25X_H 2#define __ASM_ARCH_MFP_PXA25X_H
3 3
4#include <mach/mfp.h>
5#include <mach/mfp-pxa2xx.h> 4#include <mach/mfp-pxa2xx.h>
6 5
7/* GPIO */ 6/* GPIO */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index da4f85a4f990..6543c05f47ed 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -8,7 +8,6 @@
8 * specific controller, and this should work in most cases. 8 * specific controller, and this should work in most cases.
9 */ 9 */
10 10
11#include <mach/mfp.h>
12#include <mach/mfp-pxa2xx.h> 11#include <mach/mfp-pxa2xx.h>
13 12
14/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN 13/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index 3e9211591e20..658b28ed129b 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_ARCH_MFP_PXA2XX_H 1#ifndef __ASM_ARCH_MFP_PXA2XX_H
2#define __ASM_ARCH_MFP_PXA2XX_H 2#define __ASM_ARCH_MFP_PXA2XX_H
3 3
4#include <mach/mfp.h> 4#include <plat/mfp.h>
5 5
6/* 6/*
7 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: 7 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
index bc1fb33a6e70..ae8441192ef0 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
@@ -15,7 +15,6 @@
15#ifndef __ASM_ARCH_MFP_PXA300_H 15#ifndef __ASM_ARCH_MFP_PXA300_H
16#define __ASM_ARCH_MFP_PXA300_H 16#define __ASM_ARCH_MFP_PXA300_H
17 17
18#include <mach/mfp.h>
19#include <mach/mfp-pxa3xx.h> 18#include <mach/mfp-pxa3xx.h>
20 19
21/* GPIO */ 20/* GPIO */
@@ -41,6 +40,7 @@
41#endif 40#endif
42 41
43/* Chip Select */ 42/* Chip Select */
43#define GPIO1_nCS2 MFP_CFG(GPIO1, AF1)
44#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) 44#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1)
45 45
46/* AC97 */ 46/* AC97 */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
index 67f8385ea548..07897e61d05a 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -15,7 +15,6 @@
15#ifndef __ASM_ARCH_MFP_PXA320_H 15#ifndef __ASM_ARCH_MFP_PXA320_H
16#define __ASM_ARCH_MFP_PXA320_H 16#define __ASM_ARCH_MFP_PXA320_H
17 17
18#include <mach/mfp.h>
19#include <mach/mfp-pxa3xx.h> 18#include <mach/mfp-pxa3xx.h>
20 19
21/* GPIO */ 20/* GPIO */
@@ -38,6 +37,7 @@
38#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) 37#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0)
39 38
40/* Chip Select */ 39/* Chip Select */
40#define GPIO3_nCS2 MFP_CFG(GPIO3, AF1)
41#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) 41#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1)
42 42
43/* AC97 */ 43/* AC97 */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
index 1f6b35c015d0..d375195d982b 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
@@ -1,68 +1,9 @@
1#ifndef __ASM_ARCH_MFP_PXA3XX_H 1#ifndef __ASM_ARCH_MFP_PXA3XX_H
2#define __ASM_ARCH_MFP_PXA3XX_H 2#define __ASM_ARCH_MFP_PXA3XX_H
3 3
4#define MFPR_BASE (0x40e10000) 4#include <plat/mfp.h>
5#define MFPR_SIZE (PAGE_SIZE)
6
7/* MFPR register bit definitions */
8#define MFPR_PULL_SEL (0x1 << 15)
9#define MFPR_PULLUP_EN (0x1 << 14)
10#define MFPR_PULLDOWN_EN (0x1 << 13)
11#define MFPR_SLEEP_SEL (0x1 << 9)
12#define MFPR_SLEEP_OE_N (0x1 << 7)
13#define MFPR_EDGE_CLEAR (0x1 << 6)
14#define MFPR_EDGE_FALL_EN (0x1 << 5)
15#define MFPR_EDGE_RISE_EN (0x1 << 4)
16
17#define MFPR_SLEEP_DATA(x) ((x) << 8)
18#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
19#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
20 5
21#define MFPR_EDGE_NONE (0) 6#define MFPR_BASE (0x40e10000)
22#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
23#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
24#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
25
26/*
27 * Table that determines the low power modes outputs, with actual settings
28 * used in parentheses for don't-care values. Except for the float output,
29 * the configured driven and pulled levels match, so if there is a need for
30 * non-LPM pulled output, the same configuration could probably be used.
31 *
32 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
33 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
34 *
35 * Input 0 X(0) X(0) X(0) 0
36 * Drive 0 0 0 0 X(1) 0
37 * Drive 1 0 1 X(1) 0 0
38 * Pull hi (1) 1 X(1) 1 0 0
39 * Pull lo (0) 1 X(0) 0 1 0
40 * Z (float) 1 X(0) 0 0 0
41 */
42#define MFPR_LPM_INPUT (0)
43#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
44#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
45#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
46#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
47#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
48#define MFPR_LPM_MASK (0xe080)
49
50/*
51 * The pullup and pulldown state of the MFP pin at run mode is by default
52 * determined by the selected alternate function. In case that some buggy
53 * devices need to override this default behavior, the definitions below
54 * indicates the setting of corresponding MFPR bits
55 *
56 * Definition pull_sel pullup_en pulldown_en
57 * MFPR_PULL_NONE 0 0 0
58 * MFPR_PULL_LOW 1 0 1
59 * MFPR_PULL_HIGH 1 1 0
60 * MFPR_PULL_BOTH 1 1 1
61 */
62#define MFPR_PULL_NONE (0)
63#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
64#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
65#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
66 7
67/* PXA3xx common MFP configurations - processor specific ones defined 8/* PXA3xx common MFP configurations - processor specific ones defined
68 * in mfp-pxa300.h and mfp-pxa320.h 9 * in mfp-pxa300.h and mfp-pxa320.h
@@ -197,56 +138,21 @@
197#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) 138#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
198#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) 139#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
199 140
200/* 141/* NOTE: usage of these two functions is not recommended,
201 * each MFP pin will have a MFPR register, since the offset of the 142 * use pxa3xx_mfp_config() instead.
202 * register varies between processors, the processor specific code
203 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
204 *
205 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
206 * structure, which represents a range of MFP pins from "start" to
207 * "end", with the offset begining at "offset", to define a single
208 * pin, let "end" = -1
209 *
210 * use
211 *
212 * MFP_ADDR_X() to define a range of pins
213 * MFP_ADDR() to define a single pin
214 * MFP_ADDR_END to signal the end of pin offset definitions
215 */
216struct pxa3xx_mfp_addr_map {
217 unsigned int start;
218 unsigned int end;
219 unsigned long offset;
220};
221
222#define MFP_ADDR_X(start, end, offset) \
223 { MFP_PIN_##start, MFP_PIN_##end, offset }
224
225#define MFP_ADDR(pin, offset) \
226 { MFP_PIN_##pin, -1, offset }
227
228#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
229
230/*
231 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
232 * to the MFPR register
233 */
234unsigned long pxa3xx_mfp_read(int mfp);
235void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
236
237/*
238 * pxa3xx_mfp_config - configure the MFPR registers
239 *
240 * used by board specific initialization code
241 */
242void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
243
244/*
245 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
246 * index and MFPR register offset
247 *
248 * used by processor specific code
249 */ 143 */
250void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); 144static inline unsigned long pxa3xx_mfp_read(int mfp)
251void __init pxa3xx_init_mfp(void); 145{
146 return mfp_read(mfp);
147}
148
149static inline void pxa3xx_mfp_write(int mfp, unsigned long val)
150{
151 mfp_write(mfp, val);
152}
153
154static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num)
155{
156 mfp_config(mfp_cfg, num);
157}
252#endif /* __ASM_ARCH_MFP_PXA3XX_H */ 158#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index fa73f56a1372..0d119d3b9221 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -13,7 +13,6 @@
13#ifndef __ASM_ARCH_MFP_PXA9xx_H 13#ifndef __ASM_ARCH_MFP_PXA9xx_H
14#define __ASM_ARCH_MFP_PXA9xx_H 14#define __ASM_ARCH_MFP_PXA9xx_H
15 15
16#include <mach/mfp.h>
17#include <mach/mfp-pxa3xx.h> 16#include <mach/mfp-pxa3xx.h>
18 17
19/* GPIO */ 18/* GPIO */
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c
index eb197a6e8e94..7a270eecd480 100644
--- a/arch/arm/mach-pxa/mfp-pxa3xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c
@@ -20,183 +20,9 @@
20#include <linux/sysdev.h> 20#include <linux/sysdev.h>
21 21
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <mach/mfp.h>
24#include <mach/mfp-pxa3xx.h> 23#include <mach/mfp-pxa3xx.h>
25#include <mach/pxa3xx-regs.h> 24#include <mach/pxa3xx-regs.h>
26 25
27/* mfp_spin_lock is used to ensure that MFP register configuration
28 * (most likely a read-modify-write operation) is atomic, and that
29 * mfp_table[] is consistent
30 */
31static DEFINE_SPINLOCK(mfp_spin_lock);
32
33static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
34
35struct pxa3xx_mfp_pin {
36 unsigned long config; /* -1 for not configured */
37 unsigned long mfpr_off; /* MFPRxx Register offset */
38 unsigned long mfpr_run; /* Run-Mode Register Value */
39 unsigned long mfpr_lpm; /* Low Power Mode Register Value */
40};
41
42static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
43
44/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
45static const unsigned long mfpr_lpm[] = {
46 MFPR_LPM_INPUT,
47 MFPR_LPM_DRIVE_LOW,
48 MFPR_LPM_DRIVE_HIGH,
49 MFPR_LPM_PULL_LOW,
50 MFPR_LPM_PULL_HIGH,
51 MFPR_LPM_FLOAT,
52};
53
54/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
55static const unsigned long mfpr_pull[] = {
56 MFPR_PULL_NONE,
57 MFPR_PULL_LOW,
58 MFPR_PULL_HIGH,
59 MFPR_PULL_BOTH,
60};
61
62/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
63static const unsigned long mfpr_edge[] = {
64 MFPR_EDGE_NONE,
65 MFPR_EDGE_RISE,
66 MFPR_EDGE_FALL,
67 MFPR_EDGE_BOTH,
68};
69
70#define mfpr_readl(off) \
71 __raw_readl(mfpr_mmio_base + (off))
72
73#define mfpr_writel(off, val) \
74 __raw_writel(val, mfpr_mmio_base + (off))
75
76#define mfp_configured(p) ((p)->config != -1)
77
78/*
79 * perform a read-back of any MFPR register to make sure the
80 * previous writings are finished
81 */
82#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0)
83
84static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p)
85{
86 if (mfp_configured(p))
87 mfpr_writel(p->mfpr_off, p->mfpr_run);
88}
89
90static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p)
91{
92 if (mfp_configured(p)) {
93 unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
94 if (mfpr_clr != p->mfpr_run)
95 mfpr_writel(p->mfpr_off, mfpr_clr);
96 if (p->mfpr_lpm != mfpr_clr)
97 mfpr_writel(p->mfpr_off, p->mfpr_lpm);
98 }
99}
100
101void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num)
102{
103 unsigned long flags;
104 int i;
105
106 spin_lock_irqsave(&mfp_spin_lock, flags);
107
108 for (i = 0; i < num; i++, mfp_cfgs++) {
109 unsigned long tmp, c = *mfp_cfgs;
110 struct pxa3xx_mfp_pin *p;
111 int pin, af, drv, lpm, edge, pull;
112
113 pin = MFP_PIN(c);
114 BUG_ON(pin >= MFP_PIN_MAX);
115 p = &mfp_table[pin];
116
117 af = MFP_AF(c);
118 drv = MFP_DS(c);
119 lpm = MFP_LPM_STATE(c);
120 edge = MFP_LPM_EDGE(c);
121 pull = MFP_PULL(c);
122
123 /* run-mode pull settings will conflict with MFPR bits of
124 * low power mode state, calculate mfpr_run and mfpr_lpm
125 * individually if pull != MFP_PULL_NONE
126 */
127 tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
128
129 if (likely(pull == MFP_PULL_NONE)) {
130 p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
131 p->mfpr_lpm = p->mfpr_run;
132 } else {
133 p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
134 p->mfpr_run = tmp | mfpr_pull[pull];
135 }
136
137 p->config = c; __mfp_config_run(p);
138 }
139
140 mfpr_sync();
141 spin_unlock_irqrestore(&mfp_spin_lock, flags);
142}
143
144unsigned long pxa3xx_mfp_read(int mfp)
145{
146 unsigned long val, flags;
147
148 BUG_ON(mfp >= MFP_PIN_MAX);
149
150 spin_lock_irqsave(&mfp_spin_lock, flags);
151 val = mfpr_readl(mfp_table[mfp].mfpr_off);
152 spin_unlock_irqrestore(&mfp_spin_lock, flags);
153
154 return val;
155}
156
157void pxa3xx_mfp_write(int mfp, unsigned long val)
158{
159 unsigned long flags;
160
161 BUG_ON(mfp >= MFP_PIN_MAX);
162
163 spin_lock_irqsave(&mfp_spin_lock, flags);
164 mfpr_writel(mfp_table[mfp].mfpr_off, val);
165 mfpr_sync();
166 spin_unlock_irqrestore(&mfp_spin_lock, flags);
167}
168
169void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
170{
171 struct pxa3xx_mfp_addr_map *p;
172 unsigned long offset, flags;
173 int i;
174
175 spin_lock_irqsave(&mfp_spin_lock, flags);
176
177 for (p = map; p->start != MFP_PIN_INVALID; p++) {
178 offset = p->offset;
179 i = p->start;
180
181 do {
182 mfp_table[i].mfpr_off = offset;
183 mfp_table[i].mfpr_run = 0;
184 mfp_table[i].mfpr_lpm = 0;
185 offset += 4; i++;
186 } while ((i <= p->end) && (p->end != -1));
187 }
188
189 spin_unlock_irqrestore(&mfp_spin_lock, flags);
190}
191
192void __init pxa3xx_init_mfp(void)
193{
194 int i;
195
196 for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
197 mfp_table[i].config = -1;
198}
199
200#ifdef CONFIG_PM 26#ifdef CONFIG_PM
201/* 27/*
202 * Configure the MFPs appropriately for suspend/resume. 28 * Configure the MFPs appropriately for suspend/resume.
@@ -207,23 +33,13 @@ void __init pxa3xx_init_mfp(void)
207 */ 33 */
208static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) 34static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state)
209{ 35{
210 int pin; 36 mfp_config_lpm();
211
212 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
213 struct pxa3xx_mfp_pin *p = &mfp_table[pin];
214 __mfp_config_lpm(p);
215 }
216 return 0; 37 return 0;
217} 38}
218 39
219static int pxa3xx_mfp_resume(struct sys_device *d) 40static int pxa3xx_mfp_resume(struct sys_device *d)
220{ 41{
221 int pin; 42 mfp_config_run();
222
223 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
224 struct pxa3xx_mfp_pin *p = &mfp_table[pin];
225 __mfp_config_run(p);
226 }
227 43
228 /* clear RDH bit when MFP settings are restored 44 /* clear RDH bit when MFP settings are restored
229 * 45 *
@@ -231,7 +47,6 @@ static int pxa3xx_mfp_resume(struct sys_device *d)
231 * preserve them here in case they will be referenced later 47 * preserve them here in case they will be referenced later
232 */ 48 */
233 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 49 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
234
235 return 0; 50 return 0;
236} 51}
237#else 52#else
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 37bb12d13ca2..4ba6d21f851c 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -23,7 +23,7 @@
23#include "devices.h" 23#include "devices.h"
24#include "clock.h" 24#include "clock.h"
25 25
26static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { 26static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
27 27
28 MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), 28 MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
29 MFP_ADDR_X(GPIO3, GPIO26, 0x027c), 29 MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
@@ -72,7 +72,7 @@ static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
72}; 72};
73 73
74/* override pxa300 MFP register addresses */ 74/* override pxa300 MFP register addresses */
75static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { 75static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
76 MFP_ADDR_X(GPIO30, GPIO98, 0x0418), 76 MFP_ADDR_X(GPIO30, GPIO98, 0x0418),
77 MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), 77 MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C),
78 78
@@ -98,13 +98,13 @@ static struct clk_lookup pxa310_clkregs[] = {
98static int __init pxa300_init(void) 98static int __init pxa300_init(void)
99{ 99{
100 if (cpu_is_pxa300() || cpu_is_pxa310()) { 100 if (cpu_is_pxa300() || cpu_is_pxa310()) {
101 pxa3xx_init_mfp(); 101 mfp_init_base(io_p2v(MFPR_BASE));
102 pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); 102 mfp_init_addr(pxa300_mfp_addr_map);
103 clks_register(ARRAY_AND_SIZE(common_clkregs)); 103 clks_register(ARRAY_AND_SIZE(common_clkregs));
104 } 104 }
105 105
106 if (cpu_is_pxa310()) { 106 if (cpu_is_pxa310()) {
107 pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); 107 mfp_init_addr(pxa310_mfp_addr_map);
108 clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); 108 clks_register(ARRAY_AND_SIZE(pxa310_clkregs));
109 } 109 }
110 110
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index e708f4e0ecaf..8b3d97efadab 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -23,7 +23,7 @@
23#include "devices.h" 23#include "devices.h"
24#include "clock.h" 24#include "clock.h"
25 25
26static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { 26static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
27 27
28 MFP_ADDR_X(GPIO0, GPIO4, 0x0124), 28 MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
29 MFP_ADDR_X(GPIO5, GPIO9, 0x028C), 29 MFP_ADDR_X(GPIO5, GPIO9, 0x028C),
@@ -86,8 +86,8 @@ static struct clk_lookup pxa320_clkregs[] = {
86static int __init pxa320_init(void) 86static int __init pxa320_init(void)
87{ 87{
88 if (cpu_is_pxa320()) { 88 if (cpu_is_pxa320()) {
89 pxa3xx_init_mfp(); 89 mfp_init_base(io_p2v(MFPR_BASE));
90 pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); 90 mfp_init_addr(pxa320_mfp_addr_map);
91 clks_register(ARRAY_AND_SIZE(pxa320_clkregs)); 91 clks_register(ARRAY_AND_SIZE(pxa320_clkregs));
92 } 92 }
93 93
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index f15dfa55f27f..71131742fffd 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -18,7 +18,7 @@
18 18
19#include <mach/pxa930.h> 19#include <mach/pxa930.h>
20 20
21static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = { 21static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
22 22
23 MFP_ADDR(GPIO0, 0x02e0), 23 MFP_ADDR(GPIO0, 0x02e0),
24 MFP_ADDR(GPIO1, 0x02dc), 24 MFP_ADDR(GPIO1, 0x02dc),
@@ -179,8 +179,8 @@ static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
179static int __init pxa930_init(void) 179static int __init pxa930_init(void)
180{ 180{
181 if (cpu_is_pxa930()) { 181 if (cpu_is_pxa930()) {
182 pxa3xx_init_mfp(); 182 mfp_init_base(io_p2v(MFPR_BASE));
183 pxa3xx_mfp_init_addr(pxa930_mfp_addr_map); 183 mfp_init_addr(pxa930_mfp_addr_map);
184 } 184 }
185 185
186 return 0; 186 return 0;
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 4f6f5024884e..6e8ade6ae339 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -919,7 +919,7 @@ static void __init tosa_init(void)
919 pxa2xx_set_spi_info(2, &pxa_ssp_master_info); 919 pxa2xx_set_spi_info(2, &pxa_ssp_master_info);
920 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); 920 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
921 921
922 clk_add_alias("CLK_CK3P6MI", &tc6393xb_device.dev, "GPIO11_CLK", NULL); 922 clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL);
923 923
924 platform_add_devices(devices, ARRAY_SIZE(devices)); 924 platform_add_devices(devices, ARRAY_SIZE(devices));
925} 925}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 11:31:30 -0500