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authorHaojian Zhuang <haojian.zhuang@marvell.com>2010-03-16 05:12:37 -0400
committerEric Miao <eric.y.miao@gmail.com>2010-05-11 11:24:58 -0400
commit54c39b420f017c546fb130a05c14bdb0a7910f98 (patch)
tree44d77ca073fc7c7efc3f32f1d419a4ee16b1fbd8 /arch/arm/mach-pxa
parentbe1194cca55961b4dd98ea17fb24f0ffc6fa2213 (diff)
[ARM] pxa: move ssp into common plat-pxa
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-pxa')
-rw-r--r--arch/arm/mach-pxa/Kconfig5
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/include/mach/ssp.h196
-rw-r--r--arch/arm/mach-pxa/poodle.c2
-rw-r--r--arch/arm/mach-pxa/ssp.c223
5 files changed, 1 insertions, 426 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 8f7eb12776a9..6dd450a7dea6 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -648,11 +648,6 @@ config PXA_SHARP_Cxx00
648 help 648 help
649 Enable common support for Sharp Cxx00 models 649 Enable common support for Sharp Cxx00 models
650 650
651config PXA_SSP
652 tristate
653 help
654 Enable support for PXA2xx SSP ports
655
656config TOSA_BT 651config TOSA_BT
657 tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" 652 tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
658 depends on MACH_TOSA 653 depends on MACH_TOSA
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index a83aff386fba..cf57fb2f73d8 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_PXA3xx) += cpufreq-pxa3xx.o
14endif 14endif
15 15
16# Generic drivers that other drivers may depend upon 16# Generic drivers that other drivers may depend upon
17obj-$(CONFIG_PXA_SSP) += ssp.o
18 17
19# SoC-specific code 18# SoC-specific code
20obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o 19obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h
deleted file mode 100644
index 4c4ce62390d0..000000000000
--- a/arch/arm/mach-pxa/include/mach/ssp.h
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * ssp.h
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This driver supports the following PXA CPU/SSP ports:-
11 *
12 * PXA250 SSP
13 * PXA255 SSP, NSSP
14 * PXA26x SSP, NSSP, ASSP
15 * PXA27x SSP1, SSP2, SSP3
16 * PXA3xx SSP1, SSP2, SSP3, SSP4
17 */
18
19#ifndef __ASM_ARCH_SSP_H
20#define __ASM_ARCH_SSP_H
21
22#include <linux/list.h>
23#include <linux/io.h>
24
25/*
26 * SSP Serial Port Registers
27 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
28 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
29 */
30
31#define SSCR0 (0x00) /* SSP Control Register 0 */
32#define SSCR1 (0x04) /* SSP Control Register 1 */
33#define SSSR (0x08) /* SSP Status Register */
34#define SSITR (0x0C) /* SSP Interrupt Test Register */
35#define SSDR (0x10) /* SSP Data Write/Data Read Register */
36
37#define SSTO (0x28) /* SSP Time Out Register */
38#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
39#define SSTSA (0x30) /* SSP Tx Timeslot Active */
40#define SSRSA (0x34) /* SSP Rx Timeslot Active */
41#define SSTSS (0x38) /* SSP Timeslot Status */
42#define SSACD (0x3C) /* SSP Audio Clock Divider */
43
44#if defined(CONFIG_PXA3xx)
45#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
46#endif
47
48/* Common PXA2xx bits first */
49#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
50#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
51#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
52#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
53#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
54#define SSCR0_National (0x2 << 4) /* National Microwire */
55#define SSCR0_ECS (1 << 6) /* External clock select */
56#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
57#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
58
59#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
60#define SSCR0_EDSS (1 << 20) /* Extended data size select */
61#define SSCR0_NCS (1 << 21) /* Network clock select */
62#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
63#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
64#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
65#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
66#define SSCR0_ACS (1 << 30) /* Audio clock select */
67#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
68#endif
69
70#if defined(CONFIG_PXA3xx)
71#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
72#endif
73
74#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
75#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
76#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
77#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
78#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
79#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
80#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
81#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
82#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
83#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
84
85#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
86#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
87#define SSSR_BSY (1 << 4) /* SSP Busy */
88#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
89#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
90#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
91
92#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
93#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
94#define SSCR0_NCS (1 << 21) /* Network Clock Select */
95#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
96
97/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
98#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
99#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
100#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
101#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
102#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
103#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
104#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
105#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
106#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
107#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
108#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
109#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
110#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
111#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
112#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
113#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
114#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
115#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
116#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
117
118#define SSSR_BCE (1 << 23) /* Bit Count Error */
119#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
120#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
121#define SSSR_EOC (1 << 20) /* End Of Chain */
122#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
123#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
124
125#if defined(CONFIG_PXA3xx)
126#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
127#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
128#endif
129
130#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
131#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
132#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
133#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
134#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
135#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
136#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
137#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
138#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
139
140#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
141#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
142#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
143#if defined(CONFIG_PXA3xx)
144#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
145#endif
146
147enum pxa_ssp_type {
148 SSP_UNDEFINED = 0,
149 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
150 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
151 PXA27x_SSP,
152};
153
154struct ssp_device {
155 struct platform_device *pdev;
156 struct list_head node;
157
158 struct clk *clk;
159 void __iomem *mmio_base;
160 unsigned long phys_base;
161
162 const char *label;
163 int port_id;
164 int type;
165 int use_count;
166 int irq;
167 int drcmr_rx;
168 int drcmr_tx;
169};
170
171/**
172 * ssp_write_reg - Write to a SSP register
173 *
174 * @dev: SSP device to access
175 * @reg: Register to write to
176 * @val: Value to be written.
177 */
178static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
179{
180 __raw_writel(val, dev->mmio_base + reg);
181}
182
183/**
184 * ssp_read_reg - Read from a SSP register
185 *
186 * @dev: SSP device to access
187 * @reg: Register to read from
188 */
189static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
190{
191 return __raw_readl(dev->mmio_base + reg);
192}
193
194struct ssp_device *ssp_request(int port, const char *label);
195void ssp_free(struct ssp_device *);
196#endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 48b10c783a28..dcb178807046 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -40,12 +40,12 @@
40#include <mach/pxa25x.h> 40#include <mach/pxa25x.h>
41#include <mach/mmc.h> 41#include <mach/mmc.h>
42#include <mach/udc.h> 42#include <mach/udc.h>
43#include <plat/i2c.h>
44#include <mach/irda.h> 43#include <mach/irda.h>
45#include <mach/poodle.h> 44#include <mach/poodle.h>
46#include <mach/pxafb.h> 45#include <mach/pxafb.h>
47#include <mach/sharpsl.h> 46#include <mach/sharpsl.h>
48#include <mach/pxa2xx_spi.h> 47#include <mach/pxa2xx_spi.h>
48#include <plat/i2c.h>
49 49
50#include <asm/hardware/scoop.h> 50#include <asm/hardware/scoop.h>
51#include <asm/hardware/locomo.h> 51#include <asm/hardware/locomo.h>
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
deleted file mode 100644
index a9b2d3eb8f32..000000000000
--- a/arch/arm/mach-pxa/ssp.c
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * linux/arch/arm/mach-pxa/ssp.c
3 *
4 * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King
5 *
6 * Copyright (C) 2003 Russell King.
7 * Copyright (C) 2003 Wolfson Microelectronics PLC
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * PXA2xx SSP driver. This provides the generic core for simple
14 * IO-based SSP applications and allows easy port setup for DMA access.
15 *
16 * Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com>
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/slab.h>
23#include <linux/errno.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/mutex.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/platform_device.h>
31#include <linux/io.h>
32
33#include <asm/irq.h>
34#include <mach/hardware.h>
35#include <mach/ssp.h>
36
37static DEFINE_MUTEX(ssp_lock);
38static LIST_HEAD(ssp_list);
39
40struct ssp_device *ssp_request(int port, const char *label)
41{
42 struct ssp_device *ssp = NULL;
43
44 mutex_lock(&ssp_lock);
45
46 list_for_each_entry(ssp, &ssp_list, node) {
47 if (ssp->port_id == port && ssp->use_count == 0) {
48 ssp->use_count++;
49 ssp->label = label;
50 break;
51 }
52 }
53
54 mutex_unlock(&ssp_lock);
55
56 if (&ssp->node == &ssp_list)
57 return NULL;
58
59 return ssp;
60}
61EXPORT_SYMBOL(ssp_request);
62
63void ssp_free(struct ssp_device *ssp)
64{
65 mutex_lock(&ssp_lock);
66 if (ssp->use_count) {
67 ssp->use_count--;
68 ssp->label = NULL;
69 } else
70 dev_err(&ssp->pdev->dev, "device already free\n");
71 mutex_unlock(&ssp_lock);
72}
73EXPORT_SYMBOL(ssp_free);
74
75static int __devinit ssp_probe(struct platform_device *pdev)
76{
77 const struct platform_device_id *id = platform_get_device_id(pdev);
78 struct resource *res;
79 struct ssp_device *ssp;
80 int ret = 0;
81
82 ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL);
83 if (ssp == NULL) {
84 dev_err(&pdev->dev, "failed to allocate memory");
85 return -ENOMEM;
86 }
87 ssp->pdev = pdev;
88
89 ssp->clk = clk_get(&pdev->dev, NULL);
90 if (IS_ERR(ssp->clk)) {
91 ret = PTR_ERR(ssp->clk);
92 goto err_free;
93 }
94
95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
96 if (res == NULL) {
97 dev_err(&pdev->dev, "no memory resource defined\n");
98 ret = -ENODEV;
99 goto err_free_clk;
100 }
101
102 res = request_mem_region(res->start, res->end - res->start + 1,
103 pdev->name);
104 if (res == NULL) {
105 dev_err(&pdev->dev, "failed to request memory resource\n");
106 ret = -EBUSY;
107 goto err_free_clk;
108 }
109
110 ssp->phys_base = res->start;
111
112 ssp->mmio_base = ioremap(res->start, res->end - res->start + 1);
113 if (ssp->mmio_base == NULL) {
114 dev_err(&pdev->dev, "failed to ioremap() registers\n");
115 ret = -ENODEV;
116 goto err_free_mem;
117 }
118
119 ssp->irq = platform_get_irq(pdev, 0);
120 if (ssp->irq < 0) {
121 dev_err(&pdev->dev, "no IRQ resource defined\n");
122 ret = -ENODEV;
123 goto err_free_io;
124 }
125
126 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
127 if (res == NULL) {
128 dev_err(&pdev->dev, "no SSP RX DRCMR defined\n");
129 ret = -ENODEV;
130 goto err_free_io;
131 }
132 ssp->drcmr_rx = res->start;
133
134 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
135 if (res == NULL) {
136 dev_err(&pdev->dev, "no SSP TX DRCMR defined\n");
137 ret = -ENODEV;
138 goto err_free_io;
139 }
140 ssp->drcmr_tx = res->start;
141
142 /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
143 * starts from 0, do a translation here
144 */
145 ssp->port_id = pdev->id + 1;
146 ssp->use_count = 0;
147 ssp->type = (int)id->driver_data;
148
149 mutex_lock(&ssp_lock);
150 list_add(&ssp->node, &ssp_list);
151 mutex_unlock(&ssp_lock);
152
153 platform_set_drvdata(pdev, ssp);
154 return 0;
155
156err_free_io:
157 iounmap(ssp->mmio_base);
158err_free_mem:
159 release_mem_region(res->start, res->end - res->start + 1);
160err_free_clk:
161 clk_put(ssp->clk);
162err_free:
163 kfree(ssp);
164 return ret;
165}
166
167static int __devexit ssp_remove(struct platform_device *pdev)
168{
169 struct resource *res;
170 struct ssp_device *ssp;
171
172 ssp = platform_get_drvdata(pdev);
173 if (ssp == NULL)
174 return -ENODEV;
175
176 iounmap(ssp->mmio_base);
177
178 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
179 release_mem_region(res->start, res->end - res->start + 1);
180
181 clk_put(ssp->clk);
182
183 mutex_lock(&ssp_lock);
184 list_del(&ssp->node);
185 mutex_unlock(&ssp_lock);
186
187 kfree(ssp);
188 return 0;
189}
190
191static const struct platform_device_id ssp_id_table[] = {
192 { "pxa25x-ssp", PXA25x_SSP },
193 { "pxa25x-nssp", PXA25x_NSSP },
194 { "pxa27x-ssp", PXA27x_SSP },
195 { },
196};
197
198static struct platform_driver ssp_driver = {
199 .probe = ssp_probe,
200 .remove = __devexit_p(ssp_remove),
201 .driver = {
202 .owner = THIS_MODULE,
203 .name = "pxa2xx-ssp",
204 },
205 .id_table = ssp_id_table,
206};
207
208static int __init pxa_ssp_init(void)
209{
210 return platform_driver_register(&ssp_driver);
211}
212
213static void __exit pxa_ssp_exit(void)
214{
215 platform_driver_unregister(&ssp_driver);
216}
217
218arch_initcall(pxa_ssp_init);
219module_exit(pxa_ssp_exit);
220
221MODULE_DESCRIPTION("PXA SSP driver");
222MODULE_AUTHOR("Liam Girdwood");
223MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 13:45:20 -0500