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authorEric Miao <eric.y.miao@gmail.com>2010-11-21 21:49:55 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-12-16 01:31:19 -0500
commit4029813c89926ae5d78cc2dff49d845d934424f6 (patch)
treeeaa7e075d3f369aa710ae4e26fdf80ab9cdd588b /arch/arm/mach-pxa
parent2e8581e756ddbd0dea8b0d4059e9a82d2929de01 (diff)
ARM: pxa: separate the clock support into clock-{pxa2xx,pxa3xx}.c
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-pxa')
-rw-r--r--arch/arm/mach-pxa/Makefile6
-rw-r--r--arch/arm/mach-pxa/clock-pxa2xx.c30
-rw-r--r--arch/arm/mach-pxa/clock-pxa3xx.c161
-rw-r--r--arch/arm/mach-pxa/clock.c26
-rw-r--r--arch/arm/mach-pxa/clock.h21
-rw-r--r--arch/arm/mach-pxa/pxa25x.c41
-rw-r--r--arch/arm/mach-pxa/pxa27x.c51
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c170
8 files changed, 266 insertions, 240 deletions
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index e2f89c2c6f49..c90789e3db1c 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -16,9 +16,9 @@ endif
16# Generic drivers that other drivers may depend upon 16# Generic drivers that other drivers may depend upon
17 17
18# SoC-specific code 18# SoC-specific code
19obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o 19obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
20obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o 20obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
21obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o 21obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
22obj-$(CONFIG_CPU_PXA300) += pxa300.o 22obj-$(CONFIG_CPU_PXA300) += pxa300.o
23obj-$(CONFIG_CPU_PXA320) += pxa320.o 23obj-$(CONFIG_CPU_PXA320) += pxa320.o
24obj-$(CONFIG_CPU_PXA930) += pxa930.o 24obj-$(CONFIG_CPU_PXA930) += pxa930.o
diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c
new file mode 100644
index 000000000000..416b3f06efb7
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa2xx.c
@@ -0,0 +1,30 @@
1/*
2 * linux/arch/arm/mach-pxa/clock-pxa2xx.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/init.h>
12
13#include <mach/pxa2xx-regs.h>
14
15#include "clock.h"
16
17void clk_pxa2xx_cken_enable(struct clk *clk)
18{
19 CKEN |= 1 << clk->cken;
20}
21
22void clk_pxa2xx_cken_disable(struct clk *clk)
23{
24 CKEN &= ~(1 << clk->cken);
25}
26
27const struct clkops clk_pxa2xx_cken_ops = {
28 .enable = clk_pxa2xx_cken_enable,
29 .disable = clk_pxa2xx_cken_disable,
30};
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
new file mode 100644
index 000000000000..34a36c4af19b
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -0,0 +1,161 @@
1/*
2 * linux/arch/arm/mach-pxa/clock-pxa3xx.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/init.h>
12
13#include <mach/pxa3xx-regs.h>
14
15#include "clock.h"
16
17/* Crystal clock: 13MHz */
18#define BASE_CLK 13000000
19
20/* Ring Oscillator Clock: 60MHz */
21#define RO_CLK 60000000
22
23#define ACCR_D0CS (1 << 26)
24#define ACCR_PCCE (1 << 11)
25
26/* crystal frequency to static memory controller multiplier (SMCFS) */
27static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
28
29/* crystal frequency to HSIO bus frequency multiplier (HSS) */
30static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
31
32/*
33 * Get the clock frequency as reflected by CCSR and the turbo flag.
34 * We assume these values have been applied via a fcs.
35 * If info is not 0 we also display the current settings.
36 */
37unsigned int pxa3xx_get_clk_frequency_khz(int info)
38{
39 unsigned long acsr, xclkcfg;
40 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
41
42 /* Read XCLKCFG register turbo bit */
43 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
44 t = xclkcfg & 0x1;
45
46 acsr = ACSR;
47
48 xl = acsr & 0x1f;
49 xn = (acsr >> 8) & 0x7;
50 hss = (acsr >> 14) & 0x3;
51
52 XL = xl * BASE_CLK;
53 XN = xn * XL;
54
55 ro = acsr & ACCR_D0CS;
56
57 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
58 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
59
60 if (info) {
61 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
62 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
63 (ro) ? "" : "in");
64 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
65 XL / 1000000, (XL % 1000000) / 10000, xl);
66 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
67 XN / 1000000, (XN % 1000000) / 10000, xn,
68 (t) ? "" : "in");
69 pr_info("HSIO bus clock: %d.%02dMHz\n",
70 HSS / 1000000, (HSS % 1000000) / 10000);
71 }
72
73 return CLK / 1000;
74}
75
76/*
77 * Return the current AC97 clock frequency.
78 */
79static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
80{
81 unsigned long rate = 312000000;
82 unsigned long ac97_div;
83
84 ac97_div = AC97_DIV;
85
86 /* This may loose precision for some rates but won't for the
87 * standard 24.576MHz.
88 */
89 rate /= (ac97_div >> 12) & 0x7fff;
90 rate *= (ac97_div & 0xfff);
91
92 return rate;
93}
94
95/*
96 * Return the current HSIO bus clock frequency
97 */
98static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
99{
100 unsigned long acsr;
101 unsigned int hss, hsio_clk;
102
103 acsr = ACSR;
104
105 hss = (acsr >> 14) & 0x3;
106 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
107
108 return hsio_clk;
109}
110
111void clk_pxa3xx_cken_enable(struct clk *clk)
112{
113 unsigned long mask = 1ul << (clk->cken & 0x1f);
114
115 if (clk->cken < 32)
116 CKENA |= mask;
117 else
118 CKENB |= mask;
119}
120
121void clk_pxa3xx_cken_disable(struct clk *clk)
122{
123 unsigned long mask = 1ul << (clk->cken & 0x1f);
124
125 if (clk->cken < 32)
126 CKENA &= ~mask;
127 else
128 CKENB &= ~mask;
129}
130
131const struct clkops clk_pxa3xx_cken_ops = {
132 .enable = clk_pxa3xx_cken_enable,
133 .disable = clk_pxa3xx_cken_disable,
134};
135
136const struct clkops clk_pxa3xx_hsio_ops = {
137 .enable = clk_pxa3xx_cken_enable,
138 .disable = clk_pxa3xx_cken_disable,
139 .getrate = clk_pxa3xx_hsio_getrate,
140};
141
142const struct clkops clk_pxa3xx_ac97_ops = {
143 .enable = clk_pxa3xx_cken_enable,
144 .disable = clk_pxa3xx_cken_disable,
145 .getrate = clk_pxa3xx_ac97_getrate,
146};
147
148static void clk_pout_enable(struct clk *clk)
149{
150 OSCC |= OSCC_PEN;
151}
152
153static void clk_pout_disable(struct clk *clk)
154{
155 OSCC &= ~OSCC_PEN;
156}
157
158const struct clkops clk_pxa3xx_pout_ops = {
159 .enable = clk_pout_enable,
160 .disable = clk_pout_disable,
161};
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index abba0089a2ae..8184fe2d71c3 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -3,21 +3,12 @@
3 */ 3 */
4#include <linux/module.h> 4#include <linux/module.h>
5#include <linux/kernel.h> 5#include <linux/kernel.h>
6#include <linux/list.h>
7#include <linux/errno.h>
8#include <linux/err.h>
9#include <linux/string.h>
10#include <linux/clk.h> 6#include <linux/clk.h>
11#include <linux/spinlock.h> 7#include <linux/spinlock.h>
12#include <linux/platform_device.h>
13#include <linux/delay.h> 8#include <linux/delay.h>
14 9
15#include <asm/clkdev.h> 10#include <asm/clkdev.h>
16#include <mach/pxa2xx-regs.h>
17#include <mach/hardware.h>
18 11
19#include "devices.h"
20#include "generic.h"
21#include "clock.h" 12#include "clock.h"
22 13
23static DEFINE_SPINLOCK(clocks_lock); 14static DEFINE_SPINLOCK(clocks_lock);
@@ -63,18 +54,19 @@ unsigned long clk_get_rate(struct clk *clk)
63} 54}
64EXPORT_SYMBOL(clk_get_rate); 55EXPORT_SYMBOL(clk_get_rate);
65 56
66 57void clk_dummy_enable(struct clk *clk)
67void clk_cken_enable(struct clk *clk)
68{ 58{
69 CKEN |= 1 << clk->cken;
70} 59}
71 60
72void clk_cken_disable(struct clk *clk) 61void clk_dummy_disable(struct clk *clk)
73{ 62{
74 CKEN &= ~(1 << clk->cken);
75} 63}
76 64
77const struct clkops clk_cken_ops = { 65const struct clkops clk_dummy_ops = {
78 .enable = clk_cken_enable, 66 .enable = clk_dummy_enable,
79 .disable = clk_cken_disable, 67 .disable = clk_dummy_disable,
68};
69
70struct clk clk_dummy = {
71 .ops = &clk_dummy_ops,
80}; 72};
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index f09ecb1a379e..04348781ad79 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -14,6 +14,12 @@ struct clk {
14 unsigned int enabled; 14 unsigned int enabled;
15}; 15};
16 16
17void clk_dummy_enable(struct clk *);
18void clk_dummy_disable(struct clk *);
19
20extern const struct clkops clk_dummy_ops;
21extern struct clk clk_dummy;
22
17#define INIT_CLKREG(_clk,_devname,_conname) \ 23#define INIT_CLKREG(_clk,_devname,_conname) \
18 { \ 24 { \
19 .clk = _clk, \ 25 .clk = _clk, \
@@ -34,18 +40,18 @@ struct clk clk_##_name = { \
34 .delay = _delay, \ 40 .delay = _delay, \
35 } 41 }
36 42
37#define DEFINE_CKEN(_name, _cken, _rate, _delay) \ 43#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \
38struct clk clk_##_name = { \ 44struct clk clk_##_name = { \
39 .ops = &clk_cken_ops, \ 45 .ops = &clk_pxa2xx_cken_ops, \
40 .rate = _rate, \ 46 .rate = _rate, \
41 .cken = CKEN_##_cken, \ 47 .cken = CKEN_##_cken, \
42 .delay = _delay, \ 48 .delay = _delay, \
43 } 49 }
44 50
45extern const struct clkops clk_cken_ops; 51extern const struct clkops clk_pxa2xx_cken_ops;
46 52
47void clk_cken_enable(struct clk *clk); 53void clk_pxa2xx_cken_enable(struct clk *clk);
48void clk_cken_disable(struct clk *clk); 54void clk_pxa2xx_cken_disable(struct clk *clk);
49 55
50#ifdef CONFIG_PXA3xx 56#ifdef CONFIG_PXA3xx
51#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ 57#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \
@@ -57,7 +63,10 @@ struct clk clk_##_name = { \
57 } 63 }
58 64
59extern const struct clkops clk_pxa3xx_cken_ops; 65extern const struct clkops clk_pxa3xx_cken_ops;
66extern const struct clkops clk_pxa3xx_hsio_ops;
67extern const struct clkops clk_pxa3xx_ac97_ops;
68extern const struct clkops clk_pxa3xx_pout_ops;
69
60extern void clk_pxa3xx_cken_enable(struct clk *); 70extern void clk_pxa3xx_cken_enable(struct clk *);
61extern void clk_pxa3xx_cken_disable(struct clk *); 71extern void clk_pxa3xx_cken_disable(struct clk *);
62#endif 72#endif
63
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 23136b6afa8e..f29775e3e18d 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -106,8 +106,8 @@ static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
106} 106}
107 107
108static const struct clkops clk_pxa25x_lcd_ops = { 108static const struct clkops clk_pxa25x_lcd_ops = {
109 .enable = clk_cken_enable, 109 .enable = clk_pxa2xx_cken_enable,
110 .disable = clk_cken_disable, 110 .disable = clk_pxa2xx_cken_disable,
111 .getrate = clk_pxa25x_lcd_getrate, 111 .getrate = clk_pxa25x_lcd_getrate,
112}; 112};
113 113
@@ -162,31 +162,29 @@ static const struct clkops clk_pxa25x_gpio11_ops = {
162 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz 162 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
163 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) 163 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
164 */ 164 */
165static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
166
167static struct clk_lookup pxa25x_hwuart_clkreg =
168 INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
169 165
170/* 166/*
171 * PXA 2xx clock declarations. 167 * PXA 2xx clock declarations.
172 */ 168 */
169static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
170static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
171static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
172static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
173static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
174static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
175static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
176static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
177static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
178static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
179static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
180static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
181static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
182static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
183static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
184
173static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); 185static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
174static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
175static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
176static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1);
177static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5);
178static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); 186static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
179static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); 187static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
180static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0);
181static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0);
182static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0);
183static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
184static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0);
185static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
186static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
187static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0);
188static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0);
189static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0);
190 188
191static struct clk_lookup pxa25x_clkregs[] = { 189static struct clk_lookup pxa25x_clkregs[] = {
192 INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), 190 INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
@@ -209,6 +207,9 @@ static struct clk_lookup pxa25x_clkregs[] = {
209 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), 207 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
210}; 208};
211 209
210static struct clk_lookup pxa25x_hwuart_clkreg =
211 INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
212
212#ifdef CONFIG_PM 213#ifdef CONFIG_PM
213 214
214#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 215#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 839548d94185..13242f2a3392 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -161,36 +161,37 @@ static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
161} 161}
162 162
163static const struct clkops clk_pxa27x_lcd_ops = { 163static const struct clkops clk_pxa27x_lcd_ops = {
164 .enable = clk_cken_enable, 164 .enable = clk_pxa2xx_cken_enable,
165 .disable = clk_cken_disable, 165 .disable = clk_pxa2xx_cken_disable,
166 .getrate = clk_pxa27x_lcd_getrate, 166 .getrate = clk_pxa27x_lcd_getrate,
167}; 167};
168 168
169static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
170static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
171static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
172static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
173static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
174static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
175static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
176static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
177static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
178static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
179static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
180static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
181static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
182static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
183static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
184static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
185static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
186static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
187static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
188static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
189static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
190static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
191static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
192
169static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); 193static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
170static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); 194static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
171static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
172static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
173static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
174static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
175static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
176static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
177static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
178static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
179static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
180static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
181static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
182static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
183static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
184static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
185static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
186static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
187static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
188static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
189static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
190static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
191static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
192static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
193static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
194 195
195static struct clk_lookup pxa27x_clkregs[] = { 196static struct clk_lookup pxa27x_clkregs[] = {
196 INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), 197 INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index a0b123c99a4d..b239c1ab3ed9 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -38,184 +38,15 @@
38#include "devices.h" 38#include "devices.h"
39#include "clock.h" 39#include "clock.h"
40 40
41/* Crystal clock: 13MHz */
42#define BASE_CLK 13000000
43
44/* Ring Oscillator Clock: 60MHz */
45#define RO_CLK 60000000
46
47#define ACCR_D0CS (1 << 26)
48#define ACCR_PCCE (1 << 11)
49
50#define PECR_IE(n) ((1 << ((n) * 2)) << 28) 41#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
51#define PECR_IS(n) ((1 << ((n) * 2)) << 29) 42#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
52 43
53/* crystal frequency to static memory controller multiplier (SMCFS) */
54static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
55
56/* crystal frequency to HSIO bus frequency multiplier (HSS) */
57static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
58
59/*
60 * Get the clock frequency as reflected by CCSR and the turbo flag.
61 * We assume these values have been applied via a fcs.
62 * If info is not 0 we also display the current settings.
63 */
64unsigned int pxa3xx_get_clk_frequency_khz(int info)
65{
66 unsigned long acsr, xclkcfg;
67 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
68
69 /* Read XCLKCFG register turbo bit */
70 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
71 t = xclkcfg & 0x1;
72
73 acsr = ACSR;
74
75 xl = acsr & 0x1f;
76 xn = (acsr >> 8) & 0x7;
77 hss = (acsr >> 14) & 0x3;
78
79 XL = xl * BASE_CLK;
80 XN = xn * XL;
81
82 ro = acsr & ACCR_D0CS;
83
84 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
85 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
86
87 if (info) {
88 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
89 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
90 (ro) ? "" : "in");
91 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
92 XL / 1000000, (XL % 1000000) / 10000, xl);
93 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
94 XN / 1000000, (XN % 1000000) / 10000, xn,
95 (t) ? "" : "in");
96 pr_info("HSIO bus clock: %d.%02dMHz\n",
97 HSS / 1000000, (HSS % 1000000) / 10000);
98 }
99
100 return CLK / 1000;
101}
102
103void pxa3xx_clear_reset_status(unsigned int mask) 44void pxa3xx_clear_reset_status(unsigned int mask)
104{ 45{
105 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 46 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
106 ARSR = mask; 47 ARSR = mask;
107} 48}
108 49
109/*
110 * Return the current AC97 clock frequency.
111 */
112static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
113{
114 unsigned long rate = 312000000;
115 unsigned long ac97_div;
116
117 ac97_div = AC97_DIV;
118
119 /* This may loose precision for some rates but won't for the
120 * standard 24.576MHz.
121 */
122 rate /= (ac97_div >> 12) & 0x7fff;
123 rate *= (ac97_div & 0xfff);
124
125 return rate;
126}
127
128/*
129 * Return the current HSIO bus clock frequency
130 */
131static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
132{
133 unsigned long acsr;
134 unsigned int hss, hsio_clk;
135
136 acsr = ACSR;
137
138 hss = (acsr >> 14) & 0x3;
139 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
140
141 return hsio_clk;
142}
143
144void clk_pxa3xx_cken_enable(struct clk *clk)
145{
146 unsigned long mask = 1ul << (clk->cken & 0x1f);
147
148 if (clk->cken < 32)
149 CKENA |= mask;
150 else
151 CKENB |= mask;
152}
153
154void clk_pxa3xx_cken_disable(struct clk *clk)
155{
156 unsigned long mask = 1ul << (clk->cken & 0x1f);
157
158 if (clk->cken < 32)
159 CKENA &= ~mask;
160 else
161 CKENB &= ~mask;
162}
163
164const struct clkops clk_pxa3xx_cken_ops = {
165 .enable = clk_pxa3xx_cken_enable,
166 .disable = clk_pxa3xx_cken_disable,
167};
168
169static const struct clkops clk_pxa3xx_hsio_ops = {
170 .enable = clk_pxa3xx_cken_enable,
171 .disable = clk_pxa3xx_cken_disable,
172 .getrate = clk_pxa3xx_hsio_getrate,
173};
174
175static const struct clkops clk_pxa3xx_ac97_ops = {
176 .enable = clk_pxa3xx_cken_enable,
177 .disable = clk_pxa3xx_cken_disable,
178 .getrate = clk_pxa3xx_ac97_getrate,
179};
180
181static void clk_pout_enable(struct clk *clk)
182{
183 OSCC |= OSCC_PEN;
184}
185
186static void clk_pout_disable(struct clk *clk)
187{
188 OSCC &= ~OSCC_PEN;
189}
190
191static const struct clkops clk_pout_ops = {
192 .enable = clk_pout_enable,
193 .disable = clk_pout_disable,
194};
195
196static void clk_dummy_enable(struct clk *clk)
197{
198}
199
200static void clk_dummy_disable(struct clk *clk)
201{
202}
203
204static const struct clkops clk_dummy_ops = {
205 .enable = clk_dummy_enable,
206 .disable = clk_dummy_disable,
207};
208
209static struct clk clk_pxa3xx_pout = {
210 .ops = &clk_pout_ops,
211 .rate = 13000000,
212 .delay = 70,
213};
214
215static struct clk clk_dummy = {
216 .ops = &clk_dummy_ops,
217};
218
219static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 50static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
220static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 51static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
221static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 52static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -236,6 +67,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
236static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 67static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
237static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 68static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
238static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 69static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
70static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
239 71
240static struct clk_lookup pxa3xx_clkregs[] = { 72static struct clk_lookup pxa3xx_clkregs[] = {
241 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 73 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 20:02:50 -0500