diff options
author | David Woodhouse <David.Woodhouse@intel.com> | 2009-01-05 04:50:33 -0500 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2009-01-05 04:50:33 -0500 |
commit | 353816f43d1fb340ff2d9a911dd5d0799c09f6a5 (patch) | |
tree | 517290fd884d286fe2971137ac89f89e3567785a /arch/arm/mach-pxa | |
parent | 160bbab3000dafccbe43688e48208cecf4deb879 (diff) | |
parent | fe0bdec68b77020281dc814805edfe594ae89e0f (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
arch/arm/mach-pxa/corgi.c
arch/arm/mach-pxa/poodle.c
arch/arm/mach-pxa/spitz.c
Diffstat (limited to 'arch/arm/mach-pxa')
73 files changed, 4071 insertions, 1137 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index a062235e83a8..8eea7306f29b 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
@@ -19,20 +19,34 @@ config CPU_PXA320 | |||
19 | config CPU_PXA930 | 19 | config CPU_PXA930 |
20 | bool "PXA930 (codename Tavor-P)" | 20 | bool "PXA930 (codename Tavor-P)" |
21 | 21 | ||
22 | config CPU_PXA935 | ||
23 | bool "PXA935 (codename Tavor-P65)" | ||
24 | |||
22 | endmenu | 25 | endmenu |
23 | 26 | ||
24 | endif | 27 | endif |
25 | 28 | ||
26 | config ARCH_GUMSTIX | 29 | config ARCH_GUMSTIX |
27 | bool "Gumstix XScale boards" | 30 | bool "Gumstix XScale 255 boards" |
31 | select PXA25x | ||
28 | help | 32 | help |
29 | Say Y here if you intend to run this kernel on a | 33 | Say Y here if you intend to run this kernel on |
30 | Gumstix Full Function Minature Computer. | 34 | Basix, Connex, ws-200ax, ws-400ax systems |
31 | 35 | ||
32 | config MACH_GUMSTIX_F | 36 | choice |
33 | bool "Basix, Connex, ws-200ax, ws-400ax systems" | 37 | prompt "Gumstix Carrier/Expansion Board" |
34 | depends on ARCH_GUMSTIX | 38 | depends on ARCH_GUMSTIX |
35 | select PXA25x | 39 | |
40 | config GUMSTIX_AM200EPD | ||
41 | bool "Enable AM200EPD board support" | ||
42 | |||
43 | endchoice | ||
44 | |||
45 | config MACH_INTELMOTE2 | ||
46 | bool "Intel Mote 2 Platform" | ||
47 | select PXA27x | ||
48 | select IWMMXT | ||
49 | select PXA_HAVE_BOARD_IRQS | ||
36 | 50 | ||
37 | config ARCH_LUBBOCK | 51 | config ARCH_LUBBOCK |
38 | bool "Intel DBPXA250 Development Platform" | 52 | bool "Intel DBPXA250 Development Platform" |
@@ -199,6 +213,10 @@ config MACH_E800 | |||
199 | config TRIZEPS_PXA | 213 | config TRIZEPS_PXA |
200 | bool "PXA based Keith und Koep Trizeps DIMM-Modules" | 214 | bool "PXA based Keith und Koep Trizeps DIMM-Modules" |
201 | 215 | ||
216 | config MACH_H5000 | ||
217 | bool "HP iPAQ h5000" | ||
218 | select PXA25x | ||
219 | |||
202 | config MACH_TRIZEPS4 | 220 | config MACH_TRIZEPS4 |
203 | bool "Keith und Koep Trizeps4 DIMM-Module" | 221 | bool "Keith und Koep Trizeps4 DIMM-Module" |
204 | depends on TRIZEPS_PXA | 222 | depends on TRIZEPS_PXA |
@@ -283,7 +301,6 @@ config MACH_MIOA701 | |||
283 | bool "Mitac Mio A701 Support" | 301 | bool "Mitac Mio A701 Support" |
284 | select PXA27x | 302 | select PXA27x |
285 | select IWMMXT | 303 | select IWMMXT |
286 | select LEDS_GPIO | ||
287 | select HAVE_PWM | 304 | select HAVE_PWM |
288 | select GPIO_SYSFS | 305 | select GPIO_SYSFS |
289 | help | 306 | help |
@@ -342,10 +359,6 @@ config PCM990_DISPLAY_NONE | |||
342 | 359 | ||
343 | endchoice | 360 | endchoice |
344 | 361 | ||
345 | config MACH_AM200EPD | ||
346 | depends on MACH_GUMSTIX_F | ||
347 | bool "Enable AM200EPD board support" | ||
348 | |||
349 | config PXA_EZX | 362 | config PXA_EZX |
350 | bool "Motorola EZX Platform" | 363 | bool "Motorola EZX Platform" |
351 | select PXA27x | 364 | select PXA27x |
@@ -386,16 +399,25 @@ endmenu | |||
386 | 399 | ||
387 | config PXA25x | 400 | config PXA25x |
388 | bool | 401 | bool |
402 | select CPU_XSCALE | ||
389 | help | 403 | help |
390 | Select code specific to PXA21x/25x/26x variants | 404 | Select code specific to PXA21x/25x/26x variants |
391 | 405 | ||
392 | config PXA27x | 406 | config PXA27x |
393 | bool | 407 | bool |
408 | select CPU_XSCALE | ||
394 | help | 409 | help |
395 | Select code specific to PXA27x variants | 410 | Select code specific to PXA27x variants |
396 | 411 | ||
412 | config CPU_PXA26x | ||
413 | bool | ||
414 | select PXA25x | ||
415 | help | ||
416 | Select code specific to PXA26x (codename Dalhart) | ||
417 | |||
397 | config PXA3xx | 418 | config PXA3xx |
398 | bool | 419 | bool |
420 | select CPU_XSC3 | ||
399 | help | 421 | help |
400 | Select code specific to PXA3xx variants | 422 | Select code specific to PXA3xx variants |
401 | 423 | ||
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index d64c68b232e3..7b28bb561d63 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
@@ -27,7 +27,7 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o | |||
27 | 27 | ||
28 | # Specific board support | 28 | # Specific board support |
29 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o | 29 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o |
30 | obj-$(CONFIG_MACH_AM200EPD) += am200epd.o | 30 | obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o |
31 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 31 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
32 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | 32 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o |
33 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 33 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
@@ -35,6 +35,7 @@ obj-$(CONFIG_MACH_MP900C) += mp900.o | |||
35 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o | 35 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o |
36 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o | 36 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o |
37 | obj-$(CONFIG_MACH_COLIBRI) += colibri.o | 37 | obj-$(CONFIG_MACH_COLIBRI) += colibri.o |
38 | obj-$(CONFIG_MACH_H5000) += h5000.o | ||
38 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o | 39 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o |
39 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o | 40 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o |
40 | obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o | 41 | obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o |
@@ -69,6 +70,8 @@ obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o | |||
69 | obj-$(CONFIG_MACH_CM_X300) += cm-x300.o | 70 | obj-$(CONFIG_MACH_CM_X300) += cm-x300.o |
70 | obj-$(CONFIG_PXA_EZX) += ezx.o | 71 | obj-$(CONFIG_PXA_EZX) += ezx.o |
71 | 72 | ||
73 | obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o | ||
74 | |||
72 | # Support for blinky lights | 75 | # Support for blinky lights |
73 | led-y := leds.o | 76 | led-y := leds.o |
74 | led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o | 77 | led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o |
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index b965085a37b9..77ee80e5e47b 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c | |||
@@ -30,8 +30,12 @@ | |||
30 | #include <linux/irq.h> | 30 | #include <linux/irq.h> |
31 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
32 | 32 | ||
33 | #include <mach/gumstix.h> | ||
34 | #include <mach/mfp-pxa25x.h> | ||
33 | #include <mach/pxafb.h> | 35 | #include <mach/pxafb.h> |
34 | 36 | ||
37 | #include "generic.h" | ||
38 | |||
35 | #include <video/metronomefb.h> | 39 | #include <video/metronomefb.h> |
36 | 40 | ||
37 | static unsigned int panel_type = 6; | 41 | static unsigned int panel_type = 6; |
@@ -331,7 +335,16 @@ static struct metronome_board am200_board = { | |||
331 | .cleanup = am200_cleanup, | 335 | .cleanup = am200_cleanup, |
332 | }; | 336 | }; |
333 | 337 | ||
334 | static int __init am200_init(void) | 338 | static unsigned long am200_pin_config[] __initdata = { |
339 | GPIO51_GPIO, | ||
340 | GPIO49_GPIO, | ||
341 | GPIO48_GPIO, | ||
342 | GPIO32_GPIO, | ||
343 | GPIO17_GPIO, | ||
344 | GPIO16_GPIO, | ||
345 | }; | ||
346 | |||
347 | int __init am200_init(void) | ||
335 | { | 348 | { |
336 | int ret; | 349 | int ret; |
337 | 350 | ||
@@ -339,6 +352,8 @@ static int __init am200_init(void) | |||
339 | * creation events */ | 352 | * creation events */ |
340 | fb_register_client(&am200_fb_notif); | 353 | fb_register_client(&am200_fb_notif); |
341 | 354 | ||
355 | pxa2xx_mfp_config(ARRAY_AND_SIZE(am200_pin_config)); | ||
356 | |||
342 | /* request our platform independent driver */ | 357 | /* request our platform independent driver */ |
343 | request_module("metronomefb"); | 358 | request_module("metronomefb"); |
344 | 359 | ||
@@ -367,8 +382,6 @@ static int __init am200_init(void) | |||
367 | module_param(panel_type, uint, 0); | 382 | module_param(panel_type, uint, 0); |
368 | MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97"); | 383 | MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97"); |
369 | 384 | ||
370 | module_init(am200_init); | ||
371 | |||
372 | MODULE_DESCRIPTION("board driver for am200 metronome epd kit"); | 385 | MODULE_DESCRIPTION("board driver for am200 metronome epd kit"); |
373 | MODULE_AUTHOR("Jaya Kumar"); | 386 | MODULE_AUTHOR("Jaya Kumar"); |
374 | MODULE_LICENSE("GPL"); | 387 | MODULE_LICENSE("GPL"); |
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index ca8e20538157..40b774084514 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c | |||
@@ -12,53 +12,16 @@ | |||
12 | #include <linux/platform_device.h> | 12 | #include <linux/platform_device.h> |
13 | #include <linux/delay.h> | 13 | #include <linux/delay.h> |
14 | 14 | ||
15 | #include <asm/clkdev.h> | ||
15 | #include <mach/pxa2xx-regs.h> | 16 | #include <mach/pxa2xx-regs.h> |
16 | #include <mach/pxa2xx-gpio.h> | ||
17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
18 | 18 | ||
19 | #include "devices.h" | 19 | #include "devices.h" |
20 | #include "generic.h" | 20 | #include "generic.h" |
21 | #include "clock.h" | 21 | #include "clock.h" |
22 | 22 | ||
23 | static LIST_HEAD(clocks); | ||
24 | static DEFINE_MUTEX(clocks_mutex); | ||
25 | static DEFINE_SPINLOCK(clocks_lock); | 23 | static DEFINE_SPINLOCK(clocks_lock); |
26 | 24 | ||
27 | static struct clk *clk_lookup(struct device *dev, const char *id) | ||
28 | { | ||
29 | struct clk *p; | ||
30 | |||
31 | list_for_each_entry(p, &clocks, node) | ||
32 | if (strcmp(id, p->name) == 0 && p->dev == dev) | ||
33 | return p; | ||
34 | |||
35 | return NULL; | ||
36 | } | ||
37 | |||
38 | struct clk *clk_get(struct device *dev, const char *id) | ||
39 | { | ||
40 | struct clk *p, *clk = ERR_PTR(-ENOENT); | ||
41 | |||
42 | mutex_lock(&clocks_mutex); | ||
43 | p = clk_lookup(dev, id); | ||
44 | if (!p) | ||
45 | p = clk_lookup(NULL, id); | ||
46 | if (p) | ||
47 | clk = p; | ||
48 | mutex_unlock(&clocks_mutex); | ||
49 | |||
50 | if (!IS_ERR(clk) && clk->ops == NULL) | ||
51 | clk = clk->other; | ||
52 | |||
53 | return clk; | ||
54 | } | ||
55 | EXPORT_SYMBOL(clk_get); | ||
56 | |||
57 | void clk_put(struct clk *clk) | ||
58 | { | ||
59 | } | ||
60 | EXPORT_SYMBOL(clk_put); | ||
61 | |||
62 | int clk_enable(struct clk *clk) | 25 | int clk_enable(struct clk *clk) |
63 | { | 26 | { |
64 | unsigned long flags; | 27 | unsigned long flags; |
@@ -116,37 +79,27 @@ const struct clkops clk_cken_ops = { | |||
116 | .disable = clk_cken_disable, | 79 | .disable = clk_cken_disable, |
117 | }; | 80 | }; |
118 | 81 | ||
119 | void clks_register(struct clk *clks, size_t num) | 82 | void clks_register(struct clk_lookup *clks, size_t num) |
120 | { | 83 | { |
121 | int i; | 84 | int i; |
122 | 85 | ||
123 | mutex_lock(&clocks_mutex); | ||
124 | for (i = 0; i < num; i++) | 86 | for (i = 0; i < num; i++) |
125 | list_add(&clks[i].node, &clocks); | 87 | clkdev_add(&clks[i]); |
126 | mutex_unlock(&clocks_mutex); | ||
127 | } | 88 | } |
128 | 89 | ||
129 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, | 90 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, |
130 | struct device *dev) | 91 | struct device *dev) |
131 | { | 92 | { |
132 | struct clk *r = clk_lookup(dev, id); | 93 | struct clk *r = clk_get(dev, id); |
133 | struct clk *new; | 94 | struct clk_lookup *l; |
134 | 95 | ||
135 | if (!r) | 96 | if (!r) |
136 | return -ENODEV; | 97 | return -ENODEV; |
137 | 98 | ||
138 | new = kzalloc(sizeof(struct clk), GFP_KERNEL); | 99 | l = clkdev_alloc(r, alias, alias_dev ? dev_name(alias_dev) : NULL); |
139 | 100 | clk_put(r); | |
140 | if (!new) | 101 | if (!l) |
141 | return -ENOMEM; | 102 | return -ENODEV; |
142 | 103 | clkdev_add(l); | |
143 | new->name = alias; | ||
144 | new->dev = alias_dev; | ||
145 | new->other = r; | ||
146 | |||
147 | mutex_lock(&clocks_mutex); | ||
148 | list_add(&new->node, &clocks); | ||
149 | mutex_unlock(&clocks_mutex); | ||
150 | |||
151 | return 0; | 104 | return 0; |
152 | } | 105 | } |
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index 73be795fe3bf..4e9c613c6767 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h | |||
@@ -1,6 +1,4 @@ | |||
1 | #include <linux/list.h> | 1 | #include <asm/clkdev.h> |
2 | |||
3 | struct clk; | ||
4 | 2 | ||
5 | struct clkops { | 3 | struct clkops { |
6 | void (*enable)(struct clk *); | 4 | void (*enable)(struct clk *); |
@@ -9,9 +7,6 @@ struct clkops { | |||
9 | }; | 7 | }; |
10 | 8 | ||
11 | struct clk { | 9 | struct clk { |
12 | struct list_head node; | ||
13 | const char *name; | ||
14 | struct device *dev; | ||
15 | const struct clkops *ops; | 10 | const struct clkops *ops; |
16 | unsigned long rate; | 11 | unsigned long rate; |
17 | unsigned int cken; | 12 | unsigned int cken; |
@@ -20,41 +15,31 @@ struct clk { | |||
20 | struct clk *other; | 15 | struct clk *other; |
21 | }; | 16 | }; |
22 | 17 | ||
23 | #define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \ | 18 | #define INIT_CLKREG(_clk,_devname,_conname) \ |
24 | { \ | 19 | { \ |
25 | .name = _name, \ | 20 | .clk = _clk, \ |
26 | .dev = _dev, \ | 21 | .dev_id = _devname, \ |
22 | .con_id = _conname, \ | ||
23 | } | ||
24 | |||
25 | #define DEFINE_CKEN(_name, _cken, _rate, _delay) \ | ||
26 | struct clk clk_##_name = { \ | ||
27 | .ops = &clk_cken_ops, \ | 27 | .ops = &clk_cken_ops, \ |
28 | .rate = _rate, \ | 28 | .rate = _rate, \ |
29 | .cken = CKEN_##_cken, \ | 29 | .cken = CKEN_##_cken, \ |
30 | .delay = _delay, \ | 30 | .delay = _delay, \ |
31 | } | 31 | } |
32 | 32 | ||
33 | #define INIT_CK(_name, _cken, _ops, _dev) \ | 33 | #define DEFINE_CK(_name, _cken, _ops) \ |
34 | { \ | 34 | struct clk clk_##_name = { \ |
35 | .name = _name, \ | ||
36 | .dev = _dev, \ | ||
37 | .ops = _ops, \ | 35 | .ops = _ops, \ |
38 | .cken = CKEN_##_cken, \ | 36 | .cken = CKEN_##_cken, \ |
39 | } | 37 | } |
40 | 38 | ||
41 | /* | 39 | #define DEFINE_CLK(_name, _ops, _rate, _delay) \ |
42 | * This is a placeholder to alias one clock device+name pair | 40 | struct clk clk_##_name = { \ |
43 | * to another struct clk. | 41 | .ops = _ops, \ |
44 | */ | 42 | .rate = _rate, \ |
45 | #define INIT_CKOTHER(_name, _other, _dev) \ | ||
46 | { \ | ||
47 | .name = _name, \ | ||
48 | .dev = _dev, \ | ||
49 | .other = _other, \ | ||
50 | } | ||
51 | |||
52 | #define INIT_CLK(_name, _ops, _rate, _delay, _dev) \ | ||
53 | { \ | ||
54 | .name = _name, \ | ||
55 | .dev = _dev, \ | ||
56 | .ops = _ops, \ | ||
57 | .rate = _rate, \ | ||
58 | .delay = _delay, \ | 43 | .delay = _delay, \ |
59 | } | 44 | } |
60 | 45 | ||
@@ -64,20 +49,16 @@ void clk_cken_enable(struct clk *clk); | |||
64 | void clk_cken_disable(struct clk *clk); | 49 | void clk_cken_disable(struct clk *clk); |
65 | 50 | ||
66 | #ifdef CONFIG_PXA3xx | 51 | #ifdef CONFIG_PXA3xx |
67 | #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ | 52 | #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ |
68 | { \ | 53 | struct clk clk_##_name = { \ |
69 | .name = _name, \ | ||
70 | .dev = _dev, \ | ||
71 | .ops = &clk_pxa3xx_cken_ops, \ | 54 | .ops = &clk_pxa3xx_cken_ops, \ |
72 | .rate = _rate, \ | 55 | .rate = _rate, \ |
73 | .cken = CKEN_##_cken, \ | 56 | .cken = CKEN_##_cken, \ |
74 | .delay = _delay, \ | 57 | .delay = _delay, \ |
75 | } | 58 | } |
76 | 59 | ||
77 | #define PXA3xx_CK(_name, _cken, _ops, _dev) \ | 60 | #define DEFINE_PXA3_CK(_name, _cken, _ops) \ |
78 | { \ | 61 | struct clk clk_##_name = { \ |
79 | .name = _name, \ | ||
80 | .dev = _dev, \ | ||
81 | .ops = _ops, \ | 62 | .ops = _ops, \ |
82 | .cken = CKEN_##_cken, \ | 63 | .cken = CKEN_##_cken, \ |
83 | } | 64 | } |
@@ -87,7 +68,7 @@ extern void clk_pxa3xx_cken_enable(struct clk *); | |||
87 | extern void clk_pxa3xx_cken_disable(struct clk *); | 68 | extern void clk_pxa3xx_cken_disable(struct clk *); |
88 | #endif | 69 | #endif |
89 | 70 | ||
90 | void clks_register(struct clk *clks, size_t num); | 71 | void clks_register(struct clk_lookup *clks, size_t num); |
91 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, | 72 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, |
92 | struct device *dev); | 73 | struct device *dev); |
93 | 74 | ||
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index 0b3ce3b6d896..d99fd9e4d888 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c | |||
@@ -210,10 +210,8 @@ static struct pxafb_mode_info generic_stn_320x240_mode = { | |||
210 | static struct pxafb_mach_info generic_stn_320x240 = { | 210 | static struct pxafb_mach_info generic_stn_320x240 = { |
211 | .modes = &generic_stn_320x240_mode, | 211 | .modes = &generic_stn_320x240_mode, |
212 | .num_modes = 1, | 212 | .num_modes = 1, |
213 | .lccr0 = 0, | 213 | .lcd_conn = LCD_COLOR_STN_8BPP | LCD_PCLK_EDGE_FALL |\ |
214 | .lccr3 = (LCCR3_PixClkDiv(0x03) | | 214 | LCD_AC_BIAS_FREQ(0xff), |
215 | LCCR3_Acb(0xff) | | ||
216 | LCCR3_PCP), | ||
217 | .cmap_inverse = 0, | 215 | .cmap_inverse = 0, |
218 | .cmap_static = 0, | 216 | .cmap_static = 0, |
219 | }; | 217 | }; |
@@ -236,10 +234,8 @@ static struct pxafb_mode_info generic_tft_640x480_mode = { | |||
236 | static struct pxafb_mach_info generic_tft_640x480 = { | 234 | static struct pxafb_mach_info generic_tft_640x480 = { |
237 | .modes = &generic_tft_640x480_mode, | 235 | .modes = &generic_tft_640x480_mode, |
238 | .num_modes = 1, | 236 | .num_modes = 1, |
239 | .lccr0 = (LCCR0_PAS), | 237 | .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_PCLK_EDGE_FALL |\ |
240 | .lccr3 = (LCCR3_PixClkDiv(0x01) | | 238 | LCD_AC_BIAS_FREQ(0xff), |
241 | LCCR3_Acb(0xff) | | ||
242 | LCCR3_PCP), | ||
243 | .cmap_inverse = 0, | 239 | .cmap_inverse = 0, |
244 | .cmap_static = 0, | 240 | .cmap_static = 0, |
245 | }; | 241 | }; |
@@ -263,9 +259,7 @@ static struct pxafb_mode_info generic_crt_640x480_mode = { | |||
263 | static struct pxafb_mach_info generic_crt_640x480 = { | 259 | static struct pxafb_mach_info generic_crt_640x480 = { |
264 | .modes = &generic_crt_640x480_mode, | 260 | .modes = &generic_crt_640x480_mode, |
265 | .num_modes = 1, | 261 | .num_modes = 1, |
266 | .lccr0 = (LCCR0_PAS), | 262 | .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff), |
267 | .lccr3 = (LCCR3_PixClkDiv(0x01) | | ||
268 | LCCR3_Acb(0xff)), | ||
269 | .cmap_inverse = 0, | 263 | .cmap_inverse = 0, |
270 | .cmap_static = 0, | 264 | .cmap_static = 0, |
271 | }; | 265 | }; |
@@ -289,9 +283,7 @@ static struct pxafb_mode_info generic_crt_800x600_mode = { | |||
289 | static struct pxafb_mach_info generic_crt_800x600 = { | 283 | static struct pxafb_mach_info generic_crt_800x600 = { |
290 | .modes = &generic_crt_800x600_mode, | 284 | .modes = &generic_crt_800x600_mode, |
291 | .num_modes = 1, | 285 | .num_modes = 1, |
292 | .lccr0 = (LCCR0_PAS), | 286 | .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff), |
293 | .lccr3 = (LCCR3_PixClkDiv(0x02) | | ||
294 | LCCR3_Acb(0xff)), | ||
295 | .cmap_inverse = 0, | 287 | .cmap_inverse = 0, |
296 | .cmap_static = 0, | 288 | .cmap_static = 0, |
297 | }; | 289 | }; |
@@ -314,10 +306,7 @@ static struct pxafb_mode_info generic_tft_320x240_mode = { | |||
314 | static struct pxafb_mach_info generic_tft_320x240 = { | 306 | static struct pxafb_mach_info generic_tft_320x240 = { |
315 | .modes = &generic_tft_320x240_mode, | 307 | .modes = &generic_tft_320x240_mode, |
316 | .num_modes = 1, | 308 | .num_modes = 1, |
317 | .lccr0 = (LCCR0_PAS), | 309 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_AC_BIAS_FREQ(0xff), |
318 | .lccr3 = (LCCR3_PixClkDiv(0x06) | | ||
319 | LCCR3_Acb(0xff) | | ||
320 | LCCR3_PCP), | ||
321 | .cmap_inverse = 0, | 310 | .cmap_inverse = 0, |
322 | .cmap_static = 0, | 311 | .cmap_static = 0, |
323 | }; | 312 | }; |
@@ -341,9 +330,7 @@ static struct pxafb_mode_info generic_stn_640x480_mode = { | |||
341 | static struct pxafb_mach_info generic_stn_640x480 = { | 330 | static struct pxafb_mach_info generic_stn_640x480 = { |
342 | .modes = &generic_stn_640x480_mode, | 331 | .modes = &generic_stn_640x480_mode, |
343 | .num_modes = 1, | 332 | .num_modes = 1, |
344 | .lccr0 = 0, | 333 | .lcd_conn = LCD_COLOR_STN_8BPP | LCD_AC_BIAS_FREQ(0xff), |
345 | .lccr3 = (LCCR3_PixClkDiv(0x02) | | ||
346 | LCCR3_Acb(0xff)), | ||
347 | .cmap_inverse = 0, | 334 | .cmap_inverse = 0, |
348 | .cmap_static = 0, | 335 | .cmap_static = 0, |
349 | }; | 336 | }; |
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index deb46cd144bf..ff0c577cd1ac 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include <mach/mfp-pxa300.h> | 31 | #include <mach/mfp-pxa300.h> |
32 | 32 | ||
33 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
34 | #include <mach/gpio.h> | ||
35 | #include <mach/pxafb.h> | 34 | #include <mach/pxafb.h> |
36 | #include <mach/mmc.h> | 35 | #include <mach/mmc.h> |
37 | #include <mach/ohci.h> | 36 | #include <mach/ohci.h> |
@@ -137,6 +136,10 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { | |||
137 | GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ | 136 | GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ |
138 | GPIO85_GPIO, /* MMC WP */ | 137 | GPIO85_GPIO, /* MMC WP */ |
139 | GPIO99_GPIO, /* Ethernet IRQ */ | 138 | GPIO99_GPIO, /* Ethernet IRQ */ |
139 | |||
140 | /* Standard I2C */ | ||
141 | GPIO21_I2C_SCL, | ||
142 | GPIO22_I2C_SDA, | ||
140 | }; | 143 | }; |
141 | 144 | ||
142 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | 145 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index b65be8e7792a..a8d91b6c136b 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/fs.h> | 19 | #include <linux/fs.h> |
20 | #include <linux/interrupt.h> | 20 | #include <linux/interrupt.h> |
21 | #include <linux/mmc/host.h> | 21 | #include <linux/mmc/host.h> |
22 | #include <linux/mtd/physmap.h> | ||
22 | #include <linux/pm.h> | 23 | #include <linux/pm.h> |
23 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
24 | #include <linux/backlight.h> | 25 | #include <linux/backlight.h> |
@@ -591,12 +592,43 @@ static struct platform_device sharpsl_nand_device = { | |||
591 | .dev.platform_data = &sharpsl_nand_platform_data, | 592 | .dev.platform_data = &sharpsl_nand_platform_data, |
592 | }; | 593 | }; |
593 | 594 | ||
595 | static struct mtd_partition sharpsl_rom_parts[] = { | ||
596 | { | ||
597 | .name ="Boot PROM Filesystem", | ||
598 | .offset = 0x00120000, | ||
599 | .size = MTDPART_SIZ_FULL, | ||
600 | }, | ||
601 | }; | ||
602 | |||
603 | static struct physmap_flash_data sharpsl_rom_data = { | ||
604 | .width = 2, | ||
605 | .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), | ||
606 | .parts = sharpsl_rom_parts, | ||
607 | }; | ||
608 | |||
609 | static struct resource sharpsl_rom_resources[] = { | ||
610 | { | ||
611 | .start = 0x00000000, | ||
612 | .end = 0x007fffff, | ||
613 | .flags = IORESOURCE_MEM, | ||
614 | }, | ||
615 | }; | ||
616 | |||
617 | static struct platform_device sharpsl_rom_device = { | ||
618 | .name = "physmap-flash", | ||
619 | .id = -1, | ||
620 | .resource = sharpsl_rom_resources, | ||
621 | .num_resources = ARRAY_SIZE(sharpsl_rom_resources), | ||
622 | .dev.platform_data = &sharpsl_rom_data, | ||
623 | }; | ||
624 | |||
594 | static struct platform_device *devices[] __initdata = { | 625 | static struct platform_device *devices[] __initdata = { |
595 | &corgiscoop_device, | 626 | &corgiscoop_device, |
596 | &corgifb_device, | 627 | &corgifb_device, |
597 | &corgikbd_device, | 628 | &corgikbd_device, |
598 | &corgiled_device, | 629 | &corgiled_device, |
599 | &sharpsl_nand_device, | 630 | &sharpsl_nand_device, |
631 | &sharpsl_rom_device, | ||
600 | }; | 632 | }; |
601 | 633 | ||
602 | static void corgi_poweroff(void) | 634 | static void corgi_poweroff(void) |
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 1f272ea83f36..771dd4eac935 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c | |||
@@ -64,7 +64,7 @@ typedef struct { | |||
64 | 64 | ||
65 | /* Define the refresh period in mSec for the SDRAM and the number of rows */ | 65 | /* Define the refresh period in mSec for the SDRAM and the number of rows */ |
66 | #define SDRAM_TREF 64 /* standard 64ms SDRAM */ | 66 | #define SDRAM_TREF 64 /* standard 64ms SDRAM */ |
67 | #define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ | 67 | static unsigned int sdram_rows; |
68 | 68 | ||
69 | #define CCLKCFG_TURBO 0x1 | 69 | #define CCLKCFG_TURBO 0x1 |
70 | #define CCLKCFG_FCS 0x2 | 70 | #define CCLKCFG_FCS 0x2 |
@@ -73,6 +73,9 @@ typedef struct { | |||
73 | #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) | 73 | #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) |
74 | #define MDREFR_DRI_MASK 0xFFF | 74 | #define MDREFR_DRI_MASK 0xFFF |
75 | 75 | ||
76 | #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) | ||
77 | #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) | ||
78 | |||
76 | /* | 79 | /* |
77 | * PXA255 definitions | 80 | * PXA255 definitions |
78 | */ | 81 | */ |
@@ -109,6 +112,10 @@ static struct cpufreq_frequency_table | |||
109 | static struct cpufreq_frequency_table | 112 | static struct cpufreq_frequency_table |
110 | pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; | 113 | pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; |
111 | 114 | ||
115 | static unsigned int pxa255_turbo_table; | ||
116 | module_param(pxa255_turbo_table, uint, 0); | ||
117 | MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)"); | ||
118 | |||
112 | /* | 119 | /* |
113 | * PXA270 definitions | 120 | * PXA270 definitions |
114 | * | 121 | * |
@@ -158,22 +165,16 @@ static struct cpufreq_frequency_table | |||
158 | 165 | ||
159 | extern unsigned get_clk_frequency_khz(int info); | 166 | extern unsigned get_clk_frequency_khz(int info); |
160 | 167 | ||
161 | static void find_freq_tables(struct cpufreq_policy *policy, | 168 | static void find_freq_tables(struct cpufreq_frequency_table **freq_table, |
162 | struct cpufreq_frequency_table **freq_table, | ||
163 | pxa_freqs_t **pxa_freqs) | 169 | pxa_freqs_t **pxa_freqs) |
164 | { | 170 | { |
165 | if (cpu_is_pxa25x()) { | 171 | if (cpu_is_pxa25x()) { |
166 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { | 172 | if (!pxa255_turbo_table) { |
167 | *pxa_freqs = pxa255_run_freqs; | 173 | *pxa_freqs = pxa255_run_freqs; |
168 | *freq_table = pxa255_run_freq_table; | 174 | *freq_table = pxa255_run_freq_table; |
169 | } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { | 175 | } else { |
170 | *pxa_freqs = pxa255_turbo_freqs; | 176 | *pxa_freqs = pxa255_turbo_freqs; |
171 | *freq_table = pxa255_turbo_freq_table; | 177 | *freq_table = pxa255_turbo_freq_table; |
172 | } else { | ||
173 | printk("CPU PXA: Unknown policy found. " | ||
174 | "Using CPUFREQ_POLICY_PERFORMANCE\n"); | ||
175 | *pxa_freqs = pxa255_run_freqs; | ||
176 | *freq_table = pxa255_run_freq_table; | ||
177 | } | 178 | } |
178 | } | 179 | } |
179 | if (cpu_is_pxa27x()) { | 180 | if (cpu_is_pxa27x()) { |
@@ -194,14 +195,28 @@ static void pxa27x_guess_max_freq(void) | |||
194 | } | 195 | } |
195 | } | 196 | } |
196 | 197 | ||
198 | static void init_sdram_rows(void) | ||
199 | { | ||
200 | uint32_t mdcnfg = MDCNFG; | ||
201 | unsigned int drac2 = 0, drac0 = 0; | ||
202 | |||
203 | if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) | ||
204 | drac2 = MDCNFG_DRAC2(mdcnfg); | ||
205 | |||
206 | if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) | ||
207 | drac0 = MDCNFG_DRAC0(mdcnfg); | ||
208 | |||
209 | sdram_rows = 1 << (11 + max(drac0, drac2)); | ||
210 | } | ||
211 | |||
197 | static u32 mdrefr_dri(unsigned int freq) | 212 | static u32 mdrefr_dri(unsigned int freq) |
198 | { | 213 | { |
199 | u32 dri = 0; | 214 | u32 dri = 0; |
200 | 215 | ||
201 | if (cpu_is_pxa25x()) | 216 | if (cpu_is_pxa25x()) |
202 | dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32)); | 217 | dri = ((freq * SDRAM_TREF) / (sdram_rows * 32)); |
203 | if (cpu_is_pxa27x()) | 218 | if (cpu_is_pxa27x()) |
204 | dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32; | 219 | dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32; |
205 | return dri; | 220 | return dri; |
206 | } | 221 | } |
207 | 222 | ||
@@ -212,7 +227,7 @@ static int pxa_verify_policy(struct cpufreq_policy *policy) | |||
212 | pxa_freqs_t *pxa_freqs; | 227 | pxa_freqs_t *pxa_freqs; |
213 | int ret; | 228 | int ret; |
214 | 229 | ||
215 | find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs); | 230 | find_freq_tables(&pxa_freqs_table, &pxa_freqs); |
216 | ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); | 231 | ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); |
217 | 232 | ||
218 | if (freq_debug) | 233 | if (freq_debug) |
@@ -240,7 +255,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, | |||
240 | unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; | 255 | unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; |
241 | 256 | ||
242 | /* Get the current policy */ | 257 | /* Get the current policy */ |
243 | find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings); | 258 | find_freq_tables(&pxa_freqs_table, &pxa_freq_settings); |
244 | 259 | ||
245 | /* Lookup the next frequency */ | 260 | /* Lookup the next frequency */ |
246 | if (cpufreq_frequency_table_target(policy, pxa_freqs_table, | 261 | if (cpufreq_frequency_table_target(policy, pxa_freqs_table, |
@@ -329,11 +344,15 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) | |||
329 | { | 344 | { |
330 | int i; | 345 | int i; |
331 | unsigned int freq; | 346 | unsigned int freq; |
347 | struct cpufreq_frequency_table *pxa255_freq_table; | ||
348 | pxa_freqs_t *pxa255_freqs; | ||
332 | 349 | ||
333 | /* try to guess pxa27x cpu */ | 350 | /* try to guess pxa27x cpu */ |
334 | if (cpu_is_pxa27x()) | 351 | if (cpu_is_pxa27x()) |
335 | pxa27x_guess_max_freq(); | 352 | pxa27x_guess_max_freq(); |
336 | 353 | ||
354 | init_sdram_rows(); | ||
355 | |||
337 | /* set default policy and cpuinfo */ | 356 | /* set default policy and cpuinfo */ |
338 | policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ | 357 | policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ |
339 | policy->cur = get_clk_frequency_khz(0); /* current freq */ | 358 | policy->cur = get_clk_frequency_khz(0); /* current freq */ |
@@ -354,6 +373,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) | |||
354 | } | 373 | } |
355 | pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; | 374 | pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; |
356 | 375 | ||
376 | pxa255_turbo_table = !!pxa255_turbo_table; | ||
377 | |||
357 | /* Generate the pxa27x cpufreq_frequency_table struct */ | 378 | /* Generate the pxa27x cpufreq_frequency_table struct */ |
358 | for (i = 0; i < NUM_PXA27x_FREQS; i++) { | 379 | for (i = 0; i < NUM_PXA27x_FREQS; i++) { |
359 | freq = pxa27x_freqs[i].khz; | 380 | freq = pxa27x_freqs[i].khz; |
@@ -368,8 +389,12 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) | |||
368 | * Set the policy's minimum and maximum frequencies from the tables | 389 | * Set the policy's minimum and maximum frequencies from the tables |
369 | * just constructed. This sets cpuinfo.mxx_freq, min and max. | 390 | * just constructed. This sets cpuinfo.mxx_freq, min and max. |
370 | */ | 391 | */ |
371 | if (cpu_is_pxa25x()) | 392 | if (cpu_is_pxa25x()) { |
372 | cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table); | 393 | find_freq_tables(&pxa255_freq_table, &pxa255_freqs); |
394 | pr_info("PXA255 cpufreq using %s frequency table\n", | ||
395 | pxa255_turbo_table ? "turbo" : "run"); | ||
396 | cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table); | ||
397 | } | ||
373 | else if (cpu_is_pxa27x()) | 398 | else if (cpu_is_pxa27x()) |
374 | cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); | 399 | cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); |
375 | 400 | ||
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 35736fc08634..e16f8e3d58d3 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
@@ -4,13 +4,12 @@ | |||
4 | #include <linux/platform_device.h> | 4 | #include <linux/platform_device.h> |
5 | #include <linux/dma-mapping.h> | 5 | #include <linux/dma-mapping.h> |
6 | 6 | ||
7 | #include <mach/gpio.h> | 7 | #include <mach/pxa-regs.h> |
8 | #include <mach/udc.h> | 8 | #include <mach/udc.h> |
9 | #include <mach/pxafb.h> | 9 | #include <mach/pxafb.h> |
10 | #include <mach/mmc.h> | 10 | #include <mach/mmc.h> |
11 | #include <mach/irda.h> | 11 | #include <mach/irda.h> |
12 | #include <mach/i2c.h> | 12 | #include <mach/i2c.h> |
13 | #include <mach/mfp-pxa27x.h> | ||
14 | #include <mach/ohci.h> | 13 | #include <mach/ohci.h> |
15 | #include <mach/pxa27x_keypad.h> | 14 | #include <mach/pxa27x_keypad.h> |
16 | #include <mach/pxa2xx_spi.h> | 15 | #include <mach/pxa2xx_spi.h> |
@@ -156,8 +155,8 @@ void __init set_pxa_fb_parent(struct device *parent_dev) | |||
156 | 155 | ||
157 | static struct resource pxa_resource_ffuart[] = { | 156 | static struct resource pxa_resource_ffuart[] = { |
158 | { | 157 | { |
159 | .start = __PREG(FFUART), | 158 | .start = 0x40100000, |
160 | .end = __PREG(FFUART) + 35, | 159 | .end = 0x40100023, |
161 | .flags = IORESOURCE_MEM, | 160 | .flags = IORESOURCE_MEM, |
162 | }, { | 161 | }, { |
163 | .start = IRQ_FFUART, | 162 | .start = IRQ_FFUART, |
@@ -175,8 +174,8 @@ struct platform_device pxa_device_ffuart= { | |||
175 | 174 | ||
176 | static struct resource pxa_resource_btuart[] = { | 175 | static struct resource pxa_resource_btuart[] = { |
177 | { | 176 | { |
178 | .start = __PREG(BTUART), | 177 | .start = 0x40200000, |
179 | .end = __PREG(BTUART) + 35, | 178 | .end = 0x40200023, |
180 | .flags = IORESOURCE_MEM, | 179 | .flags = IORESOURCE_MEM, |
181 | }, { | 180 | }, { |
182 | .start = IRQ_BTUART, | 181 | .start = IRQ_BTUART, |
@@ -194,8 +193,8 @@ struct platform_device pxa_device_btuart = { | |||
194 | 193 | ||
195 | static struct resource pxa_resource_stuart[] = { | 194 | static struct resource pxa_resource_stuart[] = { |
196 | { | 195 | { |
197 | .start = __PREG(STUART), | 196 | .start = 0x40700000, |
198 | .end = __PREG(STUART) + 35, | 197 | .end = 0x40700023, |
199 | .flags = IORESOURCE_MEM, | 198 | .flags = IORESOURCE_MEM, |
200 | }, { | 199 | }, { |
201 | .start = IRQ_STUART, | 200 | .start = IRQ_STUART, |
@@ -213,8 +212,8 @@ struct platform_device pxa_device_stuart = { | |||
213 | 212 | ||
214 | static struct resource pxa_resource_hwuart[] = { | 213 | static struct resource pxa_resource_hwuart[] = { |
215 | { | 214 | { |
216 | .start = __PREG(HWUART), | 215 | .start = 0x41600000, |
217 | .end = __PREG(HWUART) + 47, | 216 | .end = 0x4160002F, |
218 | .flags = IORESOURCE_MEM, | 217 | .flags = IORESOURCE_MEM, |
219 | }, { | 218 | }, { |
220 | .start = IRQ_HWUART, | 219 | .start = IRQ_HWUART, |
@@ -249,18 +248,53 @@ struct platform_device pxa_device_i2c = { | |||
249 | .num_resources = ARRAY_SIZE(pxai2c_resources), | 248 | .num_resources = ARRAY_SIZE(pxai2c_resources), |
250 | }; | 249 | }; |
251 | 250 | ||
252 | static unsigned long pxa27x_i2c_mfp_cfg[] = { | ||
253 | GPIO117_I2C_SCL, | ||
254 | GPIO118_I2C_SDA, | ||
255 | }; | ||
256 | |||
257 | void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) | 251 | void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) |
258 | { | 252 | { |
259 | if (cpu_is_pxa27x()) | ||
260 | pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg)); | ||
261 | pxa_register_device(&pxa_device_i2c, info); | 253 | pxa_register_device(&pxa_device_i2c, info); |
262 | } | 254 | } |
263 | 255 | ||
256 | #ifdef CONFIG_PXA27x | ||
257 | static struct resource pxa27x_resources_i2c_power[] = { | ||
258 | { | ||
259 | .start = 0x40f00180, | ||
260 | .end = 0x40f001a3, | ||
261 | .flags = IORESOURCE_MEM, | ||
262 | }, { | ||
263 | .start = IRQ_PWRI2C, | ||
264 | .end = IRQ_PWRI2C, | ||
265 | .flags = IORESOURCE_IRQ, | ||
266 | }, | ||
267 | }; | ||
268 | |||
269 | struct platform_device pxa27x_device_i2c_power = { | ||
270 | .name = "pxa2xx-i2c", | ||
271 | .id = 1, | ||
272 | .resource = pxa27x_resources_i2c_power, | ||
273 | .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power), | ||
274 | }; | ||
275 | #endif | ||
276 | |||
277 | #ifdef CONFIG_PXA3xx | ||
278 | static struct resource pxa3xx_resources_i2c_power[] = { | ||
279 | { | ||
280 | .start = 0x40f500c0, | ||
281 | .end = 0x40f500d3, | ||
282 | .flags = IORESOURCE_MEM, | ||
283 | }, { | ||
284 | .start = IRQ_PWRI2C, | ||
285 | .end = IRQ_PWRI2C, | ||
286 | .flags = IORESOURCE_IRQ, | ||
287 | }, | ||
288 | }; | ||
289 | |||
290 | struct platform_device pxa3xx_device_i2c_power = { | ||
291 | .name = "pxa2xx-i2c", | ||
292 | .id = 1, | ||
293 | .resource = pxa3xx_resources_i2c_power, | ||
294 | .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), | ||
295 | }; | ||
296 | #endif | ||
297 | |||
264 | static struct resource pxai2s_resources[] = { | 298 | static struct resource pxai2s_resources[] = { |
265 | { | 299 | { |
266 | .start = 0x40400000, | 300 | .start = 0x40400000, |
@@ -296,11 +330,36 @@ void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) | |||
296 | pxa_register_device(&pxa_device_ficp, info); | 330 | pxa_register_device(&pxa_device_ficp, info); |
297 | } | 331 | } |
298 | 332 | ||
299 | struct platform_device pxa_device_rtc = { | 333 | static struct resource pxa_rtc_resources[] = { |
334 | [0] = { | ||
335 | .start = 0x40900000, | ||
336 | .end = 0x40900000 + 0x3b, | ||
337 | .flags = IORESOURCE_MEM, | ||
338 | }, | ||
339 | [1] = { | ||
340 | .start = IRQ_RTC1Hz, | ||
341 | .end = IRQ_RTC1Hz, | ||
342 | .flags = IORESOURCE_IRQ, | ||
343 | }, | ||
344 | [2] = { | ||
345 | .start = IRQ_RTCAlrm, | ||
346 | .end = IRQ_RTCAlrm, | ||
347 | .flags = IORESOURCE_IRQ, | ||
348 | }, | ||
349 | }; | ||
350 | |||
351 | struct platform_device sa1100_device_rtc = { | ||
300 | .name = "sa1100-rtc", | 352 | .name = "sa1100-rtc", |
301 | .id = -1, | 353 | .id = -1, |
302 | }; | 354 | }; |
303 | 355 | ||
356 | struct platform_device pxa_device_rtc = { | ||
357 | .name = "pxa-rtc", | ||
358 | .id = -1, | ||
359 | .num_resources = ARRAY_SIZE(pxa_rtc_resources), | ||
360 | .resource = pxa_rtc_resources, | ||
361 | }; | ||
362 | |||
304 | static struct resource pxa_ac97_resources[] = { | 363 | static struct resource pxa_ac97_resources[] = { |
305 | [0] = { | 364 | [0] = { |
306 | .start = 0x40500000, | 365 | .start = 0x40500000, |
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index bb04af4b0aa3..ecc24a4dca6d 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h | |||
@@ -11,6 +11,7 @@ extern struct platform_device pxa_device_hwuart; | |||
11 | extern struct platform_device pxa_device_i2c; | 11 | extern struct platform_device pxa_device_i2c; |
12 | extern struct platform_device pxa_device_i2s; | 12 | extern struct platform_device pxa_device_i2s; |
13 | extern struct platform_device pxa_device_ficp; | 13 | extern struct platform_device pxa_device_ficp; |
14 | extern struct platform_device sa1100_device_rtc; | ||
14 | extern struct platform_device pxa_device_rtc; | 15 | extern struct platform_device pxa_device_rtc; |
15 | extern struct platform_device pxa_device_ac97; | 16 | extern struct platform_device pxa_device_ac97; |
16 | 17 | ||
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c index c0be17e0ab82..b1514fb20d3a 100644 --- a/arch/arm/mach-pxa/dma.c +++ b/arch/arm/mach-pxa/dma.c | |||
@@ -21,7 +21,7 @@ | |||
21 | #include <asm/system.h> | 21 | #include <asm/system.h> |
22 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
24 | #include <asm/dma.h> | 24 | #include <mach/dma.h> |
25 | 25 | ||
26 | #include <mach/pxa-regs.h> | 26 | #include <mach/pxa-regs.h> |
27 | 27 | ||
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c index d488eded2058..1bd7f740427c 100644 --- a/arch/arm/mach-pxa/e330.c +++ b/arch/arm/mach-pxa/e330.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Hardware definitions for the Toshiba eseries PDAs | 2 | * Hardware definitions for the Toshiba e330 PDAs |
3 | * | 3 | * |
4 | * Copyright (c) 2003 Ian Molton <spyro@f2s.com> | 4 | * Copyright (c) 2003 Ian Molton <spyro@f2s.com> |
5 | * | 5 | * |
@@ -12,6 +12,9 @@ | |||
12 | 12 | ||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/clk.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/mfd/tc6387xb.h> | ||
15 | 18 | ||
16 | #include <asm/setup.h> | 19 | #include <asm/setup.h> |
17 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
@@ -19,13 +22,44 @@ | |||
19 | 22 | ||
20 | #include <mach/mfp-pxa25x.h> | 23 | #include <mach/mfp-pxa25x.h> |
21 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
25 | #include <mach/pxa-regs.h> | ||
26 | #include <mach/eseries-gpio.h> | ||
22 | #include <mach/udc.h> | 27 | #include <mach/udc.h> |
23 | 28 | ||
24 | #include "generic.h" | 29 | #include "generic.h" |
25 | #include "eseries.h" | 30 | #include "eseries.h" |
31 | #include "clock.h" | ||
32 | |||
33 | /* -------------------- e330 tc6387xb parameters -------------------- */ | ||
34 | |||
35 | static struct tc6387xb_platform_data e330_tc6387xb_info = { | ||
36 | .enable = &eseries_tmio_enable, | ||
37 | .disable = &eseries_tmio_disable, | ||
38 | .suspend = &eseries_tmio_suspend, | ||
39 | .resume = &eseries_tmio_resume, | ||
40 | }; | ||
41 | |||
42 | static struct platform_device e330_tc6387xb_device = { | ||
43 | .name = "tc6387xb", | ||
44 | .id = -1, | ||
45 | .dev = { | ||
46 | .platform_data = &e330_tc6387xb_info, | ||
47 | }, | ||
48 | .num_resources = 2, | ||
49 | .resource = eseries_tmio_resources, | ||
50 | }; | ||
51 | |||
52 | /* --------------------------------------------------------------- */ | ||
53 | |||
54 | static struct platform_device *devices[] __initdata = { | ||
55 | &e330_tc6387xb_device, | ||
56 | }; | ||
26 | 57 | ||
27 | static void __init e330_init(void) | 58 | static void __init e330_init(void) |
28 | { | 59 | { |
60 | eseries_register_clks(); | ||
61 | eseries_get_tmio_gpios(); | ||
62 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
29 | pxa_set_udc_info(&e7xx_udc_mach_info); | 63 | pxa_set_udc_info(&e7xx_udc_mach_info); |
30 | } | 64 | } |
31 | 65 | ||
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c index 8ecbc5479828..251129391d7d 100644 --- a/arch/arm/mach-pxa/e350.c +++ b/arch/arm/mach-pxa/e350.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Hardware definitions for the Toshiba eseries PDAs | 2 | * Hardware definitions for the Toshiba e350 PDAs |
3 | * | 3 | * |
4 | * Copyright (c) 2003 Ian Molton <spyro@f2s.com> | 4 | * Copyright (c) 2003 Ian Molton <spyro@f2s.com> |
5 | * | 5 | * |
@@ -12,20 +12,54 @@ | |||
12 | 12 | ||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/clk.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/mfd/t7l66xb.h> | ||
15 | 18 | ||
16 | #include <asm/setup.h> | 19 | #include <asm/setup.h> |
17 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
18 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
19 | 22 | ||
20 | #include <mach/mfp-pxa25x.h> | 23 | #include <mach/mfp-pxa25x.h> |
24 | #include <mach/pxa-regs.h> | ||
21 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
26 | #include <mach/eseries-gpio.h> | ||
22 | #include <mach/udc.h> | 27 | #include <mach/udc.h> |
23 | 28 | ||
24 | #include "generic.h" | 29 | #include "generic.h" |
25 | #include "eseries.h" | 30 | #include "eseries.h" |
31 | #include "clock.h" | ||
32 | |||
33 | /* -------------------- e350 t7l66xb parameters -------------------- */ | ||
34 | |||
35 | static struct t7l66xb_platform_data e350_t7l66xb_info = { | ||
36 | .irq_base = IRQ_BOARD_START, | ||
37 | .enable = &eseries_tmio_enable, | ||
38 | .suspend = &eseries_tmio_suspend, | ||
39 | .resume = &eseries_tmio_resume, | ||
40 | }; | ||
41 | |||
42 | static struct platform_device e350_t7l66xb_device = { | ||
43 | .name = "t7l66xb", | ||
44 | .id = -1, | ||
45 | .dev = { | ||
46 | .platform_data = &e350_t7l66xb_info, | ||
47 | }, | ||
48 | .num_resources = 2, | ||
49 | .resource = eseries_tmio_resources, | ||
50 | }; | ||
51 | |||
52 | /* ---------------------------------------------------------- */ | ||
53 | |||
54 | static struct platform_device *devices[] __initdata = { | ||
55 | &e350_t7l66xb_device, | ||
56 | }; | ||
26 | 57 | ||
27 | static void __init e350_init(void) | 58 | static void __init e350_init(void) |
28 | { | 59 | { |
60 | eseries_register_clks(); | ||
61 | eseries_get_tmio_gpios(); | ||
62 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
29 | pxa_set_udc_info(&e7xx_udc_mach_info); | 63 | pxa_set_udc_info(&e7xx_udc_mach_info); |
30 | } | 64 | } |
31 | 65 | ||
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c index 544bbaa20621..bed0336aca3d 100644 --- a/arch/arm/mach-pxa/e400.c +++ b/arch/arm/mach-pxa/e400.c | |||
@@ -12,20 +12,26 @@ | |||
12 | 12 | ||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/clk.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/mfd/t7l66xb.h> | ||
18 | #include <linux/mtd/nand.h> | ||
19 | #include <linux/mtd/partitions.h> | ||
15 | 20 | ||
16 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
17 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
18 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
19 | 24 | ||
20 | #include <mach/pxa-regs.h> | ||
21 | #include <mach/mfp-pxa25x.h> | 25 | #include <mach/mfp-pxa25x.h> |
26 | #include <mach/pxa-regs.h> | ||
22 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
23 | 28 | #include <mach/eseries-gpio.h> | |
24 | #include <mach/pxafb.h> | 29 | #include <mach/pxafb.h> |
25 | #include <mach/udc.h> | 30 | #include <mach/udc.h> |
26 | 31 | ||
27 | #include "generic.h" | 32 | #include "generic.h" |
28 | #include "eseries.h" | 33 | #include "eseries.h" |
34 | #include "clock.h" | ||
29 | 35 | ||
30 | /* ------------------------ E400 LCD definitions ------------------------ */ | 36 | /* ------------------------ E400 LCD definitions ------------------------ */ |
31 | 37 | ||
@@ -46,7 +52,7 @@ static struct pxafb_mode_info e400_pxafb_mode_info = { | |||
46 | static struct pxafb_mach_info e400_pxafb_mach_info = { | 52 | static struct pxafb_mach_info e400_pxafb_mach_info = { |
47 | .modes = &e400_pxafb_mode_info, | 53 | .modes = &e400_pxafb_mode_info, |
48 | .num_modes = 1, | 54 | .num_modes = 1, |
49 | .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, | 55 | .lcd_conn = LCD_COLOR_TFT_16BPP, |
50 | .lccr3 = 0, | 56 | .lccr3 = 0, |
51 | .pxafb_backlight_power = NULL, | 57 | .pxafb_backlight_power = NULL, |
52 | }; | 58 | }; |
@@ -65,7 +71,10 @@ static unsigned long e400_pin_config[] __initdata = { | |||
65 | GPIO42_BTUART_RXD, | 71 | GPIO42_BTUART_RXD, |
66 | GPIO43_BTUART_TXD, | 72 | GPIO43_BTUART_TXD, |
67 | GPIO44_BTUART_CTS, | 73 | GPIO44_BTUART_CTS, |
68 | GPIO45_GPIO, /* Used by TMIO for #SUSPEND */ | 74 | |
75 | /* TMIO controller */ | ||
76 | GPIO19_GPIO, /* t7l66xb #PCLR */ | ||
77 | GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ | ||
69 | 78 | ||
70 | /* wakeup */ | 79 | /* wakeup */ |
71 | GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, | 80 | GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, |
@@ -73,10 +82,60 @@ static unsigned long e400_pin_config[] __initdata = { | |||
73 | 82 | ||
74 | /* ---------------------------------------------------------------------- */ | 83 | /* ---------------------------------------------------------------------- */ |
75 | 84 | ||
85 | static struct mtd_partition partition_a = { | ||
86 | .name = "Internal NAND flash", | ||
87 | .offset = 0, | ||
88 | .size = MTDPART_SIZ_FULL, | ||
89 | }; | ||
90 | |||
91 | static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; | ||
92 | |||
93 | static struct nand_bbt_descr e400_t7l66xb_nand_bbt = { | ||
94 | .options = 0, | ||
95 | .offs = 4, | ||
96 | .len = 2, | ||
97 | .pattern = scan_ff_pattern | ||
98 | }; | ||
99 | |||
100 | static struct tmio_nand_data e400_t7l66xb_nand_config = { | ||
101 | .num_partitions = 1, | ||
102 | .partition = &partition_a, | ||
103 | .badblock_pattern = &e400_t7l66xb_nand_bbt, | ||
104 | }; | ||
105 | |||
106 | static struct t7l66xb_platform_data e400_t7l66xb_info = { | ||
107 | .irq_base = IRQ_BOARD_START, | ||
108 | .enable = &eseries_tmio_enable, | ||
109 | .suspend = &eseries_tmio_suspend, | ||
110 | .resume = &eseries_tmio_resume, | ||
111 | |||
112 | .nand_data = &e400_t7l66xb_nand_config, | ||
113 | }; | ||
114 | |||
115 | static struct platform_device e400_t7l66xb_device = { | ||
116 | .name = "t7l66xb", | ||
117 | .id = -1, | ||
118 | .dev = { | ||
119 | .platform_data = &e400_t7l66xb_info, | ||
120 | }, | ||
121 | .num_resources = 2, | ||
122 | .resource = eseries_tmio_resources, | ||
123 | }; | ||
124 | |||
125 | /* ---------------------------------------------------------- */ | ||
126 | |||
127 | static struct platform_device *devices[] __initdata = { | ||
128 | &e400_t7l66xb_device, | ||
129 | }; | ||
130 | |||
76 | static void __init e400_init(void) | 131 | static void __init e400_init(void) |
77 | { | 132 | { |
78 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); | 133 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); |
134 | /* Fixme - e400 may have a switched clock */ | ||
135 | eseries_register_clks(); | ||
136 | eseries_get_tmio_gpios(); | ||
79 | set_pxa_fb_info(&e400_pxafb_mach_info); | 137 | set_pxa_fb_info(&e400_pxafb_mach_info); |
138 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
80 | pxa_set_udc_info(&e7xx_udc_mach_info); | 139 | pxa_set_udc_info(&e7xx_udc_mach_info); |
81 | } | 140 | } |
82 | 141 | ||
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c index c57a15b37f0d..b00d670b2ea6 100644 --- a/arch/arm/mach-pxa/e740.c +++ b/arch/arm/mach-pxa/e740.c | |||
@@ -15,6 +15,8 @@ | |||
15 | #include <linux/device.h> | 15 | #include <linux/device.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/fb.h> | 17 | #include <linux/fb.h> |
18 | #include <linux/clk.h> | ||
19 | #include <linux/mfd/t7l66xb.h> | ||
18 | 20 | ||
19 | #include <video/w100fb.h> | 21 | #include <video/w100fb.h> |
20 | 22 | ||
@@ -23,12 +25,16 @@ | |||
23 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
24 | 26 | ||
25 | #include <mach/mfp-pxa25x.h> | 27 | #include <mach/mfp-pxa25x.h> |
28 | #include <mach/pxa-regs.h> | ||
26 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <mach/eseries-gpio.h> | ||
27 | #include <mach/udc.h> | 31 | #include <mach/udc.h> |
32 | #include <mach/irda.h> | ||
28 | 33 | ||
29 | #include "generic.h" | 34 | #include "generic.h" |
30 | #include "eseries.h" | 35 | #include "eseries.h" |
31 | 36 | #include "clock.h" | |
37 | #include "devices.h" | ||
32 | 38 | ||
33 | /* ------------------------ e740 video support --------------------------- */ | 39 | /* ------------------------ e740 video support --------------------------- */ |
34 | 40 | ||
@@ -116,7 +122,17 @@ static unsigned long e740_pin_config[] __initdata = { | |||
116 | GPIO42_BTUART_RXD, | 122 | GPIO42_BTUART_RXD, |
117 | GPIO43_BTUART_TXD, | 123 | GPIO43_BTUART_TXD, |
118 | GPIO44_BTUART_CTS, | 124 | GPIO44_BTUART_CTS, |
119 | GPIO45_GPIO, /* Used by TMIO for #SUSPEND */ | 125 | |
126 | /* TMIO controller */ | ||
127 | GPIO19_GPIO, /* t7l66xb #PCLR */ | ||
128 | GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ | ||
129 | |||
130 | /* UDC */ | ||
131 | GPIO13_GPIO, | ||
132 | GPIO3_GPIO, | ||
133 | |||
134 | /* IrDA */ | ||
135 | GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, | ||
120 | 136 | ||
121 | /* PC Card */ | 137 | /* PC Card */ |
122 | GPIO8_GPIO, /* CD0 */ | 138 | GPIO8_GPIO, /* CD0 */ |
@@ -142,17 +158,43 @@ static unsigned long e740_pin_config[] __initdata = { | |||
142 | GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, | 158 | GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, |
143 | }; | 159 | }; |
144 | 160 | ||
161 | /* -------------------- e740 t7l66xb parameters -------------------- */ | ||
162 | |||
163 | static struct t7l66xb_platform_data e740_t7l66xb_info = { | ||
164 | .irq_base = IRQ_BOARD_START, | ||
165 | .enable = &eseries_tmio_enable, | ||
166 | .suspend = &eseries_tmio_suspend, | ||
167 | .resume = &eseries_tmio_resume, | ||
168 | }; | ||
169 | |||
170 | static struct platform_device e740_t7l66xb_device = { | ||
171 | .name = "t7l66xb", | ||
172 | .id = -1, | ||
173 | .dev = { | ||
174 | .platform_data = &e740_t7l66xb_info, | ||
175 | }, | ||
176 | .num_resources = 2, | ||
177 | .resource = eseries_tmio_resources, | ||
178 | }; | ||
179 | |||
145 | /* ----------------------------------------------------------------------- */ | 180 | /* ----------------------------------------------------------------------- */ |
146 | 181 | ||
147 | static struct platform_device *devices[] __initdata = { | 182 | static struct platform_device *devices[] __initdata = { |
148 | &e740_fb_device, | 183 | &e740_fb_device, |
184 | &e740_t7l66xb_device, | ||
149 | }; | 185 | }; |
150 | 186 | ||
151 | static void __init e740_init(void) | 187 | static void __init e740_init(void) |
152 | { | 188 | { |
153 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); | 189 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); |
190 | eseries_register_clks(); | ||
191 | clk_add_alias("CLK_CK48M", &e740_t7l66xb_device.dev, | ||
192 | "UDCCLK", &pxa25x_device_udc.dev), | ||
193 | eseries_get_tmio_gpios(); | ||
154 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 194 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
155 | pxa_set_udc_info(&e7xx_udc_mach_info); | 195 | pxa_set_udc_info(&e7xx_udc_mach_info); |
196 | e7xx_irda_init(); | ||
197 | pxa_set_ficp_info(&e7xx_ficp_platform_data); | ||
156 | } | 198 | } |
157 | 199 | ||
158 | MACHINE_START(E740, "Toshiba e740") | 200 | MACHINE_START(E740, "Toshiba e740") |
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index 640e738b85df..84d7c1aac58d 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/device.h> | 15 | #include <linux/device.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/fb.h> | 17 | #include <linux/fb.h> |
18 | #include <linux/mfd/tc6393xb.h> | ||
18 | 19 | ||
19 | #include <video/w100fb.h> | 20 | #include <video/w100fb.h> |
20 | 21 | ||
@@ -23,11 +24,15 @@ | |||
23 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
24 | 25 | ||
25 | #include <mach/mfp-pxa25x.h> | 26 | #include <mach/mfp-pxa25x.h> |
27 | #include <mach/pxa-regs.h> | ||
26 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
29 | #include <mach/eseries-gpio.h> | ||
27 | #include <mach/udc.h> | 30 | #include <mach/udc.h> |
31 | #include <mach/irda.h> | ||
28 | 32 | ||
29 | #include "generic.h" | 33 | #include "generic.h" |
30 | #include "eseries.h" | 34 | #include "eseries.h" |
35 | #include "clock.h" | ||
31 | 36 | ||
32 | /* ---------------------- E750 LCD definitions -------------------- */ | 37 | /* ---------------------- E750 LCD definitions -------------------- */ |
33 | 38 | ||
@@ -100,16 +105,45 @@ static struct platform_device e750_fb_device = { | |||
100 | .resource = e750_fb_resources, | 105 | .resource = e750_fb_resources, |
101 | }; | 106 | }; |
102 | 107 | ||
103 | /* ----------------------------------------------------------------------- */ | 108 | /* ----------------- e750 tc6393xb parameters ------------------ */ |
109 | |||
110 | static struct tc6393xb_platform_data e750_tc6393xb_info = { | ||
111 | .irq_base = IRQ_BOARD_START, | ||
112 | .scr_pll2cr = 0x0cc1, | ||
113 | .scr_gper = 0, | ||
114 | .gpio_base = -1, | ||
115 | .suspend = &eseries_tmio_suspend, | ||
116 | .resume = &eseries_tmio_resume, | ||
117 | .enable = &eseries_tmio_enable, | ||
118 | .disable = &eseries_tmio_disable, | ||
119 | }; | ||
120 | |||
121 | static struct platform_device e750_tc6393xb_device = { | ||
122 | .name = "tc6393xb", | ||
123 | .id = -1, | ||
124 | .dev = { | ||
125 | .platform_data = &e750_tc6393xb_info, | ||
126 | }, | ||
127 | .num_resources = 2, | ||
128 | .resource = eseries_tmio_resources, | ||
129 | }; | ||
130 | |||
131 | /* ------------------------------------------------------------- */ | ||
104 | 132 | ||
105 | static struct platform_device *devices[] __initdata = { | 133 | static struct platform_device *devices[] __initdata = { |
106 | &e750_fb_device, | 134 | &e750_fb_device, |
135 | &e750_tc6393xb_device, | ||
107 | }; | 136 | }; |
108 | 137 | ||
109 | static void __init e750_init(void) | 138 | static void __init e750_init(void) |
110 | { | 139 | { |
140 | clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev, | ||
141 | "GPIO11_CLK", NULL), | ||
142 | eseries_get_tmio_gpios(); | ||
111 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 143 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
112 | pxa_set_udc_info(&e7xx_udc_mach_info); | 144 | pxa_set_udc_info(&e7xx_udc_mach_info); |
145 | e7xx_irda_init(); | ||
146 | pxa_set_ficp_info(&e7xx_ficp_platform_data); | ||
113 | } | 147 | } |
114 | 148 | ||
115 | MACHINE_START(E750, "Toshiba e750") | 149 | MACHINE_START(E750, "Toshiba e750") |
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c index a293e09bfe25..9a86a426f924 100644 --- a/arch/arm/mach-pxa/e800.c +++ b/arch/arm/mach-pxa/e800.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/device.h> | 15 | #include <linux/device.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/fb.h> | 17 | #include <linux/fb.h> |
18 | #include <linux/mfd/tc6393xb.h> | ||
18 | 19 | ||
19 | #include <video/w100fb.h> | 20 | #include <video/w100fb.h> |
20 | 21 | ||
@@ -23,12 +24,14 @@ | |||
23 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
24 | 25 | ||
25 | #include <mach/mfp-pxa25x.h> | 26 | #include <mach/mfp-pxa25x.h> |
27 | #include <mach/pxa-regs.h> | ||
26 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
27 | #include <mach/eseries-gpio.h> | 29 | #include <mach/eseries-gpio.h> |
28 | #include <mach/udc.h> | 30 | #include <mach/udc.h> |
29 | 31 | ||
30 | #include "generic.h" | 32 | #include "generic.h" |
31 | #include "eseries.h" | 33 | #include "eseries.h" |
34 | #include "clock.h" | ||
32 | 35 | ||
33 | /* ------------------------ e800 LCD definitions ------------------------- */ | 36 | /* ------------------------ e800 LCD definitions ------------------------- */ |
34 | 37 | ||
@@ -160,14 +163,41 @@ static struct pxa2xx_udc_mach_info e800_udc_mach_info = { | |||
160 | .gpio_pullup_inverted = 1 | 163 | .gpio_pullup_inverted = 1 |
161 | }; | 164 | }; |
162 | 165 | ||
166 | /* ----------------- e800 tc6393xb parameters ------------------ */ | ||
167 | |||
168 | static struct tc6393xb_platform_data e800_tc6393xb_info = { | ||
169 | .irq_base = IRQ_BOARD_START, | ||
170 | .scr_pll2cr = 0x0cc1, | ||
171 | .scr_gper = 0, | ||
172 | .gpio_base = -1, | ||
173 | .suspend = &eseries_tmio_suspend, | ||
174 | .resume = &eseries_tmio_resume, | ||
175 | .enable = &eseries_tmio_enable, | ||
176 | .disable = &eseries_tmio_disable, | ||
177 | }; | ||
178 | |||
179 | static struct platform_device e800_tc6393xb_device = { | ||
180 | .name = "tc6393xb", | ||
181 | .id = -1, | ||
182 | .dev = { | ||
183 | .platform_data = &e800_tc6393xb_info, | ||
184 | }, | ||
185 | .num_resources = 2, | ||
186 | .resource = eseries_tmio_resources, | ||
187 | }; | ||
188 | |||
163 | /* ----------------------------------------------------------------------- */ | 189 | /* ----------------------------------------------------------------------- */ |
164 | 190 | ||
165 | static struct platform_device *devices[] __initdata = { | 191 | static struct platform_device *devices[] __initdata = { |
166 | &e800_fb_device, | 192 | &e800_fb_device, |
193 | &e800_tc6393xb_device, | ||
167 | }; | 194 | }; |
168 | 195 | ||
169 | static void __init e800_init(void) | 196 | static void __init e800_init(void) |
170 | { | 197 | { |
198 | clk_add_alias("CLK_CK3P6MI", &e800_tc6393xb_device.dev, | ||
199 | "GPIO11_CLK", NULL), | ||
200 | eseries_get_tmio_gpios(); | ||
171 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 201 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
172 | pxa_set_udc_info(&e800_udc_mach_info); | 202 | pxa_set_udc_info(&e800_udc_mach_info); |
173 | } | 203 | } |
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index d28849b50a14..dfce7d5b659e 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c | |||
@@ -12,6 +12,9 @@ | |||
12 | 12 | ||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/gpio.h> | ||
16 | #include <linux/delay.h> | ||
17 | #include <linux/platform_device.h> | ||
15 | 18 | ||
16 | #include <asm/setup.h> | 19 | #include <asm/setup.h> |
17 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
@@ -21,8 +24,10 @@ | |||
21 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
22 | #include <mach/eseries-gpio.h> | 25 | #include <mach/eseries-gpio.h> |
23 | #include <mach/udc.h> | 26 | #include <mach/udc.h> |
27 | #include <mach/irda.h> | ||
24 | 28 | ||
25 | #include "generic.h" | 29 | #include "generic.h" |
30 | #include "clock.h" | ||
26 | 31 | ||
27 | /* Only e800 has 128MB RAM */ | 32 | /* Only e800 has 128MB RAM */ |
28 | void __init eseries_fixup(struct machine_desc *desc, | 33 | void __init eseries_fixup(struct machine_desc *desc, |
@@ -43,3 +48,122 @@ struct pxa2xx_udc_mach_info e7xx_udc_mach_info = { | |||
43 | .gpio_pullup_inverted = 1 | 48 | .gpio_pullup_inverted = 1 |
44 | }; | 49 | }; |
45 | 50 | ||
51 | static void e7xx_irda_transceiver_mode(struct device *dev, int mode) | ||
52 | { | ||
53 | if (mode & IR_OFF) { | ||
54 | gpio_set_value(GPIO_E7XX_IR_OFF, 1); | ||
55 | pxa2xx_transceiver_mode(dev, mode); | ||
56 | } else { | ||
57 | pxa2xx_transceiver_mode(dev, mode); | ||
58 | gpio_set_value(GPIO_E7XX_IR_OFF, 0); | ||
59 | } | ||
60 | } | ||
61 | |||
62 | int e7xx_irda_init(void) | ||
63 | { | ||
64 | int ret; | ||
65 | |||
66 | ret = gpio_request(GPIO_E7XX_IR_OFF, "IrDA power"); | ||
67 | if (ret) | ||
68 | goto out; | ||
69 | |||
70 | ret = gpio_direction_output(GPIO_E7XX_IR_OFF, 0); | ||
71 | if (ret) | ||
72 | goto out; | ||
73 | |||
74 | e7xx_irda_transceiver_mode(NULL, IR_SIRMODE | IR_OFF); | ||
75 | out: | ||
76 | return ret; | ||
77 | } | ||
78 | |||
79 | static void e7xx_irda_shutdown(struct device *dev) | ||
80 | { | ||
81 | e7xx_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF); | ||
82 | gpio_free(GPIO_E7XX_IR_OFF); | ||
83 | } | ||
84 | |||
85 | struct pxaficp_platform_data e7xx_ficp_platform_data = { | ||
86 | .transceiver_cap = IR_SIRMODE | IR_OFF, | ||
87 | .transceiver_mode = e7xx_irda_transceiver_mode, | ||
88 | .shutdown = e7xx_irda_shutdown, | ||
89 | }; | ||
90 | |||
91 | int eseries_tmio_enable(struct platform_device *dev) | ||
92 | { | ||
93 | /* Reset - bring SUSPEND high before PCLR */ | ||
94 | gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); | ||
95 | gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0); | ||
96 | msleep(1); | ||
97 | gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1); | ||
98 | msleep(1); | ||
99 | gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 1); | ||
100 | msleep(1); | ||
101 | return 0; | ||
102 | } | ||
103 | |||
104 | int eseries_tmio_disable(struct platform_device *dev) | ||
105 | { | ||
106 | gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); | ||
107 | gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0); | ||
108 | return 0; | ||
109 | } | ||
110 | |||
111 | int eseries_tmio_suspend(struct platform_device *dev) | ||
112 | { | ||
113 | gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); | ||
114 | return 0; | ||
115 | } | ||
116 | |||
117 | int eseries_tmio_resume(struct platform_device *dev) | ||
118 | { | ||
119 | gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1); | ||
120 | msleep(1); | ||
121 | return 0; | ||
122 | } | ||
123 | |||
124 | void eseries_get_tmio_gpios(void) | ||
125 | { | ||
126 | gpio_request(GPIO_ESERIES_TMIO_SUSPEND, NULL); | ||
127 | gpio_request(GPIO_ESERIES_TMIO_PCLR, NULL); | ||
128 | gpio_direction_output(GPIO_ESERIES_TMIO_SUSPEND, 0); | ||
129 | gpio_direction_output(GPIO_ESERIES_TMIO_PCLR, 0); | ||
130 | } | ||
131 | |||
132 | /* TMIO controller uses the same resources on all e-series machines. */ | ||
133 | struct resource eseries_tmio_resources[] = { | ||
134 | [0] = { | ||
135 | .start = PXA_CS4_PHYS, | ||
136 | .end = PXA_CS4_PHYS + 0x1fffff, | ||
137 | .flags = IORESOURCE_MEM, | ||
138 | }, | ||
139 | [1] = { | ||
140 | .start = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), | ||
141 | .end = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), | ||
142 | .flags = IORESOURCE_IRQ, | ||
143 | }, | ||
144 | }; | ||
145 | |||
146 | /* Some e-series hardware cannot control the 32K clock */ | ||
147 | static void clk_32k_dummy(struct clk *clk) | ||
148 | { | ||
149 | } | ||
150 | |||
151 | static const struct clkops clk_32k_dummy_ops = { | ||
152 | .enable = clk_32k_dummy, | ||
153 | .disable = clk_32k_dummy, | ||
154 | }; | ||
155 | |||
156 | static struct clk tmio_dummy_clk = { | ||
157 | .ops = &clk_32k_dummy_ops, | ||
158 | .rate = 32768, | ||
159 | }; | ||
160 | |||
161 | static struct clk_lookup eseries_clkregs[] = { | ||
162 | INIT_CLKREG(&tmio_dummy_clk, NULL, "CLK_CK32K"), | ||
163 | }; | ||
164 | |||
165 | void eseries_register_clks(void) | ||
166 | { | ||
167 | clks_register(eseries_clkregs, ARRAY_SIZE(eseries_clkregs)); | ||
168 | } | ||
169 | |||
diff --git a/arch/arm/mach-pxa/eseries.h b/arch/arm/mach-pxa/eseries.h index a83f88d4b6ad..5930f5e2a123 100644 --- a/arch/arm/mach-pxa/eseries.h +++ b/arch/arm/mach-pxa/eseries.h | |||
@@ -2,3 +2,15 @@ void __init eseries_fixup(struct machine_desc *desc, | |||
2 | struct tag *tags, char **cmdline, struct meminfo *mi); | 2 | struct tag *tags, char **cmdline, struct meminfo *mi); |
3 | 3 | ||
4 | extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info; | 4 | extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info; |
5 | extern struct pxaficp_platform_data e7xx_ficp_platform_data; | ||
6 | extern int e7xx_irda_init(void); | ||
7 | |||
8 | extern int eseries_tmio_enable(struct platform_device *dev); | ||
9 | extern int eseries_tmio_disable(struct platform_device *dev); | ||
10 | extern int eseries_tmio_suspend(struct platform_device *dev); | ||
11 | extern int eseries_tmio_resume(struct platform_device *dev); | ||
12 | extern void eseries_get_tmio_gpios(void); | ||
13 | extern struct resource eseries_tmio_resources[]; | ||
14 | extern struct platform_device e300_tc6387xb_device; | ||
15 | extern void eseries_register_clks(void); | ||
16 | |||
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index cc3d850cc0b6..df5f822f3b6c 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c | |||
@@ -16,11 +16,14 @@ | |||
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
18 | #include <linux/pwm_backlight.h> | 18 | #include <linux/pwm_backlight.h> |
19 | #include <linux/input.h> | ||
19 | 20 | ||
20 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
21 | #include <mach/pxafb.h> | 22 | #include <mach/pxafb.h> |
22 | #include <mach/ohci.h> | 23 | #include <mach/ohci.h> |
23 | #include <mach/i2c.h> | 24 | #include <mach/i2c.h> |
25 | #include <mach/hardware.h> | ||
26 | #include <mach/pxa27x_keypad.h> | ||
24 | 27 | ||
25 | #include <mach/mfp-pxa27x.h> | 28 | #include <mach/mfp-pxa27x.h> |
26 | #include <mach/pxa-regs.h> | 29 | #include <mach/pxa-regs.h> |
@@ -101,120 +104,732 @@ static unsigned long ezx_pin_config[] __initdata = { | |||
101 | GPIO44_BTUART_CTS, | 104 | GPIO44_BTUART_CTS, |
102 | GPIO45_BTUART_RTS, | 105 | GPIO45_BTUART_RTS, |
103 | 106 | ||
104 | /* STUART */ | 107 | /* I2C */ |
105 | GPIO46_STUART_RXD, | 108 | GPIO117_I2C_SCL, |
106 | GPIO47_STUART_TXD, | 109 | GPIO118_I2C_SDA, |
107 | 110 | ||
108 | /* For A780 support (connected with Neptune GSM chip) */ | 111 | /* PCAP SSP */ |
109 | GPIO30_USB_P3_2, /* ICL_TXENB */ | 112 | GPIO29_SSP1_SCLK, |
110 | GPIO31_USB_P3_6, /* ICL_VPOUT */ | 113 | GPIO25_SSP1_TXD, |
111 | GPIO90_USB_P3_5, /* ICL_VPIN */ | 114 | GPIO26_SSP1_RXD, |
112 | GPIO91_USB_P3_1, /* ICL_XRXD */ | 115 | GPIO24_GPIO, /* pcap chip select */ |
113 | GPIO56_USB_P3_4, /* ICL_VMOUT */ | 116 | GPIO1_GPIO, /* pcap interrupt */ |
114 | GPIO113_USB_P3_3, /* /ICL_VMIN */ | 117 | GPIO4_GPIO, /* WDI_AP */ |
118 | GPIO55_GPIO, /* SYS_RESTART */ | ||
119 | |||
120 | /* MMC */ | ||
121 | GPIO32_MMC_CLK, | ||
122 | GPIO92_MMC_DAT_0, | ||
123 | GPIO109_MMC_DAT_1, | ||
124 | GPIO110_MMC_DAT_2, | ||
125 | GPIO111_MMC_DAT_3, | ||
126 | GPIO112_MMC_CMD, | ||
127 | GPIO11_GPIO, /* mmc detect */ | ||
128 | |||
129 | /* usb to external transceiver */ | ||
130 | GPIO34_USB_P2_2, | ||
131 | GPIO35_USB_P2_1, | ||
132 | GPIO36_USB_P2_4, | ||
133 | GPIO39_USB_P2_6, | ||
134 | GPIO40_USB_P2_5, | ||
135 | GPIO53_USB_P2_3, | ||
136 | |||
137 | /* usb to Neptune GSM chip */ | ||
138 | GPIO30_USB_P3_2, | ||
139 | GPIO31_USB_P3_6, | ||
140 | GPIO90_USB_P3_5, | ||
141 | GPIO91_USB_P3_1, | ||
142 | GPIO56_USB_P3_4, | ||
143 | GPIO113_USB_P3_3, | ||
144 | }; | ||
145 | |||
146 | #if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_E680) | ||
147 | static unsigned long gen1_pin_config[] __initdata = { | ||
148 | /* flip / lockswitch */ | ||
149 | GPIO12_GPIO, | ||
150 | |||
151 | /* bluetooth (bcm2035) */ | ||
152 | GPIO14_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ | ||
153 | GPIO48_GPIO, /* RESET */ | ||
154 | GPIO28_GPIO, /* WAKEUP */ | ||
155 | |||
156 | /* Neptune handshake */ | ||
157 | GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ | ||
158 | GPIO57_GPIO, /* AP_RDY */ | ||
159 | GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ | ||
160 | GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI2 */ | ||
161 | GPIO82_GPIO, /* RESET */ | ||
162 | GPIO99_GPIO, /* TC_MM_EN */ | ||
163 | |||
164 | /* sound */ | ||
165 | GPIO52_SSP3_SCLK, | ||
166 | GPIO83_SSP3_SFRM, | ||
167 | GPIO81_SSP3_TXD, | ||
168 | GPIO89_SSP3_RXD, | ||
169 | |||
170 | /* ssp2 pins to in */ | ||
171 | GPIO22_GPIO, /* SSP2_SCLK */ | ||
172 | GPIO37_GPIO, /* SSP2_SFRM */ | ||
173 | GPIO38_GPIO, /* SSP2_TXD */ | ||
174 | GPIO88_GPIO, /* SSP2_RXD */ | ||
175 | |||
176 | /* camera */ | ||
177 | GPIO23_CIF_MCLK, | ||
178 | GPIO54_CIF_PCLK, | ||
179 | GPIO85_CIF_LV, | ||
180 | GPIO84_CIF_FV, | ||
181 | GPIO27_CIF_DD_0, | ||
182 | GPIO114_CIF_DD_1, | ||
183 | GPIO51_CIF_DD_2, | ||
184 | GPIO115_CIF_DD_3, | ||
185 | GPIO95_CIF_DD_4, | ||
186 | GPIO94_CIF_DD_5, | ||
187 | GPIO17_CIF_DD_6, | ||
188 | GPIO108_CIF_DD_7, | ||
189 | GPIO50_GPIO, /* CAM_EN */ | ||
190 | GPIO19_GPIO, /* CAM_RST */ | ||
191 | |||
192 | /* EMU */ | ||
193 | GPIO120_GPIO, /* EMU_MUX1 */ | ||
194 | GPIO119_GPIO, /* EMU_MUX2 */ | ||
195 | GPIO86_GPIO, /* SNP_INT_CTL */ | ||
196 | GPIO87_GPIO, /* SNP_INT_IN */ | ||
197 | }; | ||
198 | #endif | ||
199 | |||
200 | #if defined(CONFIG_MACH_EZX_A1200) || defined(CONFIG_MACH_EZX_A910) || \ | ||
201 | defined(CONFIG_MACH_EZX_E2) || defined(CONFIG_MACH_EZX_E6) | ||
202 | static unsigned long gen2_pin_config[] __initdata = { | ||
203 | /* flip / lockswitch */ | ||
204 | GPIO15_GPIO, | ||
205 | |||
206 | /* EOC */ | ||
207 | GPIO10_GPIO, | ||
208 | |||
209 | /* bluetooth (bcm2045) */ | ||
210 | GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ | ||
211 | GPIO37_GPIO, /* RESET */ | ||
212 | GPIO57_GPIO, /* WAKEUP */ | ||
213 | |||
214 | /* Neptune handshake */ | ||
215 | GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ | ||
216 | GPIO96_GPIO, /* AP_RDY */ | ||
217 | GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ | ||
218 | GPIO116_GPIO, /* RESET */ | ||
219 | GPIO41_GPIO, /* BP_FLASH */ | ||
220 | |||
221 | /* sound */ | ||
222 | GPIO52_SSP3_SCLK, | ||
223 | GPIO83_SSP3_SFRM, | ||
224 | GPIO81_SSP3_TXD, | ||
225 | GPIO82_SSP3_RXD, | ||
226 | |||
227 | /* ssp2 pins to in */ | ||
228 | GPIO22_GPIO, /* SSP2_SCLK */ | ||
229 | GPIO14_GPIO, /* SSP2_SFRM */ | ||
230 | GPIO38_GPIO, /* SSP2_TXD */ | ||
231 | GPIO88_GPIO, /* SSP2_RXD */ | ||
232 | |||
233 | /* camera */ | ||
234 | GPIO23_CIF_MCLK, | ||
235 | GPIO54_CIF_PCLK, | ||
236 | GPIO85_CIF_LV, | ||
237 | GPIO84_CIF_FV, | ||
238 | GPIO27_CIF_DD_0, | ||
239 | GPIO114_CIF_DD_1, | ||
240 | GPIO51_CIF_DD_2, | ||
241 | GPIO115_CIF_DD_3, | ||
242 | GPIO95_CIF_DD_4, | ||
243 | GPIO48_CIF_DD_5, | ||
244 | GPIO93_CIF_DD_6, | ||
245 | GPIO12_CIF_DD_7, | ||
246 | GPIO50_GPIO, /* CAM_EN */ | ||
247 | GPIO28_GPIO, /* CAM_RST */ | ||
248 | GPIO17_GPIO, /* CAM_FLASH */ | ||
249 | }; | ||
250 | #endif | ||
251 | |||
252 | #ifdef CONFIG_MACH_EZX_A780 | ||
253 | static unsigned long a780_pin_config[] __initdata = { | ||
254 | /* keypad */ | ||
255 | GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
256 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
257 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
258 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
259 | GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | ||
260 | GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | ||
261 | GPIO103_KP_MKOUT_0, | ||
262 | GPIO104_KP_MKOUT_1, | ||
263 | GPIO105_KP_MKOUT_2, | ||
264 | GPIO106_KP_MKOUT_3, | ||
265 | GPIO107_KP_MKOUT_4, | ||
266 | |||
267 | /* attenuate sound */ | ||
268 | GPIO96_GPIO, | ||
269 | }; | ||
270 | #endif | ||
271 | |||
272 | #ifdef CONFIG_MACH_EZX_E680 | ||
273 | static unsigned long e680_pin_config[] __initdata = { | ||
274 | /* keypad */ | ||
275 | GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
276 | GPIO96_KP_DKIN_3 | WAKEUP_ON_LEVEL_HIGH, | ||
277 | GPIO97_KP_DKIN_4 | WAKEUP_ON_LEVEL_HIGH, | ||
278 | GPIO98_KP_DKIN_5 | WAKEUP_ON_LEVEL_HIGH, | ||
279 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
280 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
281 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
282 | GPIO103_KP_MKOUT_0, | ||
283 | GPIO104_KP_MKOUT_1, | ||
284 | GPIO105_KP_MKOUT_2, | ||
285 | GPIO106_KP_MKOUT_3, | ||
286 | |||
287 | /* MIDI */ | ||
288 | GPIO79_GPIO, /* VA_SEL_BUL */ | ||
289 | GPIO80_GPIO, /* FLT_SEL_BUL */ | ||
290 | GPIO78_GPIO, /* MIDI_RESET */ | ||
291 | GPIO33_GPIO, /* MIDI_CS */ | ||
292 | GPIO15_GPIO, /* MIDI_IRQ */ | ||
293 | GPIO49_GPIO, /* MIDI_NPWE */ | ||
294 | GPIO18_GPIO, /* MIDI_RDY */ | ||
295 | |||
296 | /* leds */ | ||
297 | GPIO46_GPIO, | ||
298 | GPIO47_GPIO, | ||
299 | }; | ||
300 | #endif | ||
301 | |||
302 | #ifdef CONFIG_MACH_EZX_A1200 | ||
303 | static unsigned long a1200_pin_config[] __initdata = { | ||
304 | /* keypad */ | ||
305 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
306 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
307 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
308 | GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | ||
309 | GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | ||
310 | GPIO103_KP_MKOUT_0, | ||
311 | GPIO104_KP_MKOUT_1, | ||
312 | GPIO105_KP_MKOUT_2, | ||
313 | GPIO106_KP_MKOUT_3, | ||
314 | GPIO107_KP_MKOUT_4, | ||
315 | GPIO108_KP_MKOUT_5, | ||
316 | }; | ||
317 | #endif | ||
318 | |||
319 | #ifdef CONFIG_MACH_EZX_A910 | ||
320 | static unsigned long a910_pin_config[] __initdata = { | ||
321 | /* keypad */ | ||
322 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
323 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
324 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
325 | GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | ||
326 | GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | ||
327 | GPIO103_KP_MKOUT_0, | ||
328 | GPIO104_KP_MKOUT_1, | ||
329 | GPIO105_KP_MKOUT_2, | ||
330 | GPIO106_KP_MKOUT_3, | ||
331 | GPIO107_KP_MKOUT_4, | ||
332 | GPIO108_KP_MKOUT_5, | ||
333 | |||
334 | /* WLAN */ | ||
335 | GPIO89_GPIO, /* RESET */ | ||
336 | GPIO33_GPIO, /* WAKEUP */ | ||
337 | GPIO94_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ | ||
338 | |||
339 | /* MMC CS */ | ||
340 | GPIO20_GPIO, | ||
341 | }; | ||
342 | #endif | ||
343 | |||
344 | #ifdef CONFIG_MACH_EZX_E2 | ||
345 | static unsigned long e2_pin_config[] __initdata = { | ||
346 | /* keypad */ | ||
347 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
348 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
349 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
350 | GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | ||
351 | GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | ||
352 | GPIO103_KP_MKOUT_0, | ||
353 | GPIO104_KP_MKOUT_1, | ||
354 | GPIO105_KP_MKOUT_2, | ||
355 | GPIO106_KP_MKOUT_3, | ||
356 | GPIO107_KP_MKOUT_4, | ||
357 | GPIO108_KP_MKOUT_5, | ||
115 | }; | 358 | }; |
359 | #endif | ||
360 | |||
361 | #ifdef CONFIG_MACH_EZX_E6 | ||
362 | static unsigned long e6_pin_config[] __initdata = { | ||
363 | /* keypad */ | ||
364 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
365 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
366 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
367 | GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | ||
368 | GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | ||
369 | GPIO103_KP_MKOUT_0, | ||
370 | GPIO104_KP_MKOUT_1, | ||
371 | GPIO105_KP_MKOUT_2, | ||
372 | GPIO106_KP_MKOUT_3, | ||
373 | GPIO107_KP_MKOUT_4, | ||
374 | GPIO108_KP_MKOUT_5, | ||
375 | }; | ||
376 | #endif | ||
377 | |||
378 | /* KEYPAD */ | ||
379 | #ifdef CONFIG_MACH_EZX_A780 | ||
380 | static unsigned int a780_key_map[] = { | ||
381 | KEY(0, 0, KEY_SEND), | ||
382 | KEY(0, 1, KEY_BACK), | ||
383 | KEY(0, 2, KEY_END), | ||
384 | KEY(0, 3, KEY_PAGEUP), | ||
385 | KEY(0, 4, KEY_UP), | ||
386 | |||
387 | KEY(1, 0, KEY_NUMERIC_1), | ||
388 | KEY(1, 1, KEY_NUMERIC_2), | ||
389 | KEY(1, 2, KEY_NUMERIC_3), | ||
390 | KEY(1, 3, KEY_SELECT), | ||
391 | KEY(1, 4, KEY_KPENTER), | ||
392 | |||
393 | KEY(2, 0, KEY_NUMERIC_4), | ||
394 | KEY(2, 1, KEY_NUMERIC_5), | ||
395 | KEY(2, 2, KEY_NUMERIC_6), | ||
396 | KEY(2, 3, KEY_RECORD), | ||
397 | KEY(2, 4, KEY_LEFT), | ||
398 | |||
399 | KEY(3, 0, KEY_NUMERIC_7), | ||
400 | KEY(3, 1, KEY_NUMERIC_8), | ||
401 | KEY(3, 2, KEY_NUMERIC_9), | ||
402 | KEY(3, 3, KEY_HOME), | ||
403 | KEY(3, 4, KEY_RIGHT), | ||
404 | |||
405 | KEY(4, 0, KEY_NUMERIC_STAR), | ||
406 | KEY(4, 1, KEY_NUMERIC_0), | ||
407 | KEY(4, 2, KEY_NUMERIC_POUND), | ||
408 | KEY(4, 3, KEY_PAGEDOWN), | ||
409 | KEY(4, 4, KEY_DOWN), | ||
410 | }; | ||
411 | |||
412 | static struct pxa27x_keypad_platform_data a780_keypad_platform_data = { | ||
413 | .matrix_key_rows = 5, | ||
414 | .matrix_key_cols = 5, | ||
415 | .matrix_key_map = a780_key_map, | ||
416 | .matrix_key_map_size = ARRAY_SIZE(a780_key_map), | ||
417 | |||
418 | .direct_key_map = { KEY_CAMERA }, | ||
419 | .direct_key_num = 1, | ||
420 | |||
421 | .debounce_interval = 30, | ||
422 | }; | ||
423 | #endif /* CONFIG_MACH_EZX_A780 */ | ||
424 | |||
425 | #ifdef CONFIG_MACH_EZX_E680 | ||
426 | static unsigned int e680_key_map[] = { | ||
427 | KEY(0, 0, KEY_UP), | ||
428 | KEY(0, 1, KEY_RIGHT), | ||
429 | KEY(0, 2, KEY_RESERVED), | ||
430 | KEY(0, 3, KEY_SEND), | ||
431 | |||
432 | KEY(1, 0, KEY_DOWN), | ||
433 | KEY(1, 1, KEY_LEFT), | ||
434 | KEY(1, 2, KEY_PAGEUP), | ||
435 | KEY(1, 3, KEY_PAGEDOWN), | ||
436 | |||
437 | KEY(2, 0, KEY_RESERVED), | ||
438 | KEY(2, 1, KEY_RESERVED), | ||
439 | KEY(2, 2, KEY_RESERVED), | ||
440 | KEY(2, 3, KEY_KPENTER), | ||
441 | }; | ||
442 | |||
443 | static struct pxa27x_keypad_platform_data e680_keypad_platform_data = { | ||
444 | .matrix_key_rows = 3, | ||
445 | .matrix_key_cols = 4, | ||
446 | .matrix_key_map = e680_key_map, | ||
447 | .matrix_key_map_size = ARRAY_SIZE(e680_key_map), | ||
448 | |||
449 | .direct_key_map = { | ||
450 | KEY_CAMERA, | ||
451 | KEY_RESERVED, | ||
452 | KEY_RESERVED, | ||
453 | KEY_F1, | ||
454 | KEY_CANCEL, | ||
455 | KEY_F2, | ||
456 | }, | ||
457 | .direct_key_num = 6, | ||
458 | |||
459 | .debounce_interval = 30, | ||
460 | }; | ||
461 | #endif /* CONFIG_MACH_EZX_E680 */ | ||
462 | |||
463 | #ifdef CONFIG_MACH_EZX_A1200 | ||
464 | static unsigned int a1200_key_map[] = { | ||
465 | KEY(0, 0, KEY_RESERVED), | ||
466 | KEY(0, 1, KEY_RIGHT), | ||
467 | KEY(0, 2, KEY_PAGEDOWN), | ||
468 | KEY(0, 3, KEY_RESERVED), | ||
469 | KEY(0, 4, KEY_RESERVED), | ||
470 | KEY(0, 5, KEY_RESERVED), | ||
471 | |||
472 | KEY(1, 0, KEY_RESERVED), | ||
473 | KEY(1, 1, KEY_DOWN), | ||
474 | KEY(1, 2, KEY_CAMERA), | ||
475 | KEY(1, 3, KEY_RESERVED), | ||
476 | KEY(1, 4, KEY_RESERVED), | ||
477 | KEY(1, 5, KEY_RESERVED), | ||
478 | |||
479 | KEY(2, 0, KEY_RESERVED), | ||
480 | KEY(2, 1, KEY_KPENTER), | ||
481 | KEY(2, 2, KEY_RECORD), | ||
482 | KEY(2, 3, KEY_RESERVED), | ||
483 | KEY(2, 4, KEY_RESERVED), | ||
484 | KEY(2, 5, KEY_SELECT), | ||
485 | |||
486 | KEY(3, 0, KEY_RESERVED), | ||
487 | KEY(3, 1, KEY_UP), | ||
488 | KEY(3, 2, KEY_SEND), | ||
489 | KEY(3, 3, KEY_RESERVED), | ||
490 | KEY(3, 4, KEY_RESERVED), | ||
491 | KEY(3, 5, KEY_RESERVED), | ||
492 | |||
493 | KEY(4, 0, KEY_RESERVED), | ||
494 | KEY(4, 1, KEY_LEFT), | ||
495 | KEY(4, 2, KEY_PAGEUP), | ||
496 | KEY(4, 3, KEY_RESERVED), | ||
497 | KEY(4, 4, KEY_RESERVED), | ||
498 | KEY(4, 5, KEY_RESERVED), | ||
499 | }; | ||
500 | |||
501 | static struct pxa27x_keypad_platform_data a1200_keypad_platform_data = { | ||
502 | .matrix_key_rows = 5, | ||
503 | .matrix_key_cols = 6, | ||
504 | .matrix_key_map = a1200_key_map, | ||
505 | .matrix_key_map_size = ARRAY_SIZE(a1200_key_map), | ||
506 | |||
507 | .debounce_interval = 30, | ||
508 | }; | ||
509 | #endif /* CONFIG_MACH_EZX_A1200 */ | ||
510 | |||
511 | #ifdef CONFIG_MACH_EZX_E6 | ||
512 | static unsigned int e6_key_map[] = { | ||
513 | KEY(0, 0, KEY_RESERVED), | ||
514 | KEY(0, 1, KEY_RIGHT), | ||
515 | KEY(0, 2, KEY_PAGEDOWN), | ||
516 | KEY(0, 3, KEY_RESERVED), | ||
517 | KEY(0, 4, KEY_RESERVED), | ||
518 | KEY(0, 5, KEY_NEXTSONG), | ||
519 | |||
520 | KEY(1, 0, KEY_RESERVED), | ||
521 | KEY(1, 1, KEY_DOWN), | ||
522 | KEY(1, 2, KEY_PROG1), | ||
523 | KEY(1, 3, KEY_RESERVED), | ||
524 | KEY(1, 4, KEY_RESERVED), | ||
525 | KEY(1, 5, KEY_RESERVED), | ||
526 | |||
527 | KEY(2, 0, KEY_RESERVED), | ||
528 | KEY(2, 1, KEY_ENTER), | ||
529 | KEY(2, 2, KEY_CAMERA), | ||
530 | KEY(2, 3, KEY_RESERVED), | ||
531 | KEY(2, 4, KEY_RESERVED), | ||
532 | KEY(2, 5, KEY_WWW), | ||
533 | |||
534 | KEY(3, 0, KEY_RESERVED), | ||
535 | KEY(3, 1, KEY_UP), | ||
536 | KEY(3, 2, KEY_SEND), | ||
537 | KEY(3, 3, KEY_RESERVED), | ||
538 | KEY(3, 4, KEY_RESERVED), | ||
539 | KEY(3, 5, KEY_PLAYPAUSE), | ||
540 | |||
541 | KEY(4, 0, KEY_RESERVED), | ||
542 | KEY(4, 1, KEY_LEFT), | ||
543 | KEY(4, 2, KEY_PAGEUP), | ||
544 | KEY(4, 3, KEY_RESERVED), | ||
545 | KEY(4, 4, KEY_RESERVED), | ||
546 | KEY(4, 5, KEY_PREVIOUSSONG), | ||
547 | }; | ||
548 | |||
549 | static struct pxa27x_keypad_platform_data e6_keypad_platform_data = { | ||
550 | .matrix_key_rows = 5, | ||
551 | .matrix_key_cols = 6, | ||
552 | .matrix_key_map = e6_key_map, | ||
553 | .matrix_key_map_size = ARRAY_SIZE(e6_key_map), | ||
116 | 554 | ||
117 | static void __init ezx_init(void) | 555 | .debounce_interval = 30, |
556 | }; | ||
557 | #endif /* CONFIG_MACH_EZX_E6 */ | ||
558 | |||
559 | #ifdef CONFIG_MACH_EZX_A910 | ||
560 | static unsigned int a910_key_map[] = { | ||
561 | KEY(0, 0, KEY_NUMERIC_6), | ||
562 | KEY(0, 1, KEY_RIGHT), | ||
563 | KEY(0, 2, KEY_PAGEDOWN), | ||
564 | KEY(0, 3, KEY_KPENTER), | ||
565 | KEY(0, 4, KEY_NUMERIC_5), | ||
566 | KEY(0, 5, KEY_CAMERA), | ||
567 | |||
568 | KEY(1, 0, KEY_NUMERIC_8), | ||
569 | KEY(1, 1, KEY_DOWN), | ||
570 | KEY(1, 2, KEY_RESERVED), | ||
571 | KEY(1, 3, KEY_F1), /* Left SoftKey */ | ||
572 | KEY(1, 4, KEY_NUMERIC_STAR), | ||
573 | KEY(1, 5, KEY_RESERVED), | ||
574 | |||
575 | KEY(2, 0, KEY_NUMERIC_7), | ||
576 | KEY(2, 1, KEY_NUMERIC_9), | ||
577 | KEY(2, 2, KEY_RECORD), | ||
578 | KEY(2, 3, KEY_F2), /* Right SoftKey */ | ||
579 | KEY(2, 4, KEY_BACK), | ||
580 | KEY(2, 5, KEY_SELECT), | ||
581 | |||
582 | KEY(3, 0, KEY_NUMERIC_2), | ||
583 | KEY(3, 1, KEY_UP), | ||
584 | KEY(3, 2, KEY_SEND), | ||
585 | KEY(3, 3, KEY_NUMERIC_0), | ||
586 | KEY(3, 4, KEY_NUMERIC_1), | ||
587 | KEY(3, 5, KEY_RECORD), | ||
588 | |||
589 | KEY(4, 0, KEY_NUMERIC_4), | ||
590 | KEY(4, 1, KEY_LEFT), | ||
591 | KEY(4, 2, KEY_PAGEUP), | ||
592 | KEY(4, 3, KEY_NUMERIC_POUND), | ||
593 | KEY(4, 4, KEY_NUMERIC_3), | ||
594 | KEY(4, 5, KEY_RESERVED), | ||
595 | }; | ||
596 | |||
597 | static struct pxa27x_keypad_platform_data a910_keypad_platform_data = { | ||
598 | .matrix_key_rows = 5, | ||
599 | .matrix_key_cols = 6, | ||
600 | .matrix_key_map = a910_key_map, | ||
601 | .matrix_key_map_size = ARRAY_SIZE(a910_key_map), | ||
602 | |||
603 | .debounce_interval = 30, | ||
604 | }; | ||
605 | #endif /* CONFIG_MACH_EZX_A910 */ | ||
606 | |||
607 | #ifdef CONFIG_MACH_EZX_E2 | ||
608 | static unsigned int e2_key_map[] = { | ||
609 | KEY(0, 0, KEY_NUMERIC_6), | ||
610 | KEY(0, 1, KEY_RIGHT), | ||
611 | KEY(0, 2, KEY_NUMERIC_9), | ||
612 | KEY(0, 3, KEY_NEXTSONG), | ||
613 | KEY(0, 4, KEY_NUMERIC_5), | ||
614 | KEY(0, 5, KEY_F1), /* Left SoftKey */ | ||
615 | |||
616 | KEY(1, 0, KEY_NUMERIC_8), | ||
617 | KEY(1, 1, KEY_DOWN), | ||
618 | KEY(1, 2, KEY_RESERVED), | ||
619 | KEY(1, 3, KEY_PAGEUP), | ||
620 | KEY(1, 4, KEY_NUMERIC_STAR), | ||
621 | KEY(1, 5, KEY_F2), /* Right SoftKey */ | ||
622 | |||
623 | KEY(2, 0, KEY_NUMERIC_7), | ||
624 | KEY(2, 1, KEY_KPENTER), | ||
625 | KEY(2, 2, KEY_RECORD), | ||
626 | KEY(2, 3, KEY_PAGEDOWN), | ||
627 | KEY(2, 4, KEY_BACK), | ||
628 | KEY(2, 5, KEY_NUMERIC_0), | ||
629 | |||
630 | KEY(3, 0, KEY_NUMERIC_2), | ||
631 | KEY(3, 1, KEY_UP), | ||
632 | KEY(3, 2, KEY_SEND), | ||
633 | KEY(3, 3, KEY_PLAYPAUSE), | ||
634 | KEY(3, 4, KEY_NUMERIC_1), | ||
635 | KEY(3, 5, KEY_SOUND), /* Music SoftKey */ | ||
636 | |||
637 | KEY(4, 0, KEY_NUMERIC_4), | ||
638 | KEY(4, 1, KEY_LEFT), | ||
639 | KEY(4, 2, KEY_NUMERIC_POUND), | ||
640 | KEY(4, 3, KEY_PREVIOUSSONG), | ||
641 | KEY(4, 4, KEY_NUMERIC_3), | ||
642 | KEY(4, 5, KEY_RESERVED), | ||
643 | }; | ||
644 | |||
645 | static struct pxa27x_keypad_platform_data e2_keypad_platform_data = { | ||
646 | .matrix_key_rows = 5, | ||
647 | .matrix_key_cols = 6, | ||
648 | .matrix_key_map = e2_key_map, | ||
649 | .matrix_key_map_size = ARRAY_SIZE(e2_key_map), | ||
650 | |||
651 | .debounce_interval = 30, | ||
652 | }; | ||
653 | #endif /* CONFIG_MACH_EZX_E2 */ | ||
654 | |||
655 | #ifdef CONFIG_MACH_EZX_A780 | ||
656 | static void __init a780_init(void) | ||
118 | { | 657 | { |
119 | pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); | 658 | pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); |
659 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); | ||
660 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config)); | ||
661 | |||
120 | pxa_set_i2c_info(NULL); | 662 | pxa_set_i2c_info(NULL); |
121 | if (machine_is_ezx_a780() || machine_is_ezx_e680()) | ||
122 | set_pxa_fb_info(&ezx_fb_info_1); | ||
123 | else | ||
124 | set_pxa_fb_info(&ezx_fb_info_2); | ||
125 | 663 | ||
126 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 664 | set_pxa_fb_info(&ezx_fb_info_1); |
127 | } | ||
128 | 665 | ||
129 | static void __init ezx_fixup(struct machine_desc *desc, struct tag *tags, | 666 | pxa_set_keypad_info(&a780_keypad_platform_data); |
130 | char **cmdline, struct meminfo *mi) | 667 | |
131 | { | 668 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
132 | /* We have two ram chips. First one with 32MB at 0xA0000000 and a second | ||
133 | * 16MB one at 0xAC000000 | ||
134 | */ | ||
135 | mi->nr_banks = 2; | ||
136 | mi->bank[0].start = 0xa0000000; | ||
137 | mi->bank[0].node = 0; | ||
138 | mi->bank[0].size = (32*1024*1024); | ||
139 | mi->bank[1].start = 0xac000000; | ||
140 | mi->bank[1].node = 1; | ||
141 | mi->bank[1].size = (16*1024*1024); | ||
142 | } | 669 | } |
143 | 670 | ||
144 | #ifdef CONFIG_MACH_EZX_A780 | ||
145 | MACHINE_START(EZX_A780, "Motorola EZX A780") | 671 | MACHINE_START(EZX_A780, "Motorola EZX A780") |
146 | .phys_io = 0x40000000, | 672 | .phys_io = 0x40000000, |
147 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 673 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
148 | .fixup = ezx_fixup, | ||
149 | .boot_params = 0xa0000100, | 674 | .boot_params = 0xa0000100, |
150 | .map_io = pxa_map_io, | 675 | .map_io = pxa_map_io, |
151 | .init_irq = pxa27x_init_irq, | 676 | .init_irq = pxa27x_init_irq, |
152 | .timer = &pxa_timer, | 677 | .timer = &pxa_timer, |
153 | .init_machine = &ezx_init, | 678 | .init_machine = a780_init, |
154 | MACHINE_END | 679 | MACHINE_END |
155 | #endif | 680 | #endif |
156 | 681 | ||
157 | #ifdef CONFIG_MACH_EZX_E680 | 682 | #ifdef CONFIG_MACH_EZX_E680 |
683 | static struct i2c_board_info __initdata e680_i2c_board_info[] = { | ||
684 | { I2C_BOARD_INFO("tea5767", 0x81) }, | ||
685 | }; | ||
686 | |||
687 | static void __init e680_init(void) | ||
688 | { | ||
689 | pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); | ||
690 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); | ||
691 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config)); | ||
692 | |||
693 | pxa_set_i2c_info(NULL); | ||
694 | i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); | ||
695 | |||
696 | set_pxa_fb_info(&ezx_fb_info_1); | ||
697 | |||
698 | pxa_set_keypad_info(&e680_keypad_platform_data); | ||
699 | |||
700 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
701 | } | ||
702 | |||
158 | MACHINE_START(EZX_E680, "Motorola EZX E680") | 703 | MACHINE_START(EZX_E680, "Motorola EZX E680") |
159 | .phys_io = 0x40000000, | 704 | .phys_io = 0x40000000, |
160 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 705 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
161 | .fixup = ezx_fixup, | ||
162 | .boot_params = 0xa0000100, | 706 | .boot_params = 0xa0000100, |
163 | .map_io = pxa_map_io, | 707 | .map_io = pxa_map_io, |
164 | .init_irq = pxa27x_init_irq, | 708 | .init_irq = pxa27x_init_irq, |
165 | .timer = &pxa_timer, | 709 | .timer = &pxa_timer, |
166 | .init_machine = &ezx_init, | 710 | .init_machine = e680_init, |
167 | MACHINE_END | 711 | MACHINE_END |
168 | #endif | 712 | #endif |
169 | 713 | ||
170 | #ifdef CONFIG_MACH_EZX_A1200 | 714 | #ifdef CONFIG_MACH_EZX_A1200 |
715 | static struct i2c_board_info __initdata a1200_i2c_board_info[] = { | ||
716 | { I2C_BOARD_INFO("tea5767", 0x81) }, | ||
717 | }; | ||
718 | |||
719 | static void __init a1200_init(void) | ||
720 | { | ||
721 | pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); | ||
722 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | ||
723 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config)); | ||
724 | |||
725 | pxa_set_i2c_info(NULL); | ||
726 | i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); | ||
727 | |||
728 | set_pxa_fb_info(&ezx_fb_info_2); | ||
729 | |||
730 | pxa_set_keypad_info(&a1200_keypad_platform_data); | ||
731 | |||
732 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
733 | } | ||
734 | |||
171 | MACHINE_START(EZX_A1200, "Motorola EZX A1200") | 735 | MACHINE_START(EZX_A1200, "Motorola EZX A1200") |
172 | .phys_io = 0x40000000, | 736 | .phys_io = 0x40000000, |
173 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 737 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
174 | .fixup = ezx_fixup, | ||
175 | .boot_params = 0xa0000100, | 738 | .boot_params = 0xa0000100, |
176 | .map_io = pxa_map_io, | 739 | .map_io = pxa_map_io, |
177 | .init_irq = pxa27x_init_irq, | 740 | .init_irq = pxa27x_init_irq, |
178 | .timer = &pxa_timer, | 741 | .timer = &pxa_timer, |
179 | .init_machine = &ezx_init, | 742 | .init_machine = a1200_init, |
180 | MACHINE_END | 743 | MACHINE_END |
181 | #endif | 744 | #endif |
182 | 745 | ||
183 | #ifdef CONFIG_MACH_EZX_A910 | 746 | #ifdef CONFIG_MACH_EZX_A910 |
747 | static void __init a910_init(void) | ||
748 | { | ||
749 | pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); | ||
750 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | ||
751 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config)); | ||
752 | |||
753 | pxa_set_i2c_info(NULL); | ||
754 | |||
755 | set_pxa_fb_info(&ezx_fb_info_2); | ||
756 | |||
757 | pxa_set_keypad_info(&a910_keypad_platform_data); | ||
758 | |||
759 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
760 | } | ||
761 | |||
184 | MACHINE_START(EZX_A910, "Motorola EZX A910") | 762 | MACHINE_START(EZX_A910, "Motorola EZX A910") |
185 | .phys_io = 0x40000000, | 763 | .phys_io = 0x40000000, |
186 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 764 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
187 | .fixup = ezx_fixup, | ||
188 | .boot_params = 0xa0000100, | 765 | .boot_params = 0xa0000100, |
189 | .map_io = pxa_map_io, | 766 | .map_io = pxa_map_io, |
190 | .init_irq = pxa27x_init_irq, | 767 | .init_irq = pxa27x_init_irq, |
191 | .timer = &pxa_timer, | 768 | .timer = &pxa_timer, |
192 | .init_machine = &ezx_init, | 769 | .init_machine = a910_init, |
193 | MACHINE_END | 770 | MACHINE_END |
194 | #endif | 771 | #endif |
195 | 772 | ||
196 | #ifdef CONFIG_MACH_EZX_E6 | 773 | #ifdef CONFIG_MACH_EZX_E6 |
774 | static struct i2c_board_info __initdata e6_i2c_board_info[] = { | ||
775 | { I2C_BOARD_INFO("tea5767", 0x81) }, | ||
776 | }; | ||
777 | |||
778 | static void __init e6_init(void) | ||
779 | { | ||
780 | pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); | ||
781 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | ||
782 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config)); | ||
783 | |||
784 | pxa_set_i2c_info(NULL); | ||
785 | i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); | ||
786 | |||
787 | set_pxa_fb_info(&ezx_fb_info_2); | ||
788 | |||
789 | pxa_set_keypad_info(&e6_keypad_platform_data); | ||
790 | |||
791 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
792 | } | ||
793 | |||
197 | MACHINE_START(EZX_E6, "Motorola EZX E6") | 794 | MACHINE_START(EZX_E6, "Motorola EZX E6") |
198 | .phys_io = 0x40000000, | 795 | .phys_io = 0x40000000, |
199 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 796 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
200 | .fixup = ezx_fixup, | ||
201 | .boot_params = 0xa0000100, | 797 | .boot_params = 0xa0000100, |
202 | .map_io = pxa_map_io, | 798 | .map_io = pxa_map_io, |
203 | .init_irq = pxa27x_init_irq, | 799 | .init_irq = pxa27x_init_irq, |
204 | .timer = &pxa_timer, | 800 | .timer = &pxa_timer, |
205 | .init_machine = &ezx_init, | 801 | .init_machine = e6_init, |
206 | MACHINE_END | 802 | MACHINE_END |
207 | #endif | 803 | #endif |
208 | 804 | ||
209 | #ifdef CONFIG_MACH_EZX_E2 | 805 | #ifdef CONFIG_MACH_EZX_E2 |
806 | static struct i2c_board_info __initdata e2_i2c_board_info[] = { | ||
807 | { I2C_BOARD_INFO("tea5767", 0x81) }, | ||
808 | }; | ||
809 | |||
810 | static void __init e2_init(void) | ||
811 | { | ||
812 | pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); | ||
813 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | ||
814 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config)); | ||
815 | |||
816 | pxa_set_i2c_info(NULL); | ||
817 | i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); | ||
818 | |||
819 | set_pxa_fb_info(&ezx_fb_info_2); | ||
820 | |||
821 | pxa_set_keypad_info(&e2_keypad_platform_data); | ||
822 | |||
823 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
824 | } | ||
825 | |||
210 | MACHINE_START(EZX_E2, "Motorola EZX E2") | 826 | MACHINE_START(EZX_E2, "Motorola EZX E2") |
211 | .phys_io = 0x40000000, | 827 | .phys_io = 0x40000000, |
212 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 828 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
213 | .fixup = ezx_fixup, | ||
214 | .boot_params = 0xa0000100, | 829 | .boot_params = 0xa0000100, |
215 | .map_io = pxa_map_io, | 830 | .map_io = pxa_map_io, |
216 | .init_irq = pxa27x_init_irq, | 831 | .init_irq = pxa27x_init_irq, |
217 | .timer = &pxa_timer, | 832 | .timer = &pxa_timer, |
218 | .init_machine = &ezx_init, | 833 | .init_machine = e2_init, |
219 | MACHINE_END | 834 | MACHINE_END |
220 | #endif | 835 | #endif |
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 85ed0b33331f..0ccc91c92c44 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <asm/system.h> | 24 | #include <asm/system.h> |
25 | #include <asm/pgtable.h> | 25 | #include <asm/pgtable.h> |
26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | #include <asm/mach-types.h> | ||
27 | 28 | ||
28 | #include <mach/pxa-regs.h> | 29 | #include <mach/pxa-regs.h> |
29 | #include <mach/reset.h> | 30 | #include <mach/reset.h> |
@@ -39,6 +40,21 @@ void clear_reset_status(unsigned int mask) | |||
39 | pxa3xx_clear_reset_status(mask); | 40 | pxa3xx_clear_reset_status(mask); |
40 | } | 41 | } |
41 | 42 | ||
43 | unsigned long get_clock_tick_rate(void) | ||
44 | { | ||
45 | unsigned long clock_tick_rate; | ||
46 | |||
47 | if (cpu_is_pxa25x()) | ||
48 | clock_tick_rate = 3686400; | ||
49 | else if (machine_is_mainstone()) | ||
50 | clock_tick_rate = 3249600; | ||
51 | else | ||
52 | clock_tick_rate = 3250000; | ||
53 | |||
54 | return clock_tick_rate; | ||
55 | } | ||
56 | EXPORT_SYMBOL(get_clock_tick_rate); | ||
57 | |||
42 | /* | 58 | /* |
43 | * Get the clock frequency as reflected by CCCR and the turbo flag. | 59 | * Get the clock frequency as reflected by CCCR and the turbo flag. |
44 | * We assume these values have been applied via a fcs. | 60 | * We assume these values have been applied via a fcs. |
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 14930cf8be7b..5fec1e479cb3 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c | |||
@@ -25,6 +25,18 @@ | |||
25 | 25 | ||
26 | #include "generic.h" | 26 | #include "generic.h" |
27 | 27 | ||
28 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) | ||
29 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | ||
30 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | ||
31 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | ||
32 | |||
33 | #define GPLR_OFFSET 0x00 | ||
34 | #define GPDR_OFFSET 0x0C | ||
35 | #define GPSR_OFFSET 0x18 | ||
36 | #define GPCR_OFFSET 0x24 | ||
37 | #define GRER_OFFSET 0x30 | ||
38 | #define GFER_OFFSET 0x3C | ||
39 | #define GEDR_OFFSET 0x48 | ||
28 | 40 | ||
29 | struct pxa_gpio_chip { | 41 | struct pxa_gpio_chip { |
30 | struct gpio_chip chip; | 42 | struct gpio_chip chip; |
@@ -33,6 +45,18 @@ struct pxa_gpio_chip { | |||
33 | 45 | ||
34 | int pxa_last_gpio; | 46 | int pxa_last_gpio; |
35 | 47 | ||
48 | #ifdef CONFIG_CPU_PXA26x | ||
49 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, | ||
50 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | ||
51 | */ | ||
52 | static int __gpio_is_inverted(unsigned gpio) | ||
53 | { | ||
54 | return cpu_is_pxa25x() && gpio > 85; | ||
55 | } | ||
56 | #else | ||
57 | #define __gpio_is_inverted(gpio) (0) | ||
58 | #endif | ||
59 | |||
36 | /* | 60 | /* |
37 | * Configure pins for GPIO or other functions | 61 | * Configure pins for GPIO or other functions |
38 | */ | 62 | */ |
@@ -75,7 +99,10 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |||
75 | gpdr = pxa->regbase + GPDR_OFFSET; | 99 | gpdr = pxa->regbase + GPDR_OFFSET; |
76 | local_irq_save(flags); | 100 | local_irq_save(flags); |
77 | value = __raw_readl(gpdr); | 101 | value = __raw_readl(gpdr); |
78 | value &= ~mask; | 102 | if (__gpio_is_inverted(chip->base + offset)) |
103 | value |= mask; | ||
104 | else | ||
105 | value &= ~mask; | ||
79 | __raw_writel(value, gpdr); | 106 | __raw_writel(value, gpdr); |
80 | local_irq_restore(flags); | 107 | local_irq_restore(flags); |
81 | 108 | ||
@@ -97,7 +124,10 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip, | |||
97 | gpdr = pxa->regbase + GPDR_OFFSET; | 124 | gpdr = pxa->regbase + GPDR_OFFSET; |
98 | local_irq_save(flags); | 125 | local_irq_save(flags); |
99 | tmp = __raw_readl(gpdr); | 126 | tmp = __raw_readl(gpdr); |
100 | tmp |= mask; | 127 | if (__gpio_is_inverted(chip->base + offset)) |
128 | tmp &= ~mask; | ||
129 | else | ||
130 | tmp |= mask; | ||
101 | __raw_writel(tmp, gpdr); | 131 | __raw_writel(tmp, gpdr); |
102 | local_irq_restore(flags); | 132 | local_irq_restore(flags); |
103 | 133 | ||
@@ -173,10 +203,17 @@ static unsigned long GPIO_IRQ_mask[4]; | |||
173 | */ | 203 | */ |
174 | static int __gpio_is_occupied(unsigned gpio) | 204 | static int __gpio_is_occupied(unsigned gpio) |
175 | { | 205 | { |
176 | if (cpu_is_pxa25x() || cpu_is_pxa27x()) | 206 | if (cpu_is_pxa27x() || cpu_is_pxa25x()) { |
177 | return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2)); | 207 | int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; |
178 | else | 208 | int dir = GPDR(gpio) & GPIO_bit(gpio); |
179 | return 0; | 209 | |
210 | if (__gpio_is_inverted(gpio)) | ||
211 | return af != 1 || dir == 0; | ||
212 | else | ||
213 | return af != 0 || dir != 0; | ||
214 | } | ||
215 | |||
216 | return 0; | ||
180 | } | 217 | } |
181 | 218 | ||
182 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | 219 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) |
@@ -190,9 +227,8 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | |||
190 | /* Don't mess with enabled GPIOs using preconfigured edges or | 227 | /* Don't mess with enabled GPIOs using preconfigured edges or |
191 | * GPIOs set to alternate function or to output during probe | 228 | * GPIOs set to alternate function or to output during probe |
192 | */ | 229 | */ |
193 | if ((GPIO_IRQ_rising_edge[idx] | | 230 | if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) || |
194 | GPIO_IRQ_falling_edge[idx] | | 231 | (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio))) |
195 | GPDR(gpio)) & GPIO_bit(gpio)) | ||
196 | return 0; | 232 | return 0; |
197 | 233 | ||
198 | if (__gpio_is_occupied(gpio)) | 234 | if (__gpio_is_occupied(gpio)) |
@@ -201,7 +237,10 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | |||
201 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | 237 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
202 | } | 238 | } |
203 | 239 | ||
204 | GPDR(gpio) &= ~GPIO_bit(gpio); | 240 | if (__gpio_is_inverted(gpio)) |
241 | GPDR(gpio) |= GPIO_bit(gpio); | ||
242 | else | ||
243 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
205 | 244 | ||
206 | if (type & IRQ_TYPE_EDGE_RISING) | 245 | if (type & IRQ_TYPE_EDGE_RISING) |
207 | __set_bit(gpio, GPIO_IRQ_rising_edge); | 246 | __set_bit(gpio, GPIO_IRQ_rising_edge); |
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index d8962a0fb98d..e296ce11658c 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c | |||
@@ -184,15 +184,22 @@ static unsigned long gumstix_pin_config[] __initdata = { | |||
184 | GPIO6_MMC_CLK, | 184 | GPIO6_MMC_CLK, |
185 | GPIO53_MMC_CLK, | 185 | GPIO53_MMC_CLK, |
186 | GPIO8_MMC_CS0, | 186 | GPIO8_MMC_CS0, |
187 | /* these are used by AM200EPD */ | ||
188 | GPIO51_GPIO, | ||
189 | GPIO49_GPIO, | ||
190 | GPIO48_GPIO, | ||
191 | GPIO32_GPIO, | ||
192 | GPIO17_GPIO, | ||
193 | GPIO16_GPIO, | ||
194 | }; | 187 | }; |
195 | 188 | ||
189 | int __attribute__((weak)) am200_init(void) | ||
190 | { | ||
191 | return 0; | ||
192 | } | ||
193 | |||
194 | static void __init carrier_board_init(void) | ||
195 | { | ||
196 | /* | ||
197 | * put carrier/expansion board init here if | ||
198 | * they cannot be detected programatically | ||
199 | */ | ||
200 | am200_init(); | ||
201 | } | ||
202 | |||
196 | static void __init gumstix_init(void) | 203 | static void __init gumstix_init(void) |
197 | { | 204 | { |
198 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config)); | 205 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config)); |
@@ -201,6 +208,7 @@ static void __init gumstix_init(void) | |||
201 | gumstix_udc_init(); | 208 | gumstix_udc_init(); |
202 | gumstix_mmc_init(); | 209 | gumstix_mmc_init(); |
203 | (void) platform_add_devices(devices, ARRAY_SIZE(devices)); | 210 | (void) platform_add_devices(devices, ARRAY_SIZE(devices)); |
211 | carrier_board_init(); | ||
204 | } | 212 | } |
205 | 213 | ||
206 | MACHINE_START(GUMSTIX, "Gumstix") | 214 | MACHINE_START(GUMSTIX, "Gumstix") |
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c new file mode 100644 index 000000000000..da6e4422c0f3 --- /dev/null +++ b/arch/arm/mach-pxa/h5000.c | |||
@@ -0,0 +1,200 @@ | |||
1 | /* | ||
2 | * Hardware definitions for HP iPAQ h5xxx Handheld Computers | ||
3 | * | ||
4 | * Copyright 2000-2003 Hewlett-Packard Company. | ||
5 | * Copyright 2002 Jamey Hicks <jamey.hicks@hp.com> | ||
6 | * Copyright 2004-2005 Phil Blundell <pb@handhelds.org> | ||
7 | * Copyright 2007-2008 Anton Vorontsov <cbouatmailru@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | ||
15 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | ||
16 | * FITNESS FOR ANY PARTICULAR PURPOSE. | ||
17 | * | ||
18 | * Author: Jamey Hicks. | ||
19 | */ | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/init.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | #include <linux/mtd/mtd.h> | ||
25 | #include <linux/mtd/partitions.h> | ||
26 | #include <linux/mtd/physmap.h> | ||
27 | #include <asm/mach-types.h> | ||
28 | #include <asm/mach/arch.h> | ||
29 | #include <asm/mach/map.h> | ||
30 | #include <mach/h5000.h> | ||
31 | #include <mach/pxa-regs.h> | ||
32 | #include <mach/pxa2xx-regs.h> | ||
33 | #include <mach/mfp-pxa25x.h> | ||
34 | #include <mach/udc.h> | ||
35 | #include "generic.h" | ||
36 | |||
37 | /* | ||
38 | * Flash | ||
39 | */ | ||
40 | |||
41 | static struct mtd_partition h5000_flash0_partitions[] = { | ||
42 | { | ||
43 | .name = "bootldr", | ||
44 | .size = 0x00040000, | ||
45 | .offset = 0, | ||
46 | .mask_flags = MTD_WRITEABLE, | ||
47 | }, | ||
48 | { | ||
49 | .name = "root", | ||
50 | .size = MTDPART_SIZ_FULL, | ||
51 | .offset = MTDPART_OFS_APPEND, | ||
52 | }, | ||
53 | }; | ||
54 | |||
55 | static struct mtd_partition h5000_flash1_partitions[] = { | ||
56 | { | ||
57 | .name = "second root", | ||
58 | .size = SZ_16M - 0x00040000, | ||
59 | .offset = 0, | ||
60 | }, | ||
61 | { | ||
62 | .name = "asset", | ||
63 | .size = MTDPART_SIZ_FULL, | ||
64 | .offset = MTDPART_OFS_APPEND, | ||
65 | .mask_flags = MTD_WRITEABLE, | ||
66 | }, | ||
67 | }; | ||
68 | |||
69 | static struct physmap_flash_data h5000_flash0_data = { | ||
70 | .width = 4, | ||
71 | .parts = h5000_flash0_partitions, | ||
72 | .nr_parts = ARRAY_SIZE(h5000_flash0_partitions), | ||
73 | }; | ||
74 | |||
75 | static struct physmap_flash_data h5000_flash1_data = { | ||
76 | .width = 4, | ||
77 | .parts = h5000_flash1_partitions, | ||
78 | .nr_parts = ARRAY_SIZE(h5000_flash1_partitions), | ||
79 | }; | ||
80 | |||
81 | static struct resource h5000_flash0_resources = { | ||
82 | .start = PXA_CS0_PHYS, | ||
83 | .end = PXA_CS0_PHYS + SZ_32M - 1, | ||
84 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, | ||
85 | }; | ||
86 | |||
87 | static struct resource h5000_flash1_resources = { | ||
88 | .start = PXA_CS0_PHYS + SZ_32M, | ||
89 | .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1, | ||
90 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, | ||
91 | }; | ||
92 | |||
93 | static struct platform_device h5000_flash[] = { | ||
94 | { | ||
95 | .name = "physmap-flash", | ||
96 | .id = 0, | ||
97 | .resource = &h5000_flash0_resources, | ||
98 | .num_resources = 1, | ||
99 | .dev = { | ||
100 | .platform_data = &h5000_flash0_data, | ||
101 | }, | ||
102 | }, | ||
103 | { | ||
104 | .name = "physmap-flash", | ||
105 | .id = 1, | ||
106 | .resource = &h5000_flash1_resources, | ||
107 | .num_resources = 1, | ||
108 | .dev = { | ||
109 | .platform_data = &h5000_flash1_data, | ||
110 | }, | ||
111 | }, | ||
112 | }; | ||
113 | |||
114 | /* | ||
115 | * USB Device Controller | ||
116 | */ | ||
117 | |||
118 | static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = { | ||
119 | .gpio_pullup = H5000_GPIO_USB_PULLUP, | ||
120 | }; | ||
121 | |||
122 | /* | ||
123 | * GPIO setup | ||
124 | */ | ||
125 | |||
126 | static unsigned long h5000_pin_config[] __initdata = { | ||
127 | /* Crystal and Clock Signals */ | ||
128 | GPIO12_32KHz, | ||
129 | |||
130 | /* SDRAM and Static Memory I/O Signals */ | ||
131 | GPIO15_nCS_1, | ||
132 | GPIO78_nCS_2, | ||
133 | GPIO79_nCS_3, | ||
134 | GPIO80_nCS_4, | ||
135 | |||
136 | /* FFUART */ | ||
137 | GPIO34_FFUART_RXD, | ||
138 | GPIO35_FFUART_CTS, | ||
139 | GPIO36_FFUART_DCD, | ||
140 | GPIO37_FFUART_DSR, | ||
141 | GPIO38_FFUART_RI, | ||
142 | GPIO39_FFUART_TXD, | ||
143 | GPIO40_FFUART_DTR, | ||
144 | GPIO41_FFUART_RTS, | ||
145 | |||
146 | /* BTUART */ | ||
147 | GPIO42_BTUART_RXD, | ||
148 | GPIO43_BTUART_TXD, | ||
149 | GPIO44_BTUART_CTS, | ||
150 | GPIO45_BTUART_RTS, | ||
151 | |||
152 | /* SSP1 */ | ||
153 | GPIO23_SSP1_SCLK, | ||
154 | GPIO25_SSP1_TXD, | ||
155 | GPIO26_SSP1_RXD, | ||
156 | }; | ||
157 | |||
158 | /* | ||
159 | * Localbus setup: | ||
160 | * CS0: Flash; | ||
161 | * CS1: MediaQ chip, select 16-bit bus and vlio; | ||
162 | * CS5: SAMCOP. | ||
163 | */ | ||
164 | |||
165 | static void fix_msc(void) | ||
166 | { | ||
167 | MSC0 = 0x129c24f2; | ||
168 | MSC1 = 0x7ff424fa; | ||
169 | MSC2 = 0x7ff47ff4; | ||
170 | |||
171 | MDREFR |= 0x02080000; | ||
172 | } | ||
173 | |||
174 | /* | ||
175 | * Platform devices | ||
176 | */ | ||
177 | |||
178 | static struct platform_device *devices[] __initdata = { | ||
179 | &h5000_flash[0], | ||
180 | &h5000_flash[1], | ||
181 | }; | ||
182 | |||
183 | static void __init h5000_init(void) | ||
184 | { | ||
185 | fix_msc(); | ||
186 | |||
187 | pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config)); | ||
188 | pxa_set_udc_info(&h5000_udc_mach_info); | ||
189 | platform_add_devices(ARRAY_AND_SIZE(devices)); | ||
190 | } | ||
191 | |||
192 | MACHINE_START(H5400, "HP iPAQ H5000") | ||
193 | .phys_io = 0x40000000, | ||
194 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
195 | .boot_params = 0xa0000100, | ||
196 | .map_io = pxa_map_io, | ||
197 | .init_irq = pxa25x_init_irq, | ||
198 | .timer = &pxa_timer, | ||
199 | .init_machine = h5000_init, | ||
200 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c new file mode 100644 index 000000000000..364c5e271330 --- /dev/null +++ b/arch/arm/mach-pxa/imote2.c | |||
@@ -0,0 +1,575 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/imote2.c | ||
3 | * | ||
4 | * Author: Ed C. Epp | ||
5 | * Created: Nov 05, 2002 | ||
6 | * Copyright: Intel Corp. | ||
7 | * | ||
8 | * Modified 2008: Jonathan Cameron | ||
9 | * | ||
10 | * The Imote2 is a wireless sensor node platform sold | ||
11 | * by Crossbow (www.xbow.com). | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/device.h> | ||
16 | #include <linux/mtd/mtd.h> | ||
17 | #include <linux/mtd/partitions.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | #include <linux/regulator/machine.h> | ||
20 | #include <linux/gpio.h> | ||
21 | #include <linux/leds.h> | ||
22 | #include <linux/spi/spi.h> | ||
23 | #include <linux/i2c.h> | ||
24 | #include <linux/mfd/da903x.h> | ||
25 | |||
26 | #include <asm/mach-types.h> | ||
27 | #include <asm/mach/arch.h> | ||
28 | #include <asm/mach/map.h> | ||
29 | #include <asm/mach/flash.h> | ||
30 | |||
31 | #include <mach/i2c.h> | ||
32 | #include <mach/pxa-regs.h> | ||
33 | #include <mach/pxa2xx-regs.h> | ||
34 | #include <mach/mfp-pxa27x.h> | ||
35 | #include <mach/regs-ssp.h> | ||
36 | #include <mach/udc.h> | ||
37 | #include <mach/mmc.h> | ||
38 | #include <mach/pxa2xx_spi.h> | ||
39 | #include <mach/pxa27x-udc.h> | ||
40 | |||
41 | #include "devices.h" | ||
42 | #include "generic.h" | ||
43 | |||
44 | static unsigned long imote2_pin_config[] __initdata = { | ||
45 | |||
46 | /* Device Identification for wakeup*/ | ||
47 | GPIO102_GPIO, | ||
48 | |||
49 | /* Button */ | ||
50 | GPIO91_GPIO, | ||
51 | |||
52 | /* DA9030 */ | ||
53 | GPIO1_GPIO, | ||
54 | |||
55 | /* MMC */ | ||
56 | GPIO32_MMC_CLK, | ||
57 | GPIO112_MMC_CMD, | ||
58 | GPIO92_MMC_DAT_0, | ||
59 | GPIO109_MMC_DAT_1, | ||
60 | GPIO110_MMC_DAT_2, | ||
61 | GPIO111_MMC_DAT_3, | ||
62 | |||
63 | /* 802.15.4 radio - driver out of mainline */ | ||
64 | GPIO22_GPIO, /* CC_RSTN */ | ||
65 | GPIO114_GPIO, /* CC_FIFO */ | ||
66 | GPIO116_GPIO, /* CC_CCA */ | ||
67 | GPIO0_GPIO, /* CC_FIFOP */ | ||
68 | GPIO16_GPIO, /* CCSFD */ | ||
69 | GPIO39_GPIO, /* CSn */ | ||
70 | GPIO115_GPIO, /* Power enable */ | ||
71 | |||
72 | /* I2C */ | ||
73 | GPIO117_I2C_SCL, | ||
74 | GPIO118_I2C_SDA, | ||
75 | |||
76 | /* SSP 3 - 802.15.4 radio */ | ||
77 | GPIO39_GPIO, /* Chip Select */ | ||
78 | GPIO34_SSP3_SCLK, | ||
79 | GPIO35_SSP3_TXD, | ||
80 | GPIO41_SSP3_RXD, | ||
81 | |||
82 | /* SSP 2 - to daughter boards */ | ||
83 | GPIO37_GPIO, /* Chip Select */ | ||
84 | GPIO36_SSP2_SCLK, | ||
85 | GPIO38_SSP2_TXD, | ||
86 | GPIO11_SSP2_RXD, | ||
87 | |||
88 | /* SSP 1 - to daughter boards */ | ||
89 | GPIO24_GPIO, /* Chip Select */ | ||
90 | GPIO23_SSP1_SCLK, | ||
91 | GPIO25_SSP1_TXD, | ||
92 | GPIO26_SSP1_RXD, | ||
93 | |||
94 | /* BTUART Basic Connector*/ | ||
95 | GPIO42_BTUART_RXD, | ||
96 | GPIO43_BTUART_TXD, | ||
97 | GPIO44_BTUART_CTS, | ||
98 | GPIO45_BTUART_RTS, | ||
99 | |||
100 | /* STUART Serial console via debug board*/ | ||
101 | GPIO46_STUART_RXD, | ||
102 | GPIO47_STUART_TXD, | ||
103 | |||
104 | /* Basic sensor board */ | ||
105 | GPIO96_GPIO, /* accelerometer interrupt */ | ||
106 | GPIO99_GPIO, /* ADC interrupt */ | ||
107 | |||
108 | /* Connector pins specified as gpios */ | ||
109 | GPIO94_GPIO, /* large basic connector pin 14 */ | ||
110 | GPIO10_GPIO, /* large basic connector pin 23 */ | ||
111 | |||
112 | /* LEDS */ | ||
113 | GPIO103_GPIO, /* red led */ | ||
114 | GPIO104_GPIO, /* green led */ | ||
115 | GPIO105_GPIO, /* blue led */ | ||
116 | }; | ||
117 | |||
118 | static struct gpio_led imote2_led_pins[] = { | ||
119 | { | ||
120 | .name = "imote2:red", | ||
121 | .gpio = 103, | ||
122 | .active_low = 1, | ||
123 | }, { | ||
124 | .name = "imote2:green", | ||
125 | .gpio = 104, | ||
126 | .active_low = 1, | ||
127 | }, { | ||
128 | .name = "imote2:blue", | ||
129 | .gpio = 105, | ||
130 | .active_low = 1, | ||
131 | }, | ||
132 | }; | ||
133 | |||
134 | static struct gpio_led_platform_data imote2_led_data = { | ||
135 | .num_leds = ARRAY_SIZE(imote2_led_pins), | ||
136 | .leds = imote2_led_pins, | ||
137 | }; | ||
138 | |||
139 | static struct platform_device imote2_leds = { | ||
140 | .name = "leds-gpio", | ||
141 | .id = -1, | ||
142 | .dev = { | ||
143 | .platform_data = &imote2_led_data, | ||
144 | }, | ||
145 | }; | ||
146 | |||
147 | /* Reverse engineered partly from Platformx drivers */ | ||
148 | enum imote2_ldos{ | ||
149 | vcc_vref, | ||
150 | vcc_cc2420, | ||
151 | vcc_mica, | ||
152 | vcc_bt, | ||
153 | /* The two voltages available to sensor boards */ | ||
154 | vcc_sensor_1_8, | ||
155 | vcc_sensor_3, | ||
156 | |||
157 | vcc_sram_ext, /* directly connected to the pxa271 */ | ||
158 | vcc_pxa_pll, | ||
159 | vcc_pxa_usim, /* Reference voltage for certain gpios */ | ||
160 | vcc_pxa_mem, | ||
161 | vcc_pxa_flash, | ||
162 | vcc_pxa_core, /*Dc-Dc buck not yet supported */ | ||
163 | vcc_lcd, | ||
164 | vcc_bb, | ||
165 | vcc_bbio, | ||
166 | vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/ | ||
167 | }; | ||
168 | |||
169 | /* The values of the various regulator constraints are obviously dependent | ||
170 | * on exactly what is wired to each ldo. Unfortunately this information is | ||
171 | * not generally available. More information has been requested from Xbow | ||
172 | * but as of yet they haven't been forthcoming. | ||
173 | * | ||
174 | * Some of these are clearly Stargate 2 related (no way of plugging | ||
175 | * in an lcd on the IM2 for example!). | ||
176 | */ | ||
177 | static struct regulator_init_data imote2_ldo_init_data[] = { | ||
178 | [vcc_bbio] = { | ||
179 | .constraints = { /* board default 1.8V */ | ||
180 | .name = "vcc_bbio", | ||
181 | .min_uV = 1800000, | ||
182 | .max_uV = 1800000, | ||
183 | }, | ||
184 | }, | ||
185 | [vcc_bb] = { | ||
186 | .constraints = { /* board default 2.8V */ | ||
187 | .name = "vcc_bb", | ||
188 | .min_uV = 2700000, | ||
189 | .max_uV = 3000000, | ||
190 | }, | ||
191 | }, | ||
192 | [vcc_pxa_flash] = { | ||
193 | .constraints = {/* default is 1.8V */ | ||
194 | .name = "vcc_pxa_flash", | ||
195 | .min_uV = 1800000, | ||
196 | .max_uV = 1800000, | ||
197 | }, | ||
198 | }, | ||
199 | [vcc_cc2420] = { /* also vcc_io */ | ||
200 | .constraints = { | ||
201 | /* board default is 2.8V */ | ||
202 | .name = "vcc_cc2420", | ||
203 | .min_uV = 2700000, | ||
204 | .max_uV = 3300000, | ||
205 | }, | ||
206 | }, | ||
207 | [vcc_vref] = { /* Reference for what? */ | ||
208 | .constraints = { /* default 1.8V */ | ||
209 | .name = "vcc_vref", | ||
210 | .min_uV = 1800000, | ||
211 | .max_uV = 1800000, | ||
212 | }, | ||
213 | }, | ||
214 | [vcc_sram_ext] = { | ||
215 | .constraints = { /* default 2.8V */ | ||
216 | .name = "vcc_sram_ext", | ||
217 | .min_uV = 2800000, | ||
218 | .max_uV = 2800000, | ||
219 | }, | ||
220 | }, | ||
221 | [vcc_mica] = { | ||
222 | .constraints = { /* default 2.8V */ | ||
223 | .name = "vcc_mica", | ||
224 | .min_uV = 2800000, | ||
225 | .max_uV = 2800000, | ||
226 | }, | ||
227 | }, | ||
228 | [vcc_bt] = { | ||
229 | .constraints = { /* default 2.8V */ | ||
230 | .name = "vcc_bt", | ||
231 | .min_uV = 2800000, | ||
232 | .max_uV = 2800000, | ||
233 | }, | ||
234 | }, | ||
235 | [vcc_lcd] = { | ||
236 | .constraints = { /* default 2.8V */ | ||
237 | .name = "vcc_lcd", | ||
238 | .min_uV = 2700000, | ||
239 | .max_uV = 3300000, | ||
240 | }, | ||
241 | }, | ||
242 | [vcc_io] = { /* Same or higher than everything | ||
243 | * bar vccbat and vccusb */ | ||
244 | .constraints = { /* default 2.8V */ | ||
245 | .name = "vcc_io", | ||
246 | .min_uV = 2692000, | ||
247 | .max_uV = 3300000, | ||
248 | }, | ||
249 | }, | ||
250 | [vcc_sensor_1_8] = { | ||
251 | .constraints = { /* default 1.8V */ | ||
252 | .name = "vcc_sensor_1_8", | ||
253 | .min_uV = 1800000, | ||
254 | .max_uV = 1800000, | ||
255 | }, | ||
256 | }, | ||
257 | [vcc_sensor_3] = { /* curiously default 2.8V */ | ||
258 | .constraints = { | ||
259 | .name = "vcc_sensor_3", | ||
260 | .min_uV = 2800000, | ||
261 | .max_uV = 3000000, | ||
262 | }, | ||
263 | }, | ||
264 | [vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/ | ||
265 | .constraints = { | ||
266 | .name = "vcc_pxa_pll", | ||
267 | .min_uV = 1170000, | ||
268 | .max_uV = 1430000, | ||
269 | }, | ||
270 | }, | ||
271 | [vcc_pxa_usim] = { | ||
272 | .constraints = { /* default 1.8V */ | ||
273 | .name = "vcc_pxa_usim", | ||
274 | .min_uV = 1710000, | ||
275 | .max_uV = 2160000, | ||
276 | }, | ||
277 | }, | ||
278 | [vcc_pxa_mem] = { | ||
279 | .constraints = { /* default 1.8V */ | ||
280 | .name = "vcc_pxa_mem", | ||
281 | .min_uV = 1800000, | ||
282 | .max_uV = 1800000, | ||
283 | }, | ||
284 | }, | ||
285 | }; | ||
286 | |||
287 | static struct da903x_subdev_info imote2_da9030_subdevs[] = { | ||
288 | { | ||
289 | .name = "da903x-regulator", | ||
290 | .id = DA9030_ID_LDO2, | ||
291 | .platform_data = &imote2_ldo_init_data[vcc_bbio], | ||
292 | }, { | ||
293 | .name = "da903x-regulator", | ||
294 | .id = DA9030_ID_LDO3, | ||
295 | .platform_data = &imote2_ldo_init_data[vcc_bb], | ||
296 | }, { | ||
297 | .name = "da903x-regulator", | ||
298 | .id = DA9030_ID_LDO4, | ||
299 | .platform_data = &imote2_ldo_init_data[vcc_pxa_flash], | ||
300 | }, { | ||
301 | .name = "da903x-regulator", | ||
302 | .id = DA9030_ID_LDO5, | ||
303 | .platform_data = &imote2_ldo_init_data[vcc_cc2420], | ||
304 | }, { | ||
305 | .name = "da903x-regulator", | ||
306 | .id = DA9030_ID_LDO6, | ||
307 | .platform_data = &imote2_ldo_init_data[vcc_vref], | ||
308 | }, { | ||
309 | .name = "da903x-regulator", | ||
310 | .id = DA9030_ID_LDO7, | ||
311 | .platform_data = &imote2_ldo_init_data[vcc_sram_ext], | ||
312 | }, { | ||
313 | .name = "da903x-regulator", | ||
314 | .id = DA9030_ID_LDO8, | ||
315 | .platform_data = &imote2_ldo_init_data[vcc_mica], | ||
316 | }, { | ||
317 | .name = "da903x-regulator", | ||
318 | .id = DA9030_ID_LDO9, | ||
319 | .platform_data = &imote2_ldo_init_data[vcc_bt], | ||
320 | }, { | ||
321 | .name = "da903x-regulator", | ||
322 | .id = DA9030_ID_LDO10, | ||
323 | .platform_data = &imote2_ldo_init_data[vcc_sensor_1_8], | ||
324 | }, { | ||
325 | .name = "da903x-regulator", | ||
326 | .id = DA9030_ID_LDO11, | ||
327 | .platform_data = &imote2_ldo_init_data[vcc_sensor_3], | ||
328 | }, { | ||
329 | .name = "da903x-regulator", | ||
330 | .id = DA9030_ID_LDO12, | ||
331 | .platform_data = &imote2_ldo_init_data[vcc_lcd], | ||
332 | }, { | ||
333 | .name = "da903x-regulator", | ||
334 | .id = DA9030_ID_LDO15, | ||
335 | .platform_data = &imote2_ldo_init_data[vcc_pxa_pll], | ||
336 | }, { | ||
337 | .name = "da903x-regulator", | ||
338 | .id = DA9030_ID_LDO17, | ||
339 | .platform_data = &imote2_ldo_init_data[vcc_pxa_usim], | ||
340 | }, { | ||
341 | .name = "da903x-regulator", | ||
342 | .id = DA9030_ID_LDO18, | ||
343 | .platform_data = &imote2_ldo_init_data[vcc_io], | ||
344 | }, { | ||
345 | .name = "da903x-regulator", | ||
346 | .id = DA9030_ID_LDO19, | ||
347 | .platform_data = &imote2_ldo_init_data[vcc_pxa_mem], | ||
348 | }, | ||
349 | }; | ||
350 | |||
351 | static struct da903x_platform_data imote2_da9030_pdata = { | ||
352 | .num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs), | ||
353 | .subdevs = imote2_da9030_subdevs, | ||
354 | }; | ||
355 | |||
356 | /* As the the imote2 doesn't currently have a conventional SD slot | ||
357 | * there is no option to hotplug cards, making all this rather simple | ||
358 | */ | ||
359 | static int imote2_mci_get_ro(struct device *dev) | ||
360 | { | ||
361 | return 0; | ||
362 | } | ||
363 | |||
364 | /* Rather simple case as hotplugging not possible */ | ||
365 | static struct pxamci_platform_data imote2_mci_platform_data = { | ||
366 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */ | ||
367 | .get_ro = imote2_mci_get_ro, | ||
368 | }; | ||
369 | |||
370 | static struct mtd_partition imote2flash_partitions[] = { | ||
371 | { | ||
372 | .name = "Bootloader", | ||
373 | .size = 0x00040000, | ||
374 | .offset = 0, | ||
375 | .mask_flags = MTD_WRITEABLE, | ||
376 | }, { | ||
377 | .name = "Kernel", | ||
378 | .size = 0x00200000, | ||
379 | .offset = 0x00040000, | ||
380 | .mask_flags = 0, | ||
381 | }, { | ||
382 | .name = "Filesystem", | ||
383 | .size = 0x01DC0000, | ||
384 | .offset = 0x00240000, | ||
385 | .mask_flags = 0, | ||
386 | }, | ||
387 | }; | ||
388 | |||
389 | static struct resource flash_resources = { | ||
390 | .start = PXA_CS0_PHYS, | ||
391 | .end = PXA_CS0_PHYS + SZ_32M - 1, | ||
392 | .flags = IORESOURCE_MEM, | ||
393 | }; | ||
394 | |||
395 | static struct flash_platform_data imote2_flash_data = { | ||
396 | .map_name = "cfi_probe", | ||
397 | .parts = imote2flash_partitions, | ||
398 | .nr_parts = ARRAY_SIZE(imote2flash_partitions), | ||
399 | .name = "PXA27xOnChipROM", | ||
400 | .width = 2, | ||
401 | }; | ||
402 | |||
403 | static struct platform_device imote2_flash_device = { | ||
404 | .name = "pxa2xx-flash", | ||
405 | .id = 0, | ||
406 | .dev = { | ||
407 | .platform_data = &imote2_flash_data, | ||
408 | }, | ||
409 | .resource = &flash_resources, | ||
410 | .num_resources = 1, | ||
411 | }; | ||
412 | |||
413 | /* Some of the drivers here are out of kernel at the moment (parts of IIO) | ||
414 | * and it may be a while before they are in the mainline. | ||
415 | */ | ||
416 | static struct i2c_board_info __initdata imote2_i2c_board_info[] = { | ||
417 | { /* UCAM sensor board */ | ||
418 | .type = "max1238", | ||
419 | .addr = 0x35, | ||
420 | }, { /* ITS400 Sensor board only */ | ||
421 | .type = "max1363", | ||
422 | .addr = 0x34, | ||
423 | /* Through a nand gate - Also beware, on V2 sensor board the | ||
424 | * pull up resistors are missing. | ||
425 | */ | ||
426 | .irq = IRQ_GPIO(99), | ||
427 | }, { /* ITS400 Sensor board only */ | ||
428 | .type = "tsl2561", | ||
429 | .addr = 0x49, | ||
430 | /* Through a nand gate - Also beware, on V2 sensor board the | ||
431 | * pull up resistors are missing. | ||
432 | */ | ||
433 | .irq = IRQ_GPIO(99), | ||
434 | }, { /* ITS400 Sensor board only */ | ||
435 | .type = "tmp175", | ||
436 | .addr = 0x4A, | ||
437 | .irq = IRQ_GPIO(96), | ||
438 | }, | ||
439 | }; | ||
440 | |||
441 | static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { | ||
442 | { | ||
443 | .type = "da9030", | ||
444 | .addr = 0x49, | ||
445 | .platform_data = &imote2_da9030_pdata, | ||
446 | .irq = gpio_to_irq(1), | ||
447 | }, | ||
448 | }; | ||
449 | |||
450 | static struct pxa2xx_spi_master pxa_ssp_master_0_info = { | ||
451 | .num_chipselect = 1, | ||
452 | }; | ||
453 | |||
454 | static struct pxa2xx_spi_master pxa_ssp_master_1_info = { | ||
455 | .num_chipselect = 1, | ||
456 | }; | ||
457 | |||
458 | static struct pxa2xx_spi_master pxa_ssp_master_2_info = { | ||
459 | .num_chipselect = 1, | ||
460 | }; | ||
461 | |||
462 | /* Patch posted by Eric Miao <eric.miao@marvell.com> will remove | ||
463 | * the need for these functions. | ||
464 | */ | ||
465 | static void spi1control(u32 command) | ||
466 | { | ||
467 | gpio_set_value(24, command & PXA2XX_CS_ASSERT ? 0 : 1); | ||
468 | }; | ||
469 | |||
470 | static void spi3control(u32 command) | ||
471 | { | ||
472 | gpio_set_value(39, command & PXA2XX_CS_ASSERT ? 0 : 1); | ||
473 | }; | ||
474 | |||
475 | static struct pxa2xx_spi_chip staccel_chip_info = { | ||
476 | .tx_threshold = 8, | ||
477 | .rx_threshold = 8, | ||
478 | .dma_burst_size = 8, | ||
479 | .timeout = 235, | ||
480 | .cs_control = spi1control, | ||
481 | }; | ||
482 | |||
483 | static struct pxa2xx_spi_chip cc2420_info = { | ||
484 | .tx_threshold = 8, | ||
485 | .rx_threshold = 8, | ||
486 | .dma_burst_size = 8, | ||
487 | .timeout = 235, | ||
488 | .cs_control = spi3control, | ||
489 | }; | ||
490 | |||
491 | static struct spi_board_info spi_board_info[] __initdata = { | ||
492 | { /* Driver in IIO */ | ||
493 | .modalias = "lis3l02dq", | ||
494 | .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */ | ||
495 | .bus_num = 1, | ||
496 | .chip_select = 0, | ||
497 | .controller_data = &staccel_chip_info, | ||
498 | .irq = IRQ_GPIO(96), | ||
499 | }, { /* Driver out of kernel as it needs considerable rewriting */ | ||
500 | .modalias = "cc2420", | ||
501 | .max_speed_hz = 6500000, | ||
502 | .bus_num = 3, | ||
503 | .chip_select = 0, | ||
504 | .controller_data = &cc2420_info, | ||
505 | }, | ||
506 | }; | ||
507 | |||
508 | static void im2_udc_command(int cmd) | ||
509 | { | ||
510 | switch (cmd) { | ||
511 | case PXA2XX_UDC_CMD_CONNECT: | ||
512 | UP2OCR |= UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE; | ||
513 | break; | ||
514 | case PXA2XX_UDC_CMD_DISCONNECT: | ||
515 | UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE); | ||
516 | break; | ||
517 | } | ||
518 | } | ||
519 | |||
520 | static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = { | ||
521 | .udc_command = im2_udc_command, | ||
522 | }; | ||
523 | |||
524 | static struct platform_device *imote2_devices[] = { | ||
525 | &imote2_flash_device, | ||
526 | &imote2_leds, | ||
527 | }; | ||
528 | |||
529 | static struct i2c_pxa_platform_data i2c_pwr_pdata = { | ||
530 | .fast_mode = 1, | ||
531 | }; | ||
532 | |||
533 | static struct i2c_pxa_platform_data i2c_pdata = { | ||
534 | .fast_mode = 1, | ||
535 | }; | ||
536 | |||
537 | static void __init imote2_init(void) | ||
538 | { | ||
539 | |||
540 | pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); | ||
541 | /* SPI chip select directions - all other directions should | ||
542 | * be handled by drivers.*/ | ||
543 | gpio_direction_output(37, 0); | ||
544 | gpio_direction_output(24, 0); | ||
545 | gpio_direction_output(39, 0); | ||
546 | |||
547 | platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices)); | ||
548 | |||
549 | pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info); | ||
550 | pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info); | ||
551 | pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info); | ||
552 | |||
553 | spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); | ||
554 | |||
555 | i2c_register_board_info(0, imote2_i2c_board_info, | ||
556 | ARRAY_SIZE(imote2_i2c_board_info)); | ||
557 | i2c_register_board_info(1, imote2_pwr_i2c_board_info, | ||
558 | ARRAY_SIZE(imote2_pwr_i2c_board_info)); | ||
559 | |||
560 | pxa27x_set_i2c_power_info(&i2c_pwr_pdata); | ||
561 | pxa_set_i2c_info(&i2c_pdata); | ||
562 | |||
563 | pxa_set_mci_info(&imote2_mci_platform_data); | ||
564 | pxa_set_udc_info(&imote2_udc_info); | ||
565 | } | ||
566 | |||
567 | MACHINE_START(INTELMOTE2, "IMOTE 2") | ||
568 | .phys_io = 0x40000000, | ||
569 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
570 | .map_io = pxa_map_io, | ||
571 | .init_irq = pxa27x_init_irq, | ||
572 | .timer = &pxa_timer, | ||
573 | .init_machine = imote2_init, | ||
574 | .boot_params = 0xA0000100, | ||
575 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/include/mach/clkdev.h b/arch/arm/mach-pxa/include/mach/clkdev.h new file mode 100644 index 000000000000..04b37a89801c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __ASM_MACH_CLKDEV_H | ||
2 | #define __ASM_MACH_CLKDEV_H | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do { } while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h index 955bfe606067..7804637a6df3 100644 --- a/arch/arm/mach-pxa/include/mach/dma.h +++ b/arch/arm/mach-pxa/include/mach/dma.h | |||
@@ -30,10 +30,6 @@ typedef enum { | |||
30 | DMA_PRIO_LOW = 2 | 30 | DMA_PRIO_LOW = 2 |
31 | } pxa_dma_prio; | 31 | } pxa_dma_prio; |
32 | 32 | ||
33 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) | ||
34 | #define HAVE_ARCH_PCI_SET_DMA_MASK 1 | ||
35 | #endif | ||
36 | |||
37 | /* | 33 | /* |
38 | * DMA registration | 34 | * DMA registration |
39 | */ | 35 | */ |
diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h index 4c90b1310270..efbd2aa9ecec 100644 --- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h +++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h | |||
@@ -43,8 +43,10 @@ | |||
43 | #define GPIO_E800_PCMCIA_PWR1 73 | 43 | #define GPIO_E800_PCMCIA_PWR1 73 |
44 | 44 | ||
45 | /* e7xx IrDA power control */ | 45 | /* e7xx IrDA power control */ |
46 | #define GPIO_E7XX_IR_ON 38 | 46 | #define GPIO_E7XX_IR_OFF 38 |
47 | 47 | ||
48 | /* ASIC related GPIOs */ | 48 | /* ASIC related GPIOs */ |
49 | #define GPIO_ESERIES_TMIO_IRQ 5 | 49 | #define GPIO_ESERIES_TMIO_IRQ 5 |
50 | #define GPIO_ESERIES_TMIO_PCLR 19 | ||
51 | #define GPIO_ESERIES_TMIO_SUSPEND 45 | ||
50 | #define GPIO_E800_ANGELX_IRQ 8 | 52 | #define GPIO_E800_ANGELX_IRQ 8 |
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 42ee1956750e..099f54a41de4 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h | |||
@@ -94,3 +94,7 @@ has detected a cable insertion; driven low otherwise. */ | |||
94 | #define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) | 94 | #define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) |
95 | #define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) | 95 | #define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) |
96 | #define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) | 96 | #define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) |
97 | |||
98 | /* for expansion boards that can't be programatically detected */ | ||
99 | extern int am200_init(void); | ||
100 | |||
diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h new file mode 100644 index 000000000000..2a5ae3802787 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/h5000.h | |||
@@ -0,0 +1,113 @@ | |||
1 | /* | ||
2 | * Hardware definitions for HP iPAQ h5xxx Handheld Computers | ||
3 | * | ||
4 | * Copyright(20)02 Hewlett-Packard Company. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | ||
12 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | ||
13 | * FITNESS FOR ANY PARTICULAR PURPOSE. | ||
14 | * | ||
15 | * Author: Jamey Hicks | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_H5000_H | ||
19 | #define __ASM_ARCH_H5000_H | ||
20 | |||
21 | #include <mach/mfp-pxa25x.h> | ||
22 | |||
23 | /* | ||
24 | * CPU GPIOs | ||
25 | */ | ||
26 | |||
27 | #define H5000_GPIO_POWER_BUTTON (0) | ||
28 | #define H5000_GPIO_RESET_BUTTON_N (1) | ||
29 | #define H5000_GPIO_OPT_INT (2) | ||
30 | #define H5000_GPIO_BACKUP_POWER (3) | ||
31 | #define H5000_GPIO_ACTION_BUTTON (4) | ||
32 | #define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */ | ||
33 | /* 6 not connected */ | ||
34 | #define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */ | ||
35 | /* 8 not connected */ | ||
36 | #define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */ | ||
37 | #define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */ | ||
38 | #define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */ | ||
39 | /*(12) not connected */ | ||
40 | #define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */ | ||
41 | #define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */ | ||
42 | /*(15) is CS1# */ | ||
43 | /*(16) not connected */ | ||
44 | /*(17) not connected */ | ||
45 | /*(18) is pcmcia ready */ | ||
46 | /*(19) is dreq1 */ | ||
47 | /*(20) is dreq0 */ | ||
48 | #define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */ | ||
49 | /*(22) is not connected */ | ||
50 | #define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */ | ||
51 | #define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */ | ||
52 | #define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */ | ||
53 | #define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */ | ||
54 | /*(27) not connected */ | ||
55 | #define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */ | ||
56 | #define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */ | ||
57 | #define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */ | ||
58 | #define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */ | ||
59 | #define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */ | ||
60 | /*(33) is CS5# */ | ||
61 | #define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */ | ||
62 | #define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */ | ||
63 | #define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */ | ||
64 | #define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */ | ||
65 | #define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */ | ||
66 | #define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */ | ||
67 | #define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */ | ||
68 | #define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */ | ||
69 | |||
70 | #define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */ | ||
71 | #define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */ | ||
72 | #define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */ | ||
73 | #define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */ | ||
74 | |||
75 | #define H5000_GPIO_IRDA_RXD (46) | ||
76 | #define H5000_GPIO_IRDA_TXD (47) | ||
77 | |||
78 | #define H5000_GPIO_POE_N (48) /* used for pcmcia */ | ||
79 | #define H5000_GPIO_PWE_N (49) /* used for pcmcia */ | ||
80 | #define H5000_GPIO_PIOR_N (50) /* used for pcmcia */ | ||
81 | #define H5000_GPIO_PIOW_N (51) /* used for pcmcia */ | ||
82 | #define H5000_GPIO_PCE1_N (52) /* used for pcmcia */ | ||
83 | #define H5000_GPIO_PCE2_N (53) /* used for pcmcia */ | ||
84 | #define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */ | ||
85 | #define H5000_GPIO_PREG_N (55) /* used for pcmcia */ | ||
86 | #define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */ | ||
87 | #define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */ | ||
88 | |||
89 | #define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */ | ||
90 | /*(59) not connected */ | ||
91 | #define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */ | ||
92 | #define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */ | ||
93 | #define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */ | ||
94 | /*(63) is not connected */ | ||
95 | #define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */ | ||
96 | #define H5000_GPIO_CHG_EN (65) /* to sc801 en */ | ||
97 | #define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */ | ||
98 | #define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */ | ||
99 | #define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */ | ||
100 | /*(69) is not connected */ | ||
101 | #define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */ | ||
102 | #define H5000_GPIO_POWER_LIGHT_SENSOR_N (71) | ||
103 | #define H5000_GPIO_BT_M_RESET (72) | ||
104 | #define H5000_GPIO_STD_CHG_RATE (73) | ||
105 | #define H5000_GPIO_SD_WP_N (74) | ||
106 | #define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */ | ||
107 | #define H5000_GPIO_HEADPHONE_DETECT (76) | ||
108 | #define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */ | ||
109 | /*(78) is CS2# */ | ||
110 | /*(79) is CS3# */ | ||
111 | /*(80) is CS4# */ | ||
112 | |||
113 | #endif /* __ASM_ARCH_H5000_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index a582a6d9b92b..16ab79547dae 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h | |||
@@ -102,6 +102,9 @@ | |||
102 | * PXA930 B0 0x69056835 0x5E643013 | 102 | * PXA930 B0 0x69056835 0x5E643013 |
103 | * PXA930 B1 0x69056837 0x7E643013 | 103 | * PXA930 B1 0x69056837 0x7E643013 |
104 | * PXA930 B2 0x69056838 0x8E643013 | 104 | * PXA930 B2 0x69056838 0x8E643013 |
105 | * | ||
106 | * PXA935 A0 0x56056931 0x1E653013 | ||
107 | * PXA935 B0 0x56056936 0x6E653013 | ||
105 | */ | 108 | */ |
106 | #ifdef CONFIG_PXA25x | 109 | #ifdef CONFIG_PXA25x |
107 | #define __cpu_is_pxa210(id) \ | 110 | #define __cpu_is_pxa210(id) \ |
@@ -178,12 +181,22 @@ | |||
178 | #define __cpu_is_pxa930(id) \ | 181 | #define __cpu_is_pxa930(id) \ |
179 | ({ \ | 182 | ({ \ |
180 | unsigned int _id = (id) >> 4 & 0xfff; \ | 183 | unsigned int _id = (id) >> 4 & 0xfff; \ |
181 | _id == 0x683; \ | 184 | _id == 0x683; \ |
182 | }) | 185 | }) |
183 | #else | 186 | #else |
184 | #define __cpu_is_pxa930(id) (0) | 187 | #define __cpu_is_pxa930(id) (0) |
185 | #endif | 188 | #endif |
186 | 189 | ||
190 | #ifdef CONFIG_CPU_PXA935 | ||
191 | #define __cpu_is_pxa935(id) \ | ||
192 | ({ \ | ||
193 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
194 | _id == 0x693; \ | ||
195 | }) | ||
196 | #else | ||
197 | #define __cpu_is_pxa935(id) (0) | ||
198 | #endif | ||
199 | |||
187 | #define cpu_is_pxa210() \ | 200 | #define cpu_is_pxa210() \ |
188 | ({ \ | 201 | ({ \ |
189 | __cpu_is_pxa210(read_cpuid_id()); \ | 202 | __cpu_is_pxa210(read_cpuid_id()); \ |
@@ -204,8 +217,6 @@ | |||
204 | __cpu_is_pxa25x(read_cpuid_id()); \ | 217 | __cpu_is_pxa25x(read_cpuid_id()); \ |
205 | }) | 218 | }) |
206 | 219 | ||
207 | extern int cpu_is_pxa26x(void); | ||
208 | |||
209 | #define cpu_is_pxa27x() \ | 220 | #define cpu_is_pxa27x() \ |
210 | ({ \ | 221 | ({ \ |
211 | __cpu_is_pxa27x(read_cpuid_id()); \ | 222 | __cpu_is_pxa27x(read_cpuid_id()); \ |
@@ -232,6 +243,12 @@ extern int cpu_is_pxa26x(void); | |||
232 | __cpu_is_pxa930(id); \ | 243 | __cpu_is_pxa930(id); \ |
233 | }) | 244 | }) |
234 | 245 | ||
246 | #define cpu_is_pxa935() \ | ||
247 | ({ \ | ||
248 | unsigned int id = read_cpuid(CPUID_ID); \ | ||
249 | __cpu_is_pxa935(id); \ | ||
250 | }) | ||
251 | |||
235 | /* | 252 | /* |
236 | * CPUID Core Generation Bit | 253 | * CPUID Core Generation Bit |
237 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x | 254 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x |
@@ -249,6 +266,12 @@ extern int cpu_is_pxa26x(void); | |||
249 | _id == 0x3; \ | 266 | _id == 0x3; \ |
250 | }) | 267 | }) |
251 | 268 | ||
269 | #define __cpu_is_pxa9xx(id) \ | ||
270 | ({ \ | ||
271 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
272 | _id == 0x683 || _id == 0x693; \ | ||
273 | }) | ||
274 | |||
252 | #define cpu_is_pxa2xx() \ | 275 | #define cpu_is_pxa2xx() \ |
253 | ({ \ | 276 | ({ \ |
254 | __cpu_is_pxa2xx(read_cpuid_id()); \ | 277 | __cpu_is_pxa2xx(read_cpuid_id()); \ |
@@ -259,32 +282,25 @@ extern int cpu_is_pxa26x(void); | |||
259 | __cpu_is_pxa3xx(read_cpuid_id()); \ | 282 | __cpu_is_pxa3xx(read_cpuid_id()); \ |
260 | }) | 283 | }) |
261 | 284 | ||
262 | /* | 285 | #define cpu_is_pxa9xx() \ |
263 | * Handy routine to set GPIO alternate functions | 286 | ({ \ |
264 | */ | 287 | __cpu_is_pxa9xx(read_cpuid_id()); \ |
265 | extern int pxa_gpio_mode( int gpio_mode ); | 288 | }) |
266 | |||
267 | /* | ||
268 | * Return GPIO level, nonzero means high, zero is low | ||
269 | */ | ||
270 | extern int pxa_gpio_get_value(unsigned gpio); | ||
271 | |||
272 | /* | ||
273 | * Set output GPIO level | ||
274 | */ | ||
275 | extern void pxa_gpio_set_value(unsigned gpio, int value); | ||
276 | |||
277 | /* | 289 | /* |
278 | * return current memory and LCD clock frequency in units of 10kHz | 290 | * return current memory and LCD clock frequency in units of 10kHz |
279 | */ | 291 | */ |
280 | extern unsigned int get_memclk_frequency_10khz(void); | 292 | extern unsigned int get_memclk_frequency_10khz(void); |
281 | 293 | ||
294 | /* return the clock tick rate of the OS timer */ | ||
295 | extern unsigned long get_clock_tick_rate(void); | ||
282 | #endif | 296 | #endif |
283 | 297 | ||
284 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) | 298 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) |
285 | #define PCIBIOS_MIN_IO 0 | 299 | #define PCIBIOS_MIN_IO 0 |
286 | #define PCIBIOS_MIN_MEM 0 | 300 | #define PCIBIOS_MIN_MEM 0 |
287 | #define pcibios_assign_all_busses() 1 | 301 | #define pcibios_assign_all_busses() 1 |
302 | #define HAVE_ARCH_PCI_SET_DMA_MASK 1 | ||
288 | #endif | 303 | #endif |
289 | 304 | ||
305 | |||
290 | #endif /* _ASM_ARCH_HARDWARE_H */ | 306 | #endif /* _ASM_ARCH_HARDWARE_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h index 600fd4f76603..262691fb97d8 100644 --- a/arch/arm/mach-pxa/include/mach/io.h +++ b/arch/arm/mach-pxa/include/mach/io.h | |||
@@ -6,15 +6,13 @@ | |||
6 | #ifndef __ASM_ARM_ARCH_IO_H | 6 | #ifndef __ASM_ARM_ARCH_IO_H |
7 | #define __ASM_ARM_ARCH_IO_H | 7 | #define __ASM_ARM_ARCH_IO_H |
8 | 8 | ||
9 | #include <mach/hardware.h> | ||
10 | |||
11 | #define IO_SPACE_LIMIT 0xffffffff | 9 | #define IO_SPACE_LIMIT 0xffffffff |
12 | 10 | ||
13 | /* | 11 | /* |
14 | * We don't actually have real ISA nor PCI buses, but there is so many | 12 | * We don't actually have real ISA nor PCI buses, but there is so many |
15 | * drivers out there that might just work if we fake them... | 13 | * drivers out there that might just work if we fake them... |
16 | */ | 14 | */ |
17 | #define __io(a) ((void __iomem *)(a)) | 15 | #define __io(a) __typesafe_io(a) |
18 | #define __mem_pci(a) (a) | 16 | #define __mem_pci(a) (a) |
19 | 17 | ||
20 | #endif | 18 | #endif |
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h index 5c4e320c1437..6c9b21c51322 100644 --- a/arch/arm/mach-pxa/include/mach/littleton.h +++ b/arch/arm/mach-pxa/include/mach/littleton.h | |||
@@ -1,8 +1,13 @@ | |||
1 | #ifndef __ASM_ARCH_ZYLONITE_H | 1 | #ifndef __ASM_ARCH_LITTLETON_H |
2 | #define __ASM_ARCH_ZYLONITE_H | 2 | #define __ASM_ARCH_LITTLETON_H |
3 | |||
4 | #include <mach/gpio.h> | ||
3 | 5 | ||
4 | #define LITTLETON_ETH_PHYS 0x30000000 | 6 | #define LITTLETON_ETH_PHYS 0x30000000 |
5 | 7 | ||
6 | #define LITTLETON_GPIO_LCD_CS (17) | 8 | #define LITTLETON_GPIO_LCD_CS (17) |
7 | 9 | ||
8 | #endif /* __ASM_ARCH_ZYLONITE_H */ | 10 | #define EXT0_GPIO_BASE (NR_BUILTIN_GPIO) |
11 | #define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) | ||
12 | |||
13 | #endif /* __ASM_ARCH_LITTLETON_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 59aef89808d6..f626730ee42e 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h | |||
@@ -18,16 +18,6 @@ | |||
18 | #define PHYS_OFFSET UL(0xa0000000) | 18 | #define PHYS_OFFSET UL(0xa0000000) |
19 | 19 | ||
20 | /* | 20 | /* |
21 | * Virtual view <-> DMA view memory address translations | ||
22 | * virt_to_bus: Used to translate the virtual address to an | ||
23 | * address suitable to be passed to set_dma_addr | ||
24 | * bus_to_virt: Used to convert an address for DMA operations | ||
25 | * to an address that the kernel can use. | ||
26 | */ | ||
27 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
28 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
29 | |||
30 | /* | ||
31 | * The nodes are matched with the physical SDRAM banks as follows: | 21 | * The nodes are matched with the physical SDRAM banks as follows: |
32 | * | 22 | * |
33 | * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff | 23 | * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff |
@@ -47,6 +37,7 @@ void cmx2xx_pci_adjust_zones(int node, unsigned long *size, | |||
47 | cmx2xx_pci_adjust_zones(node, size, holes) | 37 | cmx2xx_pci_adjust_zones(node, size, holes) |
48 | 38 | ||
49 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) | 39 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) |
40 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) | ||
50 | #endif | 41 | #endif |
51 | 42 | ||
52 | #endif | 43 | #endif |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index 617cab2cc8d0..a72869b73ee3 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h | |||
@@ -158,4 +158,35 @@ | |||
158 | #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) | 158 | #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) |
159 | #define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) | 159 | #define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) |
160 | 160 | ||
161 | #ifdef CONFIG_CPU_PXA26x | ||
162 | /* GPIO */ | ||
163 | #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) | ||
164 | #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1) | ||
165 | #define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1) | ||
166 | #define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1) | ||
167 | #define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1) | ||
168 | |||
169 | /* SDRAM */ | ||
170 | #define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) | ||
171 | #define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) | ||
172 | #define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) | ||
173 | #define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) | ||
174 | |||
175 | /* USB */ | ||
176 | #define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) | ||
177 | #define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2) | ||
178 | #define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2) | ||
179 | #define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW) | ||
180 | #define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) | ||
181 | #define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH) | ||
182 | |||
183 | /* ASSP */ | ||
184 | #define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3) | ||
185 | #define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW) | ||
186 | #define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3) | ||
187 | #define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) | ||
188 | #define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) | ||
189 | #define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) | ||
190 | #endif | ||
191 | |||
161 | #endif /* __ASM_ARCH_MFP_PXA25X_H */ | 192 | #endif /* __ASM_ARCH_MFP_PXA25X_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index 122bdbd53182..da4f85a4f990 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h | |||
@@ -11,6 +11,12 @@ | |||
11 | #include <mach/mfp.h> | 11 | #include <mach/mfp.h> |
12 | #include <mach/mfp-pxa2xx.h> | 12 | #include <mach/mfp-pxa2xx.h> |
13 | 13 | ||
14 | /* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN | ||
15 | * bit is set, regardless of the GPIO configuration | ||
16 | */ | ||
17 | #define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) | ||
18 | #define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) | ||
19 | |||
14 | /* GPIO */ | 20 | /* GPIO */ |
15 | #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) | 21 | #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) |
16 | #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) | 22 | #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h index fabd9b4df827..fa73f56a1372 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h | |||
@@ -421,6 +421,7 @@ | |||
421 | #define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) | 421 | #define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) |
422 | #define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) | 422 | #define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) |
423 | #define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) | 423 | #define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) |
424 | #define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW) | ||
424 | 425 | ||
425 | /* CIR */ | 426 | /* CIR */ |
426 | #define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) | 427 | #define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) |
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h index 8483cb511831..02868447b0b1 100644 --- a/arch/arm/mach-pxa/include/mach/mioa701.h +++ b/arch/arm/mach-pxa/include/mach/mioa701.h | |||
@@ -10,12 +10,14 @@ | |||
10 | (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) | 10 | (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) |
11 | 11 | ||
12 | /* Global GPIOs */ | 12 | /* Global GPIOs */ |
13 | #define GPIO9_CHARGE_nEN 9 | 13 | #define GPIO9_CHARGE_EN 9 |
14 | #define GPIO18_POWEROFF 18 | 14 | #define GPIO18_POWEROFF 18 |
15 | #define GPIO87_LCD_POWER 87 | 15 | #define GPIO87_LCD_POWER 87 |
16 | #define GPIO96_AC_DETECT 96 | ||
17 | #define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ | ||
16 | 18 | ||
17 | /* USB */ | 19 | /* USB */ |
18 | #define GPIO13_USB_DETECT 13 | 20 | #define GPIO13_nUSB_DETECT 13 |
19 | #define GPIO22_USB_ENABLE 22 | 21 | #define GPIO22_USB_ENABLE 22 |
20 | 22 | ||
21 | /* SDIO bits */ | 23 | /* SDIO bits */ |
@@ -24,7 +26,10 @@ | |||
24 | #define GPIO91_SDIO_EN 91 | 26 | #define GPIO91_SDIO_EN 91 |
25 | 27 | ||
26 | /* Bluetooth */ | 28 | /* Bluetooth */ |
29 | #define GPIO14_BT_nACTIVITY 14 | ||
27 | #define GPIO83_BT_ON 83 | 30 | #define GPIO83_BT_ON 83 |
31 | #define GPIO77_BT_UNKNOWN1 77 | ||
32 | #define GPIO86_BT_MAYBE_nRESET 86 | ||
28 | 33 | ||
29 | /* GPS */ | 34 | /* GPS */ |
30 | #define GPIO23_GPS_UNKNOWN1 23 | 35 | #define GPIO23_GPS_UNKNOWN1 23 |
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index 4d452fcb1508..cfca8155be72 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h | |||
@@ -15,6 +15,7 @@ | |||
15 | #ifndef __ARCH_PXA_MTD_XIP_H__ | 15 | #ifndef __ARCH_PXA_MTD_XIP_H__ |
16 | #define __ARCH_PXA_MTD_XIP_H__ | 16 | #define __ARCH_PXA_MTD_XIP_H__ |
17 | 17 | ||
18 | #include <mach/hardware.h> | ||
18 | #include <mach/pxa-regs.h> | 19 | #include <mach/pxa-regs.h> |
19 | 20 | ||
20 | #define xip_irqpending() (ICIP & ICMR) | 21 | #define xip_irqpending() (ICIP & ICMR) |
diff --git a/arch/arm/mach-pxa/include/mach/palmasoc.h b/arch/arm/mach-pxa/include/mach/palmasoc.h new file mode 100644 index 000000000000..6c4b1f7de20a --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmasoc.h | |||
@@ -0,0 +1,13 @@ | |||
1 | #ifndef _INCLUDE_PALMASOC_H_ | ||
2 | #define _INCLUDE_PALMASOC_H_ | ||
3 | struct palm27x_asoc_info { | ||
4 | int jack_gpio; | ||
5 | }; | ||
6 | |||
7 | #ifdef CONFIG_SND_PXA2XX_SOC_PALM27X | ||
8 | void __init palm27x_asoc_set_pdata(struct palm27x_asoc_info *data); | ||
9 | #else | ||
10 | static inline void palm27x_asoc_set_pdata(struct palm27x_asoc_info *data) {} | ||
11 | #endif | ||
12 | |||
13 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index 15295d960000..31d615aa7723 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h | |||
@@ -13,6 +13,7 @@ | |||
13 | #ifndef __PXA_REGS_H | 13 | #ifndef __PXA_REGS_H |
14 | #define __PXA_REGS_H | 14 | #define __PXA_REGS_H |
15 | 15 | ||
16 | #include <mach/hardware.h> | ||
16 | 17 | ||
17 | /* | 18 | /* |
18 | * PXA Chip selects | 19 | * PXA Chip selects |
@@ -123,298 +124,6 @@ | |||
123 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | 124 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ |
124 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | 125 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
125 | 126 | ||
126 | |||
127 | /* | ||
128 | * UARTs | ||
129 | */ | ||
130 | |||
131 | /* Full Function UART (FFUART) */ | ||
132 | #define FFUART FFRBR | ||
133 | #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ | ||
134 | #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ | ||
135 | #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ | ||
136 | #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ | ||
137 | #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ | ||
138 | #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ | ||
139 | #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ | ||
140 | #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ | ||
141 | #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ | ||
142 | #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ | ||
143 | #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ | ||
144 | #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
145 | #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
146 | |||
147 | /* Bluetooth UART (BTUART) */ | ||
148 | #define BTUART BTRBR | ||
149 | #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ | ||
150 | #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ | ||
151 | #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ | ||
152 | #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ | ||
153 | #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ | ||
154 | #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ | ||
155 | #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ | ||
156 | #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ | ||
157 | #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ | ||
158 | #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ | ||
159 | #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ | ||
160 | #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
161 | #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
162 | |||
163 | /* Standard UART (STUART) */ | ||
164 | #define STUART STRBR | ||
165 | #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ | ||
166 | #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ | ||
167 | #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ | ||
168 | #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ | ||
169 | #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ | ||
170 | #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ | ||
171 | #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ | ||
172 | #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ | ||
173 | #define STMSR __REG(0x40700018) /* Reserved */ | ||
174 | #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ | ||
175 | #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ | ||
176 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
177 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
178 | |||
179 | /* Hardware UART (HWUART) */ | ||
180 | #define HWUART HWRBR | ||
181 | #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ | ||
182 | #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ | ||
183 | #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ | ||
184 | #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ | ||
185 | #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ | ||
186 | #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ | ||
187 | #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ | ||
188 | #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ | ||
189 | #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ | ||
190 | #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ | ||
191 | #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ | ||
192 | #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ | ||
193 | #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ | ||
194 | #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ | ||
195 | #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
196 | #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
197 | |||
198 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ | ||
199 | #define IER_UUE (1 << 6) /* UART Unit Enable */ | ||
200 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ | ||
201 | #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ | ||
202 | #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ | ||
203 | #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ | ||
204 | #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ | ||
205 | #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ | ||
206 | |||
207 | #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ | ||
208 | #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ | ||
209 | #define IIR_TOD (1 << 3) /* Time Out Detected */ | ||
210 | #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ | ||
211 | #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ | ||
212 | #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ | ||
213 | |||
214 | #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ | ||
215 | #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ | ||
216 | #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ | ||
217 | #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ | ||
218 | #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ | ||
219 | #define FCR_ITL_1 (0) | ||
220 | #define FCR_ITL_8 (FCR_ITL1) | ||
221 | #define FCR_ITL_16 (FCR_ITL2) | ||
222 | #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) | ||
223 | |||
224 | #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ | ||
225 | #define LCR_SB (1 << 6) /* Set Break */ | ||
226 | #define LCR_STKYP (1 << 5) /* Sticky Parity */ | ||
227 | #define LCR_EPS (1 << 4) /* Even Parity Select */ | ||
228 | #define LCR_PEN (1 << 3) /* Parity Enable */ | ||
229 | #define LCR_STB (1 << 2) /* Stop Bit */ | ||
230 | #define LCR_WLS1 (1 << 1) /* Word Length Select */ | ||
231 | #define LCR_WLS0 (1 << 0) /* Word Length Select */ | ||
232 | |||
233 | #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ | ||
234 | #define LSR_TEMT (1 << 6) /* Transmitter Empty */ | ||
235 | #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ | ||
236 | #define LSR_BI (1 << 4) /* Break Interrupt */ | ||
237 | #define LSR_FE (1 << 3) /* Framing Error */ | ||
238 | #define LSR_PE (1 << 2) /* Parity Error */ | ||
239 | #define LSR_OE (1 << 1) /* Overrun Error */ | ||
240 | #define LSR_DR (1 << 0) /* Data Ready */ | ||
241 | |||
242 | #define MCR_LOOP (1 << 4) | ||
243 | #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ | ||
244 | #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ | ||
245 | #define MCR_RTS (1 << 1) /* Request to Send */ | ||
246 | #define MCR_DTR (1 << 0) /* Data Terminal Ready */ | ||
247 | |||
248 | #define MSR_DCD (1 << 7) /* Data Carrier Detect */ | ||
249 | #define MSR_RI (1 << 6) /* Ring Indicator */ | ||
250 | #define MSR_DSR (1 << 5) /* Data Set Ready */ | ||
251 | #define MSR_CTS (1 << 4) /* Clear To Send */ | ||
252 | #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ | ||
253 | #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ | ||
254 | #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ | ||
255 | #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ | ||
256 | |||
257 | /* | ||
258 | * IrSR (Infrared Selection Register) | ||
259 | */ | ||
260 | #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ | ||
261 | #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ | ||
262 | #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ | ||
263 | #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ | ||
264 | #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ | ||
265 | |||
266 | |||
267 | /* | ||
268 | * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c | ||
269 | */ | ||
270 | |||
271 | /* | ||
272 | * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c | ||
273 | */ | ||
274 | |||
275 | /* | ||
276 | * AC97 Controller registers | ||
277 | */ | ||
278 | |||
279 | #define POCR __REG(0x40500000) /* PCM Out Control Register */ | ||
280 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
281 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
282 | |||
283 | #define PICR __REG(0x40500004) /* PCM In Control Register */ | ||
284 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
285 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
286 | |||
287 | #define MCCR __REG(0x40500008) /* Mic In Control Register */ | ||
288 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
289 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
290 | |||
291 | #define GCR __REG(0x4050000C) /* Global Control Register */ | ||
292 | #ifdef CONFIG_PXA3xx | ||
293 | #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ | ||
294 | #endif | ||
295 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ | ||
296 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ | ||
297 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ | ||
298 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ | ||
299 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ | ||
300 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ | ||
301 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ | ||
302 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ | ||
303 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ | ||
304 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ | ||
305 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ | ||
306 | |||
307 | #define POSR __REG(0x40500010) /* PCM Out Status Register */ | ||
308 | #define POSR_FIFOE (1 << 4) /* FIFO error */ | ||
309 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ | ||
310 | |||
311 | #define PISR __REG(0x40500014) /* PCM In Status Register */ | ||
312 | #define PISR_FIFOE (1 << 4) /* FIFO error */ | ||
313 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
314 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ | ||
315 | |||
316 | #define MCSR __REG(0x40500018) /* Mic In Status Register */ | ||
317 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ | ||
318 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
319 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ | ||
320 | |||
321 | #define GSR __REG(0x4050001C) /* Global Status Register */ | ||
322 | #define GSR_CDONE (1 << 19) /* Command Done */ | ||
323 | #define GSR_SDONE (1 << 18) /* Status Done */ | ||
324 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ | ||
325 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ | ||
326 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ | ||
327 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ | ||
328 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ | ||
329 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ | ||
330 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ | ||
331 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ | ||
332 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ | ||
333 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ | ||
334 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ | ||
335 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ | ||
336 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ | ||
337 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ | ||
338 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ | ||
339 | |||
340 | #define CAR __REG(0x40500020) /* CODEC Access Register */ | ||
341 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ | ||
342 | |||
343 | #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ | ||
344 | #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ | ||
345 | |||
346 | #define MOCR __REG(0x40500100) /* Modem Out Control Register */ | ||
347 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ | ||
348 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
349 | |||
350 | #define MICR __REG(0x40500108) /* Modem In Control Register */ | ||
351 | #define MICR_FEIE (1 << 3) /* FIFO Error */ | ||
352 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
353 | |||
354 | #define MOSR __REG(0x40500110) /* Modem Out Status Register */ | ||
355 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ | ||
356 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ | ||
357 | |||
358 | #define MISR __REG(0x40500118) /* Modem In Status Register */ | ||
359 | #define MISR_FIFOE (1 << 4) /* FIFO error */ | ||
360 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
361 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ | ||
362 | |||
363 | #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ | ||
364 | |||
365 | #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ | ||
366 | #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ | ||
367 | #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ | ||
368 | #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ | ||
369 | |||
370 | |||
371 | /* | ||
372 | * Fast Infrared Communication Port | ||
373 | */ | ||
374 | |||
375 | #define FICP __REG(0x40800000) /* Start of FICP area */ | ||
376 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ | ||
377 | #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ | ||
378 | #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ | ||
379 | #define ICDR __REG(0x4080000c) /* ICP Data Register */ | ||
380 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ | ||
381 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ | ||
382 | |||
383 | #define ICCR0_AME (1 << 7) /* Address match enable */ | ||
384 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ | ||
385 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ | ||
386 | #define ICCR0_RXE (1 << 4) /* Receive enable */ | ||
387 | #define ICCR0_TXE (1 << 3) /* Transmit enable */ | ||
388 | #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ | ||
389 | #define ICCR0_LBM (1 << 1) /* Loopback mode */ | ||
390 | #define ICCR0_ITR (1 << 0) /* IrDA transmission */ | ||
391 | |||
392 | #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ | ||
393 | #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ | ||
394 | #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ | ||
395 | #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ | ||
396 | #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ | ||
397 | #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ | ||
398 | |||
399 | #ifdef CONFIG_PXA27x | ||
400 | #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ | ||
401 | #endif | ||
402 | #define ICSR0_FRE (1 << 5) /* Framing error */ | ||
403 | #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ | ||
404 | #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ | ||
405 | #define ICSR0_RAB (1 << 2) /* Receiver abort */ | ||
406 | #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ | ||
407 | #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ | ||
408 | |||
409 | #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ | ||
410 | #define ICSR1_CRE (1 << 5) /* CRC error */ | ||
411 | #define ICSR1_EOF (1 << 4) /* End of frame */ | ||
412 | #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ | ||
413 | #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ | ||
414 | #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ | ||
415 | #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ | ||
416 | |||
417 | |||
418 | /* | 127 | /* |
419 | * Real Time Clock | 128 | * Real Time Clock |
420 | */ | 129 | */ |
@@ -463,19 +172,6 @@ | |||
463 | 172 | ||
464 | 173 | ||
465 | /* | 174 | /* |
466 | * Pulse Width Modulator | ||
467 | */ | ||
468 | |||
469 | #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ | ||
470 | #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ | ||
471 | #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ | ||
472 | |||
473 | #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ | ||
474 | #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ | ||
475 | #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ | ||
476 | |||
477 | |||
478 | /* | ||
479 | * Interrupt Controller | 175 | * Interrupt Controller |
480 | */ | 176 | */ |
481 | 177 | ||
@@ -496,19 +192,6 @@ | |||
496 | * General Purpose I/O | 192 | * General Purpose I/O |
497 | */ | 193 | */ |
498 | 194 | ||
499 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) | ||
500 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | ||
501 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | ||
502 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | ||
503 | |||
504 | #define GPLR_OFFSET 0x00 | ||
505 | #define GPDR_OFFSET 0x0C | ||
506 | #define GPSR_OFFSET 0x18 | ||
507 | #define GPCR_OFFSET 0x24 | ||
508 | #define GRER_OFFSET 0x30 | ||
509 | #define GFER_OFFSET 0x3C | ||
510 | #define GEDR_OFFSET 0x48 | ||
511 | |||
512 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ | 195 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ |
513 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ | 196 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ |
514 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ | 197 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ |
@@ -558,10 +241,6 @@ | |||
558 | 241 | ||
559 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | 242 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) |
560 | 243 | ||
561 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
562 | |||
563 | /* Interrupt Controller */ | ||
564 | |||
565 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | 244 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |
566 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | 245 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) |
567 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | 246 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) |
@@ -580,189 +259,5 @@ | |||
580 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) | 259 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) |
581 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ | 260 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ |
582 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) | 261 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) |
583 | #else | ||
584 | |||
585 | #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | ||
586 | #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | ||
587 | #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | ||
588 | #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | ||
589 | #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | ||
590 | #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | ||
591 | #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | ||
592 | #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | ||
593 | |||
594 | #endif | ||
595 | |||
596 | /* | ||
597 | * Power Manager - see pxa2xx-regs.h | ||
598 | */ | ||
599 | |||
600 | /* | ||
601 | * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h | ||
602 | */ | ||
603 | |||
604 | /* | ||
605 | * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h | ||
606 | */ | ||
607 | |||
608 | /* | ||
609 | * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | ||
610 | */ | ||
611 | |||
612 | #ifdef CONFIG_PXA27x | ||
613 | |||
614 | /* Camera Interface */ | ||
615 | #define CICR0 __REG(0x50000000) | ||
616 | #define CICR1 __REG(0x50000004) | ||
617 | #define CICR2 __REG(0x50000008) | ||
618 | #define CICR3 __REG(0x5000000C) | ||
619 | #define CICR4 __REG(0x50000010) | ||
620 | #define CISR __REG(0x50000014) | ||
621 | #define CIFR __REG(0x50000018) | ||
622 | #define CITOR __REG(0x5000001C) | ||
623 | #define CIBR0 __REG(0x50000028) | ||
624 | #define CIBR1 __REG(0x50000030) | ||
625 | #define CIBR2 __REG(0x50000038) | ||
626 | |||
627 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | ||
628 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | ||
629 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | ||
630 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | ||
631 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | ||
632 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | ||
633 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | ||
634 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | ||
635 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | ||
636 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | ||
637 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | ||
638 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | ||
639 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | ||
640 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | ||
641 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | ||
642 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | ||
643 | |||
644 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | ||
645 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | ||
646 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | ||
647 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | ||
648 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | ||
649 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | ||
650 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | ||
651 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | ||
652 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | ||
653 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | ||
654 | |||
655 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | ||
656 | wait count mask */ | ||
657 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | ||
658 | wait count mask */ | ||
659 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | ||
660 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | ||
661 | wait count mask */ | ||
662 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | ||
663 | wait count mask */ | ||
664 | |||
665 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | ||
666 | wait count mask */ | ||
667 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | ||
668 | wait count mask */ | ||
669 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | ||
670 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | ||
671 | wait count mask */ | ||
672 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | ||
673 | |||
674 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | ||
675 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | ||
676 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | ||
677 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | ||
678 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | ||
679 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | ||
680 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | ||
681 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | ||
682 | |||
683 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | ||
684 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | ||
685 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | ||
686 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | ||
687 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | ||
688 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | ||
689 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | ||
690 | #define CISR_EOL (1 << 8) /* End of line */ | ||
691 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | ||
692 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | ||
693 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | ||
694 | #define CISR_SOF (1 << 4) /* Start of frame */ | ||
695 | #define CISR_EOF (1 << 3) /* End of frame */ | ||
696 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | ||
697 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | ||
698 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | ||
699 | |||
700 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | ||
701 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | ||
702 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | ||
703 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | ||
704 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | ||
705 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | ||
706 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | ||
707 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | ||
708 | |||
709 | #define SRAM_SIZE 0x40000 /* 4x64K */ | ||
710 | |||
711 | #define SRAM_MEM_PHYS 0x5C000000 | ||
712 | |||
713 | #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ | ||
714 | #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ | ||
715 | |||
716 | #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ | ||
717 | #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ | ||
718 | #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ | ||
719 | #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ | ||
720 | |||
721 | #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ | ||
722 | #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ | ||
723 | #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ | ||
724 | #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ | ||
725 | |||
726 | #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ | ||
727 | #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ | ||
728 | #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ | ||
729 | #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ | ||
730 | |||
731 | #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ | ||
732 | #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ | ||
733 | #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ | ||
734 | #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ | ||
735 | |||
736 | #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ | ||
737 | #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ | ||
738 | #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ | ||
739 | #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ | ||
740 | |||
741 | #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ | ||
742 | |||
743 | #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ | ||
744 | #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ | ||
745 | #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ | ||
746 | |||
747 | #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ | ||
748 | #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ | ||
749 | #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ | ||
750 | |||
751 | #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ | ||
752 | #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ | ||
753 | #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ | ||
754 | |||
755 | #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ | ||
756 | #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ | ||
757 | #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ | ||
758 | |||
759 | #endif | ||
760 | |||
761 | /* PWRMODE register M field values */ | ||
762 | |||
763 | #define PWRMODE_IDLE 0x1 | ||
764 | #define PWRMODE_STANDBY 0x2 | ||
765 | #define PWRMODE_SLEEP 0x3 | ||
766 | #define PWRMODE_DEEPSLEEP 0x7 | ||
767 | 262 | ||
768 | #endif | 263 | #endif |
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h index 6ef1dd09970b..d83393e25273 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h | |||
@@ -365,4 +365,9 @@ | |||
365 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) | 365 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) |
366 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) | 366 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) |
367 | 367 | ||
368 | /* | ||
369 | * Handy routine to set GPIO alternate functions | ||
370 | */ | ||
371 | extern int pxa_gpio_mode( int gpio_mode ); | ||
372 | |||
368 | #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ | 373 | #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 806ecfea44bf..77102d695cc7 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | |||
@@ -49,6 +49,11 @@ | |||
49 | #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ | 49 | #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ |
50 | #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ | 50 | #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ |
51 | 51 | ||
52 | #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ | ||
53 | #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ | ||
54 | #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ | ||
55 | #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ | ||
56 | |||
52 | #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ | 57 | #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ |
53 | #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ | 58 | #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ |
54 | #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ | 59 | #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ |
@@ -243,4 +248,11 @@ | |||
243 | #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ | 248 | #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ |
244 | #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ | 249 | #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ |
245 | 250 | ||
251 | /* PWRMODE register M field values */ | ||
252 | |||
253 | #define PWRMODE_IDLE 0x1 | ||
254 | #define PWRMODE_STANDBY 0x2 | ||
255 | #define PWRMODE_SLEEP 0x3 | ||
256 | #define PWRMODE_DEEPSLEEP 0x7 | ||
257 | |||
246 | #endif | 258 | #endif |
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index cbda4d35c421..6932720ba04e 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h | |||
@@ -48,6 +48,7 @@ | |||
48 | #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) | 48 | #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) |
49 | #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) | 49 | #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) |
50 | #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) | 50 | #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) |
51 | #define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT) | ||
51 | #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) | 52 | #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) |
52 | #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) | 53 | #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) |
53 | #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) | 54 | #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) |
@@ -94,6 +95,10 @@ struct pxafb_mode_info { | |||
94 | * in pxa27x and pxa3xx, initialize them to the same value or | 95 | * in pxa27x and pxa3xx, initialize them to the same value or |
95 | * the larger one will be used | 96 | * the larger one will be used |
96 | * 3. same to {rd,wr}_pulse_width | 97 | * 3. same to {rd,wr}_pulse_width |
98 | * | ||
99 | * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity | ||
100 | * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 | ||
101 | * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD | ||
97 | */ | 102 | */ |
98 | unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ | 103 | unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ |
99 | unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ | 104 | unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ |
@@ -108,6 +113,7 @@ struct pxafb_mach_info { | |||
108 | unsigned int num_modes; | 113 | unsigned int num_modes; |
109 | 114 | ||
110 | unsigned int lcd_conn; | 115 | unsigned int lcd_conn; |
116 | unsigned long video_mem_size; | ||
111 | 117 | ||
112 | u_int fixed_modes:1, | 118 | u_int fixed_modes:1, |
113 | cmap_inverse:1, | 119 | cmap_inverse:1, |
diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h new file mode 100644 index 000000000000..e41b9d202b8c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h | |||
@@ -0,0 +1,99 @@ | |||
1 | #ifndef __ASM_ARCH_REGS_AC97_H | ||
2 | #define __ASM_ARCH_REGS_AC97_H | ||
3 | |||
4 | /* | ||
5 | * AC97 Controller registers | ||
6 | */ | ||
7 | |||
8 | #define POCR __REG(0x40500000) /* PCM Out Control Register */ | ||
9 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
10 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
11 | |||
12 | #define PICR __REG(0x40500004) /* PCM In Control Register */ | ||
13 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
14 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
15 | |||
16 | #define MCCR __REG(0x40500008) /* Mic In Control Register */ | ||
17 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
18 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
19 | |||
20 | #define GCR __REG(0x4050000C) /* Global Control Register */ | ||
21 | #ifdef CONFIG_PXA3xx | ||
22 | #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ | ||
23 | #endif | ||
24 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ | ||
25 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ | ||
26 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ | ||
27 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ | ||
28 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ | ||
29 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ | ||
30 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ | ||
31 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ | ||
32 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ | ||
33 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ | ||
34 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ | ||
35 | |||
36 | #define POSR __REG(0x40500010) /* PCM Out Status Register */ | ||
37 | #define POSR_FIFOE (1 << 4) /* FIFO error */ | ||
38 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ | ||
39 | |||
40 | #define PISR __REG(0x40500014) /* PCM In Status Register */ | ||
41 | #define PISR_FIFOE (1 << 4) /* FIFO error */ | ||
42 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
43 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ | ||
44 | |||
45 | #define MCSR __REG(0x40500018) /* Mic In Status Register */ | ||
46 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ | ||
47 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
48 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ | ||
49 | |||
50 | #define GSR __REG(0x4050001C) /* Global Status Register */ | ||
51 | #define GSR_CDONE (1 << 19) /* Command Done */ | ||
52 | #define GSR_SDONE (1 << 18) /* Status Done */ | ||
53 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ | ||
54 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ | ||
55 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ | ||
56 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ | ||
57 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ | ||
58 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ | ||
59 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ | ||
60 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ | ||
61 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ | ||
62 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ | ||
63 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ | ||
64 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ | ||
65 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ | ||
66 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ | ||
67 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ | ||
68 | |||
69 | #define CAR __REG(0x40500020) /* CODEC Access Register */ | ||
70 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ | ||
71 | |||
72 | #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ | ||
73 | #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ | ||
74 | |||
75 | #define MOCR __REG(0x40500100) /* Modem Out Control Register */ | ||
76 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ | ||
77 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
78 | |||
79 | #define MICR __REG(0x40500108) /* Modem In Control Register */ | ||
80 | #define MICR_FEIE (1 << 3) /* FIFO Error */ | ||
81 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
82 | |||
83 | #define MOSR __REG(0x40500110) /* Modem Out Status Register */ | ||
84 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ | ||
85 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ | ||
86 | |||
87 | #define MISR __REG(0x40500118) /* Modem In Status Register */ | ||
88 | #define MISR_FIFOE (1 << 4) /* FIFO error */ | ||
89 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
90 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ | ||
91 | |||
92 | #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ | ||
93 | |||
94 | #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ | ||
95 | #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ | ||
96 | #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ | ||
97 | #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ | ||
98 | |||
99 | #endif /* __ASM_ARCH_REGS_AC97_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h index c689c4ea769c..f82dcea792d9 100644 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h | |||
@@ -12,27 +12,29 @@ | |||
12 | #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ | 12 | #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ |
13 | #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ | 13 | #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ |
14 | #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ | 14 | #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ |
15 | #define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ | 15 | #define LCSR (0x038) /* LCD Controller Status Register 0 */ |
16 | #define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ | 16 | #define LCSR1 (0x034) /* LCD Controller Status Register 1 */ |
17 | #define LCSR (0x038) /* LCD Controller Status Register */ | ||
18 | #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ | 17 | #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ |
19 | #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ | 18 | #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ |
20 | #define TMEDCR (0x044) /* TMED Control Register */ | 19 | #define TMEDCR (0x044) /* TMED Control Register */ |
21 | 20 | ||
21 | #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ | ||
22 | #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ | ||
23 | #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ | ||
24 | #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ | ||
25 | #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ | ||
26 | #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ | ||
27 | #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ | ||
28 | |||
29 | #define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ | ||
30 | #define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ | ||
31 | #define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ | ||
32 | #define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ | ||
33 | |||
22 | #define CMDCR (0x100) /* Command Control Register */ | 34 | #define CMDCR (0x100) /* Command Control Register */ |
23 | #define PRSR (0x104) /* Panel Read Status Register */ | 35 | #define PRSR (0x104) /* Panel Read Status Register */ |
24 | 36 | ||
25 | #define LCCR3_1BPP (0 << 24) | 37 | #define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) |
26 | #define LCCR3_2BPP (1 << 24) | ||
27 | #define LCCR3_4BPP (2 << 24) | ||
28 | #define LCCR3_8BPP (3 << 24) | ||
29 | #define LCCR3_16BPP (4 << 24) | ||
30 | #define LCCR3_18BPP (5 << 24) | ||
31 | #define LCCR3_18BPP_P (6 << 24) | ||
32 | #define LCCR3_19BPP (7 << 24) | ||
33 | #define LCCR3_19BPP_P (1 << 29) | ||
34 | #define LCCR3_24BPP ((1 << 29) | (1 << 24)) | ||
35 | #define LCCR3_25BPP ((1 << 29) | (2 << 24)) | ||
36 | 38 | ||
37 | #define LCCR3_PDFOR_0 (0 << 30) | 39 | #define LCCR3_PDFOR_0 (0 << 30) |
38 | #define LCCR3_PDFOR_1 (1 << 30) | 40 | #define LCCR3_PDFOR_1 (1 << 30) |
@@ -42,19 +44,16 @@ | |||
42 | #define LCCR4_PAL_FOR_0 (0 << 15) | 44 | #define LCCR4_PAL_FOR_0 (0 << 15) |
43 | #define LCCR4_PAL_FOR_1 (1 << 15) | 45 | #define LCCR4_PAL_FOR_1 (1 << 15) |
44 | #define LCCR4_PAL_FOR_2 (2 << 15) | 46 | #define LCCR4_PAL_FOR_2 (2 << 15) |
47 | #define LCCR4_PAL_FOR_3 (3 << 15) | ||
45 | #define LCCR4_PAL_FOR_MASK (3 << 15) | 48 | #define LCCR4_PAL_FOR_MASK (3 << 15) |
46 | 49 | ||
47 | #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ | 50 | #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ |
48 | #define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */ | ||
49 | #define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */ | ||
50 | #define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */ | ||
51 | #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ | 51 | #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ |
52 | #define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */ | 52 | #define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ |
53 | #define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */ | 53 | #define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ |
54 | #define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */ | 54 | #define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ |
55 | #define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ | ||
55 | #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ | 56 | #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ |
56 | #define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */ | ||
57 | #define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */ | ||
58 | 57 | ||
59 | #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ | 58 | #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ |
60 | #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ | 59 | #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ |
@@ -126,9 +125,6 @@ | |||
126 | #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ | 125 | #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ |
127 | #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) | 126 | #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) |
128 | 127 | ||
129 | #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ | ||
130 | #define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP))) | ||
131 | |||
132 | #define LCCR3_ACB Fld (8, 8) /* AC Bias */ | 128 | #define LCCR3_ACB Fld (8, 8) /* AC Bias */ |
133 | #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) | 129 | #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) |
134 | 130 | ||
@@ -157,8 +153,22 @@ | |||
157 | #define LCSR_RD_ST (1 << 11) /* read status */ | 153 | #define LCSR_RD_ST (1 << 11) /* read status */ |
158 | #define LCSR_CMD_INT (1 << 12) /* command interrupt */ | 154 | #define LCSR_CMD_INT (1 << 12) /* command interrupt */ |
159 | 155 | ||
156 | #define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ | ||
157 | #define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ | ||
158 | #define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ | ||
159 | #define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ | ||
160 | |||
160 | #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ | 161 | #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ |
161 | 162 | ||
163 | /* overlay control registers */ | ||
164 | #define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ | ||
165 | #define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ | ||
166 | #define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ | ||
167 | #define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ | ||
168 | #define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ | ||
169 | #define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ | ||
170 | #define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ | ||
171 | |||
162 | /* smartpanel related */ | 172 | /* smartpanel related */ |
163 | #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ | 173 | #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ |
164 | #define PRSR_A0 (1 << 8) /* Read Data Source */ | 174 | #define PRSR_A0 (1 << 8) /* Read Data Source */ |
@@ -177,4 +187,11 @@ | |||
177 | 187 | ||
178 | #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) | 188 | #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) |
179 | #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) | 189 | #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) |
190 | |||
191 | /* SMART_DELAY() is introduced for software controlled delay primitive which | ||
192 | * can be inserted between command sequences, unused command 0x6 is used here | ||
193 | * and delay ranges from 0ms ~ 255ms | ||
194 | */ | ||
195 | #define SMART_CMD_DELAY (0x6 << 9) | ||
196 | #define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) | ||
180 | #endif /* __ASM_ARCH_REGS_LCD_H */ | 197 | #endif /* __ASM_ARCH_REGS_LCD_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h new file mode 100644 index 000000000000..55aeb7fb72f6 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-uart.h | |||
@@ -0,0 +1,143 @@ | |||
1 | #ifndef __ASM_ARCH_REGS_UART_H | ||
2 | #define __ASM_ARCH_REGS_UART_H | ||
3 | |||
4 | /* | ||
5 | * UARTs | ||
6 | */ | ||
7 | |||
8 | /* Full Function UART (FFUART) */ | ||
9 | #define FFUART FFRBR | ||
10 | #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ | ||
11 | #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ | ||
12 | #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ | ||
13 | #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ | ||
14 | #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ | ||
15 | #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ | ||
16 | #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ | ||
17 | #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ | ||
18 | #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ | ||
19 | #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ | ||
20 | #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ | ||
21 | #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
22 | #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
23 | |||
24 | /* Bluetooth UART (BTUART) */ | ||
25 | #define BTUART BTRBR | ||
26 | #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ | ||
27 | #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ | ||
28 | #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ | ||
29 | #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ | ||
30 | #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ | ||
31 | #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ | ||
32 | #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ | ||
33 | #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ | ||
34 | #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ | ||
35 | #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ | ||
36 | #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ | ||
37 | #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
38 | #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
39 | |||
40 | /* Standard UART (STUART) */ | ||
41 | #define STUART STRBR | ||
42 | #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ | ||
43 | #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ | ||
44 | #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ | ||
45 | #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ | ||
46 | #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ | ||
47 | #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ | ||
48 | #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ | ||
49 | #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ | ||
50 | #define STMSR __REG(0x40700018) /* Reserved */ | ||
51 | #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ | ||
52 | #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ | ||
53 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
54 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
55 | |||
56 | /* Hardware UART (HWUART) */ | ||
57 | #define HWUART HWRBR | ||
58 | #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ | ||
59 | #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ | ||
60 | #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ | ||
61 | #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ | ||
62 | #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ | ||
63 | #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ | ||
64 | #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ | ||
65 | #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ | ||
66 | #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ | ||
67 | #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ | ||
68 | #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ | ||
69 | #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ | ||
70 | #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ | ||
71 | #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ | ||
72 | #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
73 | #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
74 | |||
75 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ | ||
76 | #define IER_UUE (1 << 6) /* UART Unit Enable */ | ||
77 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ | ||
78 | #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ | ||
79 | #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ | ||
80 | #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ | ||
81 | #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ | ||
82 | #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ | ||
83 | |||
84 | #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ | ||
85 | #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ | ||
86 | #define IIR_TOD (1 << 3) /* Time Out Detected */ | ||
87 | #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ | ||
88 | #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ | ||
89 | #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ | ||
90 | |||
91 | #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ | ||
92 | #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ | ||
93 | #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ | ||
94 | #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ | ||
95 | #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ | ||
96 | #define FCR_ITL_1 (0) | ||
97 | #define FCR_ITL_8 (FCR_ITL1) | ||
98 | #define FCR_ITL_16 (FCR_ITL2) | ||
99 | #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) | ||
100 | |||
101 | #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ | ||
102 | #define LCR_SB (1 << 6) /* Set Break */ | ||
103 | #define LCR_STKYP (1 << 5) /* Sticky Parity */ | ||
104 | #define LCR_EPS (1 << 4) /* Even Parity Select */ | ||
105 | #define LCR_PEN (1 << 3) /* Parity Enable */ | ||
106 | #define LCR_STB (1 << 2) /* Stop Bit */ | ||
107 | #define LCR_WLS1 (1 << 1) /* Word Length Select */ | ||
108 | #define LCR_WLS0 (1 << 0) /* Word Length Select */ | ||
109 | |||
110 | #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ | ||
111 | #define LSR_TEMT (1 << 6) /* Transmitter Empty */ | ||
112 | #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ | ||
113 | #define LSR_BI (1 << 4) /* Break Interrupt */ | ||
114 | #define LSR_FE (1 << 3) /* Framing Error */ | ||
115 | #define LSR_PE (1 << 2) /* Parity Error */ | ||
116 | #define LSR_OE (1 << 1) /* Overrun Error */ | ||
117 | #define LSR_DR (1 << 0) /* Data Ready */ | ||
118 | |||
119 | #define MCR_LOOP (1 << 4) | ||
120 | #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ | ||
121 | #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ | ||
122 | #define MCR_RTS (1 << 1) /* Request to Send */ | ||
123 | #define MCR_DTR (1 << 0) /* Data Terminal Ready */ | ||
124 | |||
125 | #define MSR_DCD (1 << 7) /* Data Carrier Detect */ | ||
126 | #define MSR_RI (1 << 6) /* Ring Indicator */ | ||
127 | #define MSR_DSR (1 << 5) /* Data Set Ready */ | ||
128 | #define MSR_CTS (1 << 4) /* Clear To Send */ | ||
129 | #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ | ||
130 | #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ | ||
131 | #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ | ||
132 | #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ | ||
133 | |||
134 | /* | ||
135 | * IrSR (Infrared Selection Register) | ||
136 | */ | ||
137 | #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ | ||
138 | #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ | ||
139 | #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ | ||
140 | #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ | ||
141 | #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ | ||
142 | |||
143 | #endif /* __ASM_ARCH_REGS_UART_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/include/mach/reset.h index 7b8842cfa5fc..31e6a7b6ad80 100644 --- a/arch/arm/mach-pxa/include/mach/reset.h +++ b/arch/arm/mach-pxa/include/mach/reset.h | |||
@@ -12,9 +12,8 @@ extern void clear_reset_status(unsigned int mask); | |||
12 | 12 | ||
13 | /** | 13 | /** |
14 | * init_gpio_reset() - register GPIO as reset generator | 14 | * init_gpio_reset() - register GPIO as reset generator |
15 | * | 15 | * @gpio: gpio nr |
16 | * @gpio - gpio nr | 16 | * @output: set gpio as out/low instead of input during normal work |
17 | * @output - set gpio as out/low instead of input during normal work | ||
18 | */ | 17 | */ |
19 | extern int init_gpio_reset(int gpio, int output); | 18 | extern int init_gpio_reset(int gpio, int output); |
20 | 19 | ||
diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h index b05fc6683c47..af6760a50e1a 100644 --- a/arch/arm/mach-pxa/include/mach/timex.h +++ b/arch/arm/mach-pxa/include/mach/timex.h | |||
@@ -10,6 +10,14 @@ | |||
10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | /* Various drivers are still using the constant of CLOCK_TICK_RATE, for | ||
14 | * those drivers to at least work, the definition is provided here. | ||
15 | * | ||
16 | * NOTE: this is no longer accurate when multiple processors and boards | ||
17 | * are selected, newer drivers should not depend on this any more. Use | ||
18 | * either the clocksource/clockevent or get this at run-time by calling | ||
19 | * get_clock_tick_rate() (as defined in generic.c). | ||
20 | */ | ||
13 | 21 | ||
14 | #if defined(CONFIG_PXA25x) | 22 | #if defined(CONFIG_PXA25x) |
15 | /* PXA250/210 timer base */ | 23 | /* PXA250/210 timer base */ |
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 21e3e890af98..f4b029c03957 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h | |||
@@ -10,7 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/serial_reg.h> | 12 | #include <linux/serial_reg.h> |
13 | #include <mach/pxa-regs.h> | 13 | #include <mach/regs-uart.h> |
14 | #include <asm/mach-types.h> | 14 | #include <asm/mach-types.h> |
15 | 15 | ||
16 | #define __REG(x) ((volatile unsigned long *)x) | 16 | #define __REG(x) ((volatile unsigned long *)x) |
@@ -35,7 +35,7 @@ static inline void flush(void) | |||
35 | 35 | ||
36 | static inline void arch_decomp_setup(void) | 36 | static inline void arch_decomp_setup(void) |
37 | { | 37 | { |
38 | if (machine_is_littleton()) | 38 | if (machine_is_littleton() || machine_is_intelmote2()) |
39 | UART = STUART; | 39 | UART = STUART; |
40 | } | 40 | } |
41 | 41 | ||
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index b4d00aba0e31..31da7f3c06f6 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
@@ -20,8 +20,13 @@ | |||
20 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
23 | #include <linux/gpio.h> | ||
23 | #include <linux/spi/spi.h> | 24 | #include <linux/spi/spi.h> |
24 | #include <linux/smc91x.h> | 25 | #include <linux/smc91x.h> |
26 | #include <linux/i2c.h> | ||
27 | #include <linux/leds.h> | ||
28 | #include <linux/mfd/da903x.h> | ||
29 | #include <linux/i2c/max732x.h> | ||
25 | 30 | ||
26 | #include <asm/types.h> | 31 | #include <asm/types.h> |
27 | #include <asm/setup.h> | 32 | #include <asm/setup.h> |
@@ -36,10 +41,10 @@ | |||
36 | 41 | ||
37 | #include <mach/pxa-regs.h> | 42 | #include <mach/pxa-regs.h> |
38 | #include <mach/mfp-pxa300.h> | 43 | #include <mach/mfp-pxa300.h> |
39 | #include <mach/gpio.h> | ||
40 | #include <mach/pxafb.h> | 44 | #include <mach/pxafb.h> |
41 | #include <mach/ssp.h> | 45 | #include <mach/ssp.h> |
42 | #include <mach/pxa2xx_spi.h> | 46 | #include <mach/pxa2xx_spi.h> |
47 | #include <mach/i2c.h> | ||
43 | #include <mach/pxa27x_keypad.h> | 48 | #include <mach/pxa27x_keypad.h> |
44 | #include <mach/pxa3xx_nand.h> | 49 | #include <mach/pxa3xx_nand.h> |
45 | #include <mach/littleton.h> | 50 | #include <mach/littleton.h> |
@@ -314,6 +319,73 @@ static void __init littleton_init_nand(void) | |||
314 | static inline void littleton_init_nand(void) {} | 319 | static inline void littleton_init_nand(void) {} |
315 | #endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */ | 320 | #endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */ |
316 | 321 | ||
322 | #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) | ||
323 | static struct led_info littleton_da9034_leds[] = { | ||
324 | [0] = { | ||
325 | .name = "littleton:keypad1", | ||
326 | .flags = DA9034_LED_RAMP, | ||
327 | }, | ||
328 | [1] = { | ||
329 | .name = "littleton:keypad2", | ||
330 | .flags = DA9034_LED_RAMP, | ||
331 | }, | ||
332 | [2] = { | ||
333 | .name = "littleton:vibra", | ||
334 | .flags = 0, | ||
335 | }, | ||
336 | }; | ||
337 | |||
338 | static struct da903x_subdev_info littleton_da9034_subdevs[] = { | ||
339 | { | ||
340 | .name = "da903x-led", | ||
341 | .id = DA9034_ID_LED_1, | ||
342 | .platform_data = &littleton_da9034_leds[0], | ||
343 | }, { | ||
344 | .name = "da903x-led", | ||
345 | .id = DA9034_ID_LED_2, | ||
346 | .platform_data = &littleton_da9034_leds[1], | ||
347 | }, { | ||
348 | .name = "da903x-led", | ||
349 | .id = DA9034_ID_VIBRA, | ||
350 | .platform_data = &littleton_da9034_leds[2], | ||
351 | }, { | ||
352 | .name = "da903x-backlight", | ||
353 | .id = DA9034_ID_WLED, | ||
354 | }, | ||
355 | }; | ||
356 | |||
357 | static struct da903x_platform_data littleton_da9034_info = { | ||
358 | .num_subdevs = ARRAY_SIZE(littleton_da9034_subdevs), | ||
359 | .subdevs = littleton_da9034_subdevs, | ||
360 | }; | ||
361 | |||
362 | static struct max732x_platform_data littleton_max7320_info = { | ||
363 | .gpio_base = EXT0_GPIO_BASE, | ||
364 | }; | ||
365 | |||
366 | static struct i2c_board_info littleton_i2c_info[] = { | ||
367 | [0] = { | ||
368 | .type = "da9034", | ||
369 | .addr = 0x34, | ||
370 | .platform_data = &littleton_da9034_info, | ||
371 | .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)), | ||
372 | }, | ||
373 | [1] = { | ||
374 | .type = "max7320", | ||
375 | .addr = 0x50, | ||
376 | .platform_data = &littleton_max7320_info, | ||
377 | }, | ||
378 | }; | ||
379 | |||
380 | static void __init littleton_init_i2c(void) | ||
381 | { | ||
382 | pxa_set_i2c_info(NULL); | ||
383 | i2c_register_board_info(0, ARRAY_AND_SIZE(littleton_i2c_info)); | ||
384 | } | ||
385 | #else | ||
386 | static inline void littleton_init_i2c(void) {} | ||
387 | #endif /* CONFIG_I2C_PXA || CONFIG_I2C_PXA_MODULE */ | ||
388 | |||
317 | static void __init littleton_init(void) | 389 | static void __init littleton_init(void) |
318 | { | 390 | { |
319 | /* initialize MFP configurations */ | 391 | /* initialize MFP configurations */ |
@@ -326,6 +398,7 @@ static void __init littleton_init(void) | |||
326 | platform_device_register(&smc91x_device); | 398 | platform_device_register(&smc91x_device); |
327 | 399 | ||
328 | littleton_init_spi(); | 400 | littleton_init_spi(); |
401 | littleton_init_i2c(); | ||
329 | littleton_init_lcd(); | 402 | littleton_init_lcd(); |
330 | littleton_init_keypad(); | 403 | littleton_init_keypad(); |
331 | littleton_init_nand(); | 404 | littleton_init_nand(); |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 519138bc5f85..21b821e1a60d 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
@@ -123,6 +123,10 @@ static unsigned long magician_pin_config[] __initdata = { | |||
123 | GPIO107_GPIO, /* DS1WM_IRQ */ | 123 | GPIO107_GPIO, /* DS1WM_IRQ */ |
124 | GPIO108_GPIO, /* GSM_READY */ | 124 | GPIO108_GPIO, /* GSM_READY */ |
125 | GPIO115_GPIO, /* nPEN_IRQ */ | 125 | GPIO115_GPIO, /* nPEN_IRQ */ |
126 | |||
127 | /* I2C */ | ||
128 | GPIO117_I2C_SCL, | ||
129 | GPIO118_I2C_SDA, | ||
126 | }; | 130 | }; |
127 | 131 | ||
128 | /* | 132 | /* |
@@ -332,8 +336,7 @@ static struct pxafb_mach_info toppoly_info = { | |||
332 | .modes = toppoly_modes, | 336 | .modes = toppoly_modes, |
333 | .num_modes = 1, | 337 | .num_modes = 1, |
334 | .fixed_modes = 1, | 338 | .fixed_modes = 1, |
335 | .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, | 339 | .lcd_conn = LCD_COLOR_TFT_16BPP, |
336 | .lccr3 = LCCR3_PixRsEdg, | ||
337 | .pxafb_lcd_power = toppoly_lcd_power, | 340 | .pxafb_lcd_power = toppoly_lcd_power, |
338 | }; | 341 | }; |
339 | 342 | ||
@@ -341,8 +344,8 @@ static struct pxafb_mach_info samsung_info = { | |||
341 | .modes = samsung_modes, | 344 | .modes = samsung_modes, |
342 | .num_modes = 1, | 345 | .num_modes = 1, |
343 | .fixed_modes = 1, | 346 | .fixed_modes = 1, |
344 | .lccr0 = LCCR0_LDDALT | LCCR0_Color | LCCR0_Sngl | LCCR0_Act, | 347 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |\ |
345 | .lccr3 = LCCR3_PixFlEdg, | 348 | LCD_ALTERNATE_MAPPING, |
346 | .pxafb_lcd_power = samsung_lcd_power, | 349 | .pxafb_lcd_power = samsung_lcd_power, |
347 | }; | 350 | }; |
348 | 351 | ||
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f2c7ad8f2b6b..5f224968043c 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
@@ -128,6 +128,10 @@ static unsigned long mainstone_pin_config[] = { | |||
128 | GPIO108_KP_MKOUT_5, | 128 | GPIO108_KP_MKOUT_5, |
129 | GPIO96_KP_MKOUT_6, | 129 | GPIO96_KP_MKOUT_6, |
130 | 130 | ||
131 | /* I2C */ | ||
132 | GPIO117_I2C_SCL, | ||
133 | GPIO118_I2C_SDA, | ||
134 | |||
131 | /* GPIO */ | 135 | /* GPIO */ |
132 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, | 136 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, |
133 | }; | 137 | }; |
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 2061c00c8ead..33626de8cbf6 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c | |||
@@ -38,12 +38,13 @@ struct gpio_desc { | |||
38 | unsigned valid : 1; | 38 | unsigned valid : 1; |
39 | unsigned can_wakeup : 1; | 39 | unsigned can_wakeup : 1; |
40 | unsigned keypad_gpio : 1; | 40 | unsigned keypad_gpio : 1; |
41 | unsigned dir_inverted : 1; | ||
41 | unsigned int mask; /* bit mask in PWER or PKWR */ | 42 | unsigned int mask; /* bit mask in PWER or PKWR */ |
43 | unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */ | ||
42 | unsigned long config; | 44 | unsigned long config; |
43 | }; | 45 | }; |
44 | 46 | ||
45 | static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; | 47 | static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; |
46 | static int gpio_nr; | ||
47 | 48 | ||
48 | static unsigned long gpdr_lpm[4]; | 49 | static unsigned long gpdr_lpm[4]; |
49 | 50 | ||
@@ -54,7 +55,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) | |||
54 | int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */ | 55 | int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */ |
55 | int shft = (gpio & 0xf) << 1; | 56 | int shft = (gpio & 0xf) << 1; |
56 | int fn = MFP_AF(c); | 57 | int fn = MFP_AF(c); |
57 | int dir = c & MFP_DIR_OUT; | 58 | int is_out = (c & MFP_DIR_OUT) ? 1 : 0; |
58 | 59 | ||
59 | if (fn > 3) | 60 | if (fn > 3) |
60 | return -EINVAL; | 61 | return -EINVAL; |
@@ -68,7 +69,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) | |||
68 | else | 69 | else |
69 | GAFR_U(bank) = gafr; | 70 | GAFR_U(bank) = gafr; |
70 | 71 | ||
71 | if (dir == MFP_DIR_OUT) | 72 | if (is_out ^ gpio_desc[gpio].dir_inverted) |
72 | GPDR(gpio) |= mask; | 73 | GPDR(gpio) |= mask; |
73 | else | 74 | else |
74 | GPDR(gpio) &= ~mask; | 75 | GPDR(gpio) &= ~mask; |
@@ -77,11 +78,11 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) | |||
77 | switch (c & MFP_LPM_STATE_MASK) { | 78 | switch (c & MFP_LPM_STATE_MASK) { |
78 | case MFP_LPM_DRIVE_HIGH: | 79 | case MFP_LPM_DRIVE_HIGH: |
79 | PGSR(bank) |= mask; | 80 | PGSR(bank) |= mask; |
80 | dir = MFP_DIR_OUT; | 81 | is_out = 1; |
81 | break; | 82 | break; |
82 | case MFP_LPM_DRIVE_LOW: | 83 | case MFP_LPM_DRIVE_LOW: |
83 | PGSR(bank) &= ~mask; | 84 | PGSR(bank) &= ~mask; |
84 | dir = MFP_DIR_OUT; | 85 | is_out = 1; |
85 | break; | 86 | break; |
86 | case MFP_LPM_DEFAULT: | 87 | case MFP_LPM_DEFAULT: |
87 | break; | 88 | break; |
@@ -92,7 +93,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) | |||
92 | break; | 93 | break; |
93 | } | 94 | } |
94 | 95 | ||
95 | if (dir == MFP_DIR_OUT) | 96 | if (is_out ^ gpio_desc[gpio].dir_inverted) |
96 | gpdr_lpm[bank] |= mask; | 97 | gpdr_lpm[bank] |= mask; |
97 | else | 98 | else |
98 | gpdr_lpm[bank] &= ~mask; | 99 | gpdr_lpm[bank] &= ~mask; |
@@ -106,7 +107,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) | |||
106 | return -EINVAL; | 107 | return -EINVAL; |
107 | } | 108 | } |
108 | 109 | ||
109 | if ((c & MFP_LPM_CAN_WAKEUP) && (dir == MFP_DIR_OUT)) { | 110 | if ((c & MFP_LPM_CAN_WAKEUP) && is_out) { |
110 | pr_warning("%s: output GPIO%d unable to wakeup\n", | 111 | pr_warning("%s: output GPIO%d unable to wakeup\n", |
111 | __func__, gpio); | 112 | __func__, gpio); |
112 | return -EINVAL; | 113 | return -EINVAL; |
@@ -169,7 +170,7 @@ void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm) | |||
169 | int gpio_set_wake(unsigned int gpio, unsigned int on) | 170 | int gpio_set_wake(unsigned int gpio, unsigned int on) |
170 | { | 171 | { |
171 | struct gpio_desc *d; | 172 | struct gpio_desc *d; |
172 | unsigned long c; | 173 | unsigned long c, mux_taken; |
173 | 174 | ||
174 | if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) | 175 | if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) |
175 | return -EINVAL; | 176 | return -EINVAL; |
@@ -183,9 +184,13 @@ int gpio_set_wake(unsigned int gpio, unsigned int on) | |||
183 | if (d->keypad_gpio) | 184 | if (d->keypad_gpio) |
184 | return -EINVAL; | 185 | return -EINVAL; |
185 | 186 | ||
187 | mux_taken = (PWER & d->mux_mask) & (~d->mask); | ||
188 | if (on && mux_taken) | ||
189 | return -EBUSY; | ||
190 | |||
186 | if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { | 191 | if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { |
187 | if (on) { | 192 | if (on) { |
188 | PWER |= d->mask; | 193 | PWER = (PWER & ~d->mux_mask) | d->mask; |
189 | 194 | ||
190 | if (c & MFP_LPM_EDGE_RISE) | 195 | if (c & MFP_LPM_EDGE_RISE) |
191 | PRER |= d->mask; | 196 | PRER |= d->mask; |
@@ -210,7 +215,7 @@ static void __init pxa25x_mfp_init(void) | |||
210 | { | 215 | { |
211 | int i; | 216 | int i; |
212 | 217 | ||
213 | for (i = 0; i <= 84; i++) | 218 | for (i = 0; i <= pxa_last_gpio; i++) |
214 | gpio_desc[i].valid = 1; | 219 | gpio_desc[i].valid = 1; |
215 | 220 | ||
216 | for (i = 0; i <= 15; i++) { | 221 | for (i = 0; i <= 15; i++) { |
@@ -218,7 +223,11 @@ static void __init pxa25x_mfp_init(void) | |||
218 | gpio_desc[i].mask = GPIO_bit(i); | 223 | gpio_desc[i].mask = GPIO_bit(i); |
219 | } | 224 | } |
220 | 225 | ||
221 | gpio_nr = 85; | 226 | /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the |
227 | * direction bit inverted in GPDR2. See PXA26x DM 4.1.1. | ||
228 | */ | ||
229 | for (i = 86; i <= pxa_last_gpio; i++) | ||
230 | gpio_desc[i].dir_inverted = 1; | ||
222 | } | 231 | } |
223 | #else | 232 | #else |
224 | static inline void pxa25x_mfp_init(void) {} | 233 | static inline void pxa25x_mfp_init(void) {} |
@@ -251,11 +260,27 @@ int keypad_set_wake(unsigned int on) | |||
251 | return 0; | 260 | return 0; |
252 | } | 261 | } |
253 | 262 | ||
263 | #define PWER_WEMUX2_GPIO38 (1 << 16) | ||
264 | #define PWER_WEMUX2_GPIO53 (2 << 16) | ||
265 | #define PWER_WEMUX2_GPIO40 (3 << 16) | ||
266 | #define PWER_WEMUX2_GPIO36 (4 << 16) | ||
267 | #define PWER_WEMUX2_MASK (7 << 16) | ||
268 | #define PWER_WEMUX3_GPIO31 (1 << 19) | ||
269 | #define PWER_WEMUX3_GPIO113 (2 << 19) | ||
270 | #define PWER_WEMUX3_MASK (3 << 19) | ||
271 | |||
272 | #define INIT_GPIO_DESC_MUXED(mux, gpio) \ | ||
273 | do { \ | ||
274 | gpio_desc[(gpio)].can_wakeup = 1; \ | ||
275 | gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \ | ||
276 | gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \ | ||
277 | } while (0) | ||
278 | |||
254 | static void __init pxa27x_mfp_init(void) | 279 | static void __init pxa27x_mfp_init(void) |
255 | { | 280 | { |
256 | int i, gpio; | 281 | int i, gpio; |
257 | 282 | ||
258 | for (i = 0; i <= 120; i++) { | 283 | for (i = 0; i <= pxa_last_gpio; i++) { |
259 | /* skip GPIO2, 5, 6, 7, 8, they are not | 284 | /* skip GPIO2, 5, 6, 7, 8, they are not |
260 | * valid pins allow configuration | 285 | * valid pins allow configuration |
261 | */ | 286 | */ |
@@ -286,7 +311,12 @@ static void __init pxa27x_mfp_init(void) | |||
286 | gpio_desc[35].can_wakeup = 1; | 311 | gpio_desc[35].can_wakeup = 1; |
287 | gpio_desc[35].mask = PWER_WE35; | 312 | gpio_desc[35].mask = PWER_WE35; |
288 | 313 | ||
289 | gpio_nr = 121; | 314 | INIT_GPIO_DESC_MUXED(WEMUX3, 31); |
315 | INIT_GPIO_DESC_MUXED(WEMUX3, 113); | ||
316 | INIT_GPIO_DESC_MUXED(WEMUX2, 38); | ||
317 | INIT_GPIO_DESC_MUXED(WEMUX2, 53); | ||
318 | INIT_GPIO_DESC_MUXED(WEMUX2, 40); | ||
319 | INIT_GPIO_DESC_MUXED(WEMUX2, 36); | ||
290 | } | 320 | } |
291 | #else | 321 | #else |
292 | static inline void pxa27x_mfp_init(void) {} | 322 | static inline void pxa27x_mfp_init(void) {} |
@@ -300,7 +330,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) | |||
300 | { | 330 | { |
301 | int i; | 331 | int i; |
302 | 332 | ||
303 | for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { | 333 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { |
304 | 334 | ||
305 | saved_gafr[0][i] = GAFR_L(i); | 335 | saved_gafr[0][i] = GAFR_L(i); |
306 | saved_gafr[1][i] = GAFR_U(i); | 336 | saved_gafr[1][i] = GAFR_U(i); |
@@ -315,7 +345,7 @@ static int pxa2xx_mfp_resume(struct sys_device *d) | |||
315 | { | 345 | { |
316 | int i; | 346 | int i; |
317 | 347 | ||
318 | for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { | 348 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { |
319 | GAFR_L(i) = saved_gafr[0][i]; | 349 | GAFR_L(i) = saved_gafr[0][i]; |
320 | GAFR_U(i) = saved_gafr[1][i]; | 350 | GAFR_U(i) = saved_gafr[1][i]; |
321 | GPDR(i * 32) = saved_gpdr[i]; | 351 | GPDR(i * 32) = saved_gpdr[i]; |
@@ -348,7 +378,7 @@ static int __init pxa2xx_mfp_init(void) | |||
348 | pxa27x_mfp_init(); | 378 | pxa27x_mfp_init(); |
349 | 379 | ||
350 | /* initialize gafr_run[], pgsr_lpm[] from existing values */ | 380 | /* initialize gafr_run[], pgsr_lpm[] from existing values */ |
351 | for (i = 0; i <= gpio_to_bank(gpio_nr); i++) | 381 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) |
352 | gpdr_lpm[i] = GPDR(i * 32); | 382 | gpdr_lpm[i] = GPDR(i * 32); |
353 | 383 | ||
354 | return sysdev_class_register(&pxa2xx_mfp_sysclass); | 384 | return sysdev_class_register(&pxa2xx_mfp_sysclass); |
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 782903fe9c6c..2b427e015b6f 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c | |||
@@ -34,7 +34,7 @@ | |||
34 | #include <linux/irq.h> | 34 | #include <linux/irq.h> |
35 | #include <linux/pda_power.h> | 35 | #include <linux/pda_power.h> |
36 | #include <linux/power_supply.h> | 36 | #include <linux/power_supply.h> |
37 | #include <linux/wm97xx.h> | 37 | #include <linux/wm97xx_batt.h> |
38 | #include <linux/mtd/physmap.h> | 38 | #include <linux/mtd/physmap.h> |
39 | 39 | ||
40 | #include <asm/mach-types.h> | 40 | #include <asm/mach-types.h> |
@@ -46,6 +46,9 @@ | |||
46 | #include <mach/mmc.h> | 46 | #include <mach/mmc.h> |
47 | #include <mach/udc.h> | 47 | #include <mach/udc.h> |
48 | #include <mach/pxa27x-udc.h> | 48 | #include <mach/pxa27x-udc.h> |
49 | #include <mach/i2c.h> | ||
50 | #include <mach/camera.h> | ||
51 | #include <media/soc_camera.h> | ||
49 | 52 | ||
50 | #include <mach/mioa701.h> | 53 | #include <mach/mioa701.h> |
51 | 54 | ||
@@ -54,10 +57,11 @@ | |||
54 | 57 | ||
55 | static unsigned long mioa701_pin_config[] = { | 58 | static unsigned long mioa701_pin_config[] = { |
56 | /* Mio global */ | 59 | /* Mio global */ |
57 | MIO_CFG_OUT(GPIO9_CHARGE_nEN, AF0, DRIVE_LOW), | 60 | MIO_CFG_OUT(GPIO9_CHARGE_EN, AF0, DRIVE_LOW), |
58 | MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW), | 61 | MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW), |
59 | MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH), | 62 | MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH), |
60 | MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH), | 63 | MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH), |
64 | MIO_CFG_IN(GPIO80_MAYBE_CHARGE_VDROP, AF0), | ||
61 | 65 | ||
62 | /* Backlight PWM 0 */ | 66 | /* Backlight PWM 0 */ |
63 | GPIO16_PWM0_OUT, | 67 | GPIO16_PWM0_OUT, |
@@ -74,7 +78,7 @@ static unsigned long mioa701_pin_config[] = { | |||
74 | MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW), | 78 | MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW), |
75 | 79 | ||
76 | /* USB */ | 80 | /* USB */ |
77 | MIO_CFG_IN(GPIO13_USB_DETECT, AF0), | 81 | MIO_CFG_IN(GPIO13_nUSB_DETECT, AF0), |
78 | MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW), | 82 | MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW), |
79 | 83 | ||
80 | /* LCD */ | 84 | /* LCD */ |
@@ -98,12 +102,29 @@ static unsigned long mioa701_pin_config[] = { | |||
98 | GPIO75_LCD_LCLK, | 102 | GPIO75_LCD_LCLK, |
99 | GPIO76_LCD_PCLK, | 103 | GPIO76_LCD_PCLK, |
100 | 104 | ||
105 | /* QCI */ | ||
106 | GPIO12_CIF_DD_7, | ||
107 | GPIO17_CIF_DD_6, | ||
108 | GPIO50_CIF_DD_3, | ||
109 | GPIO51_CIF_DD_2, | ||
110 | GPIO52_CIF_DD_4, | ||
111 | GPIO53_CIF_MCLK, | ||
112 | GPIO54_CIF_PCLK, | ||
113 | GPIO55_CIF_DD_1, | ||
114 | GPIO81_CIF_DD_0, | ||
115 | GPIO82_CIF_DD_5, | ||
116 | GPIO84_CIF_FV, | ||
117 | GPIO85_CIF_LV, | ||
118 | |||
101 | /* Bluetooth */ | 119 | /* Bluetooth */ |
120 | MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0), | ||
102 | GPIO44_BTUART_CTS, | 121 | GPIO44_BTUART_CTS, |
103 | GPIO42_BTUART_RXD, | 122 | GPIO42_BTUART_RXD, |
104 | GPIO45_BTUART_RTS, | 123 | GPIO45_BTUART_RTS, |
105 | GPIO43_BTUART_TXD, | 124 | GPIO43_BTUART_TXD, |
106 | MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW), | 125 | MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW), |
126 | MIO_CFG_OUT(GPIO77_BT_UNKNOWN1, AF0, DRIVE_HIGH), | ||
127 | MIO_CFG_OUT(GPIO86_BT_MAYBE_nRESET, AF0, DRIVE_HIGH), | ||
107 | 128 | ||
108 | /* GPS */ | 129 | /* GPS */ |
109 | MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW), | 130 | MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW), |
@@ -151,16 +172,16 @@ static unsigned long mioa701_pin_config[] = { | |||
151 | GPIO104_KP_MKOUT_1, | 172 | GPIO104_KP_MKOUT_1, |
152 | GPIO105_KP_MKOUT_2, | 173 | GPIO105_KP_MKOUT_2, |
153 | 174 | ||
175 | /* I2C */ | ||
176 | GPIO117_I2C_SCL, | ||
177 | GPIO118_I2C_SDA, | ||
178 | |||
154 | /* Unknown */ | 179 | /* Unknown */ |
155 | MFP_CFG_IN(GPIO14, AF0), | ||
156 | MFP_CFG_IN(GPIO20, AF0), | 180 | MFP_CFG_IN(GPIO20, AF0), |
157 | MFP_CFG_IN(GPIO21, AF0), | 181 | MFP_CFG_IN(GPIO21, AF0), |
158 | MFP_CFG_IN(GPIO33, AF0), | 182 | MFP_CFG_IN(GPIO33, AF0), |
159 | MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH), | 183 | MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH), |
160 | MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH), | 184 | MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH), |
161 | MFP_CFG_OUT(GPIO77, AF0, DRIVE_HIGH), | ||
162 | MFP_CFG_IN(GPIO80, AF0), | ||
163 | MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH), | ||
164 | MFP_CFG_IN(GPIO96, AF0), | 185 | MFP_CFG_IN(GPIO96, AF0), |
165 | MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH), | 186 | MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH), |
166 | }; | 187 | }; |
@@ -407,7 +428,7 @@ static void udc_power_command(int cmd) | |||
407 | 428 | ||
408 | static int is_usb_connected(void) | 429 | static int is_usb_connected(void) |
409 | { | 430 | { |
410 | return !!gpio_get_value(GPIO13_USB_DETECT); | 431 | return !gpio_get_value(GPIO13_nUSB_DETECT); |
411 | } | 432 | } |
412 | 433 | ||
413 | static struct pxa2xx_udc_mach_info mioa701_udc_info = { | 434 | static struct pxa2xx_udc_mach_info mioa701_udc_info = { |
@@ -659,13 +680,19 @@ static char *supplicants[] = { | |||
659 | "mioa701_battery" | 680 | "mioa701_battery" |
660 | }; | 681 | }; |
661 | 682 | ||
683 | static int is_ac_connected(void) | ||
684 | { | ||
685 | return gpio_get_value(GPIO96_AC_DETECT); | ||
686 | } | ||
687 | |||
662 | static void mioa701_set_charge(int flags) | 688 | static void mioa701_set_charge(int flags) |
663 | { | 689 | { |
664 | gpio_set_value(GPIO9_CHARGE_nEN, !flags); | 690 | gpio_set_value(GPIO9_CHARGE_EN, (flags == PDA_POWER_CHARGE_USB)); |
665 | } | 691 | } |
666 | 692 | ||
667 | static struct pda_power_pdata power_pdata = { | 693 | static struct pda_power_pdata power_pdata = { |
668 | .is_ac_online = is_usb_connected, | 694 | .is_ac_online = is_ac_connected, |
695 | .is_usb_online = is_usb_connected, | ||
669 | .set_charge = mioa701_set_charge, | 696 | .set_charge = mioa701_set_charge, |
670 | .supplied_to = supplicants, | 697 | .supplied_to = supplicants, |
671 | .num_supplicants = ARRAY_SIZE(supplicants), | 698 | .num_supplicants = ARRAY_SIZE(supplicants), |
@@ -674,8 +701,15 @@ static struct pda_power_pdata power_pdata = { | |||
674 | static struct resource power_resources[] = { | 701 | static struct resource power_resources[] = { |
675 | [0] = { | 702 | [0] = { |
676 | .name = "ac", | 703 | .name = "ac", |
677 | .start = gpio_to_irq(GPIO13_USB_DETECT), | 704 | .start = gpio_to_irq(GPIO96_AC_DETECT), |
678 | .end = gpio_to_irq(GPIO13_USB_DETECT), | 705 | .end = gpio_to_irq(GPIO96_AC_DETECT), |
706 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | | ||
707 | IORESOURCE_IRQ_LOWEDGE, | ||
708 | }, | ||
709 | [1] = { | ||
710 | .name = "usb", | ||
711 | .start = gpio_to_irq(GPIO13_nUSB_DETECT), | ||
712 | .end = gpio_to_irq(GPIO13_nUSB_DETECT), | ||
679 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | | 713 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | |
680 | IORESOURCE_IRQ_LOWEDGE, | 714 | IORESOURCE_IRQ_LOWEDGE, |
681 | }, | 715 | }, |
@@ -691,120 +725,43 @@ static struct platform_device power_dev = { | |||
691 | }, | 725 | }, |
692 | }; | 726 | }; |
693 | 727 | ||
694 | #if defined(CONFIG_PDA_POWER) && defined(CONFIG_TOUCHSCREEN_WM97XX) | 728 | static struct wm97xx_batt_info mioa701_battery_data = { |
695 | static struct wm97xx *battery_wm; | 729 | .batt_aux = WM97XX_AUX_ID1, |
696 | 730 | .temp_aux = -1, | |
697 | static enum power_supply_property battery_props[] = { | 731 | .charge_gpio = -1, |
698 | POWER_SUPPLY_PROP_STATUS, | 732 | .min_voltage = 0xc00, |
699 | POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, | 733 | .max_voltage = 0xfc0, |
700 | POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, | 734 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, |
701 | POWER_SUPPLY_PROP_VOLTAGE_NOW, | 735 | .batt_div = 1, |
702 | POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, /* Necessary for apm */ | 736 | .batt_mult = 1, |
737 | .batt_name = "mioa701_battery", | ||
703 | }; | 738 | }; |
704 | 739 | ||
705 | static int get_battery_voltage(void) | 740 | /* |
706 | { | 741 | * Camera interface |
707 | int adc = -1; | 742 | */ |
708 | 743 | struct pxacamera_platform_data mioa701_pxacamera_platform_data = { | |
709 | if (battery_wm) | 744 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | |
710 | adc = wm97xx_read_aux_adc(battery_wm, WM97XX_AUX_ID1); | 745 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, |
711 | return adc; | 746 | .mclk_10khz = 5000, |
712 | } | ||
713 | |||
714 | static int get_battery_status(struct power_supply *b) | ||
715 | { | ||
716 | int status; | ||
717 | |||
718 | if (is_usb_connected()) | ||
719 | status = POWER_SUPPLY_STATUS_CHARGING; | ||
720 | else | ||
721 | status = POWER_SUPPLY_STATUS_DISCHARGING; | ||
722 | |||
723 | return status; | ||
724 | } | ||
725 | |||
726 | static int get_property(struct power_supply *b, | ||
727 | enum power_supply_property psp, | ||
728 | union power_supply_propval *val) | ||
729 | { | ||
730 | int rc = 0; | ||
731 | |||
732 | switch (psp) { | ||
733 | case POWER_SUPPLY_PROP_STATUS: | ||
734 | val->intval = get_battery_status(b); | ||
735 | break; | ||
736 | case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: | ||
737 | val->intval = 0xfd0; | ||
738 | break; | ||
739 | case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: | ||
740 | val->intval = 0xc00; | ||
741 | break; | ||
742 | case POWER_SUPPLY_PROP_VOLTAGE_NOW: | ||
743 | val->intval = get_battery_voltage(); | ||
744 | break; | ||
745 | case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: | ||
746 | val->intval = 100; | ||
747 | break; | ||
748 | default: | ||
749 | val->intval = -1; | ||
750 | rc = -1; | ||
751 | } | ||
752 | |||
753 | return rc; | ||
754 | }; | 747 | }; |
755 | 748 | ||
756 | static struct power_supply battery_ps = { | 749 | static struct soc_camera_link iclink = { |
757 | .name = "mioa701_battery", | 750 | .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ |
758 | .type = POWER_SUPPLY_TYPE_BATTERY, | ||
759 | .get_property = get_property, | ||
760 | .properties = battery_props, | ||
761 | .num_properties = ARRAY_SIZE(battery_props), | ||
762 | }; | 751 | }; |
763 | 752 | ||
764 | static int battery_probe(struct platform_device *pdev) | 753 | /* Board I2C devices. */ |
765 | { | 754 | static struct i2c_board_info __initdata mioa701_i2c_devices[] = { |
766 | struct wm97xx *wm = platform_get_drvdata(pdev); | 755 | { |
767 | int rc; | 756 | /* Must initialize before the camera(s) */ |
768 | 757 | I2C_BOARD_INFO("mt9m111", 0x5d), | |
769 | battery_wm = wm; | 758 | .platform_data = &iclink, |
770 | |||
771 | rc = power_supply_register(NULL, &battery_ps); | ||
772 | if (rc) | ||
773 | dev_err(&pdev->dev, | ||
774 | "Could not register mioa701 battery -> %d\n", rc); | ||
775 | return rc; | ||
776 | } | ||
777 | |||
778 | static int battery_remove(struct platform_device *pdev) | ||
779 | { | ||
780 | battery_wm = NULL; | ||
781 | return 0; | ||
782 | } | ||
783 | |||
784 | static struct platform_driver mioa701_battery_driver = { | ||
785 | .driver = { | ||
786 | .name = "wm97xx-battery", | ||
787 | }, | 759 | }, |
788 | .probe = battery_probe, | ||
789 | .remove = battery_remove | ||
790 | }; | 760 | }; |
791 | 761 | ||
792 | static int __init mioa701_battery_init(void) | 762 | struct i2c_pxa_platform_data i2c_pdata = { |
793 | { | 763 | .fast_mode = 1, |
794 | int rc; | 764 | }; |
795 | |||
796 | rc = platform_driver_register(&mioa701_battery_driver); | ||
797 | if (rc) | ||
798 | printk(KERN_ERR "Could not register mioa701 battery driver\n"); | ||
799 | return rc; | ||
800 | } | ||
801 | |||
802 | #else | ||
803 | static int __init mioa701_battery_init(void) | ||
804 | { | ||
805 | return 0; | ||
806 | } | ||
807 | #endif | ||
808 | 765 | ||
809 | /* | 766 | /* |
810 | * Mio global | 767 | * Mio global |
@@ -851,17 +808,17 @@ static void mioa701_machine_exit(void); | |||
851 | static void mioa701_poweroff(void) | 808 | static void mioa701_poweroff(void) |
852 | { | 809 | { |
853 | mioa701_machine_exit(); | 810 | mioa701_machine_exit(); |
854 | gpio_set_value(GPIO18_POWEROFF, 1); | 811 | arm_machine_restart('s'); |
855 | } | 812 | } |
856 | 813 | ||
857 | static void mioa701_restart(char c) | 814 | static void mioa701_restart(char c) |
858 | { | 815 | { |
859 | mioa701_machine_exit(); | 816 | mioa701_machine_exit(); |
860 | arm_machine_restart(c); | 817 | arm_machine_restart('s'); |
861 | } | 818 | } |
862 | 819 | ||
863 | struct gpio_ress global_gpios[] = { | 820 | struct gpio_ress global_gpios[] = { |
864 | MIO_GPIO_OUT(GPIO9_CHARGE_nEN, 1, "Charger enable"), | 821 | MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"), |
865 | MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"), | 822 | MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"), |
866 | MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power") | 823 | MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power") |
867 | }; | 824 | }; |
@@ -879,12 +836,16 @@ static void __init mioa701_machine_init(void) | |||
879 | set_pxa_fb_info(&mioa701_pxafb_info); | 836 | set_pxa_fb_info(&mioa701_pxafb_info); |
880 | pxa_set_mci_info(&mioa701_mci_info); | 837 | pxa_set_mci_info(&mioa701_mci_info); |
881 | pxa_set_keypad_info(&mioa701_keypad_info); | 838 | pxa_set_keypad_info(&mioa701_keypad_info); |
839 | wm97xx_bat_set_pdata(&mioa701_battery_data); | ||
882 | udc_init(); | 840 | udc_init(); |
883 | pm_power_off = mioa701_poweroff; | 841 | pm_power_off = mioa701_poweroff; |
884 | arm_pm_restart = mioa701_restart; | 842 | arm_pm_restart = mioa701_restart; |
885 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 843 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
886 | gsm_init(); | 844 | gsm_init(); |
887 | mioa701_battery_init(); | 845 | |
846 | pxa_set_i2c_info(&i2c_pdata); | ||
847 | pxa_set_camera_info(&mioa701_pxacamera_platform_data); | ||
848 | i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); | ||
888 | } | 849 | } |
889 | 850 | ||
890 | static void mioa701_machine_exit(void) | 851 | static void mioa701_machine_exit(void) |
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index b36cec5c9eed..34841c72815f 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c | |||
@@ -55,6 +55,10 @@ static unsigned long pcm990_pin_config[] __initdata = { | |||
55 | GPIO89_USBH1_PEN, | 55 | GPIO89_USBH1_PEN, |
56 | /* PWM0 */ | 56 | /* PWM0 */ |
57 | GPIO16_PWM0_OUT, | 57 | GPIO16_PWM0_OUT, |
58 | |||
59 | /* I2C */ | ||
60 | GPIO117_I2C_SCL, | ||
61 | GPIO118_I2C_SDA, | ||
58 | }; | 62 | }; |
59 | 63 | ||
60 | /* | 64 | /* |
@@ -100,8 +104,7 @@ static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = { | |||
100 | static struct pxafb_mach_info pcm990_fbinfo __initdata = { | 104 | static struct pxafb_mach_info pcm990_fbinfo __initdata = { |
101 | .modes = &fb_info_sharp_lq084v1dg21, | 105 | .modes = &fb_info_sharp_lq084v1dg21, |
102 | .num_modes = 1, | 106 | .num_modes = 1, |
103 | .lccr0 = LCCR0_PAS, | 107 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, |
104 | .lccr3 = LCCR3_PCP, | ||
105 | .pxafb_lcd_power = pcm990_lcd_power, | 108 | .pxafb_lcd_power = pcm990_lcd_power, |
106 | }; | 109 | }; |
107 | #elif defined(CONFIG_PCM990_DISPLAY_NEC) | 110 | #elif defined(CONFIG_PCM990_DISPLAY_NEC) |
@@ -123,8 +126,7 @@ struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = { | |||
123 | static struct pxafb_mach_info pcm990_fbinfo __initdata = { | 126 | static struct pxafb_mach_info pcm990_fbinfo __initdata = { |
124 | .modes = &fb_info_nec_nl6448bc20_18d, | 127 | .modes = &fb_info_nec_nl6448bc20_18d, |
125 | .num_modes = 1, | 128 | .num_modes = 1, |
126 | .lccr0 = LCCR0_Act, | 129 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, |
127 | .lccr3 = LCCR3_PixFlEdg, | ||
128 | .pxafb_lcd_power = pcm990_lcd_power, | 130 | .pxafb_lcd_power = pcm990_lcd_power, |
129 | }; | 131 | }; |
130 | #endif | 132 | #endif |
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index a45afdf25202..f9093beba752 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/fb.h> | 20 | #include <linux/fb.h> |
21 | #include <linux/pm.h> | 21 | #include <linux/pm.h> |
22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
23 | #include <linux/mtd/physmap.h> | ||
23 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
24 | #include <linux/spi/spi.h> | 25 | #include <linux/spi/spi.h> |
25 | #include <linux/spi/ads7846.h> | 26 | #include <linux/spi/ads7846.h> |
@@ -463,10 +464,41 @@ static struct platform_device sharpsl_nand_device = { | |||
463 | .dev.platform_data = &sharpsl_nand_platform_data, | 464 | .dev.platform_data = &sharpsl_nand_platform_data, |
464 | }; | 465 | }; |
465 | 466 | ||
467 | static struct mtd_partition sharpsl_rom_parts[] = { | ||
468 | { | ||
469 | .name ="Boot PROM Filesystem", | ||
470 | .offset = 0x00120000, | ||
471 | .size = MTDPART_SIZ_FULL, | ||
472 | }, | ||
473 | }; | ||
474 | |||
475 | static struct physmap_flash_data sharpsl_rom_data = { | ||
476 | .width = 2, | ||
477 | .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), | ||
478 | .parts = sharpsl_rom_parts, | ||
479 | }; | ||
480 | |||
481 | static struct resource sharpsl_rom_resources[] = { | ||
482 | { | ||
483 | .start = 0x00000000, | ||
484 | .end = 0x007fffff, | ||
485 | .flags = IORESOURCE_MEM, | ||
486 | }, | ||
487 | }; | ||
488 | |||
489 | static struct platform_device sharpsl_rom_device = { | ||
490 | .name = "physmap-flash", | ||
491 | .id = -1, | ||
492 | .resource = sharpsl_rom_resources, | ||
493 | .num_resources = ARRAY_SIZE(sharpsl_rom_resources), | ||
494 | .dev.platform_data = &sharpsl_rom_data, | ||
495 | }; | ||
496 | |||
466 | static struct platform_device *devices[] __initdata = { | 497 | static struct platform_device *devices[] __initdata = { |
467 | &poodle_locomo_device, | 498 | &poodle_locomo_device, |
468 | &poodle_scoop_device, | 499 | &poodle_scoop_device, |
469 | &sharpsl_nand_device, | 500 | &sharpsl_nand_device, |
501 | &sharpsl_rom_device, | ||
470 | }; | 502 | }; |
471 | 503 | ||
472 | static void poodle_poweroff(void) | 504 | static void poodle_poweroff(void) |
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c index 74e2ead8cee8..3ca7ffc6904b 100644 --- a/arch/arm/mach-pxa/pwm.c +++ b/arch/arm/mach-pxa/pwm.c | |||
@@ -173,7 +173,7 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev, | |||
173 | return ERR_PTR(-ENOMEM); | 173 | return ERR_PTR(-ENOMEM); |
174 | } | 174 | } |
175 | 175 | ||
176 | pwm->clk = clk_get(&pdev->dev, "PWMCLK"); | 176 | pwm->clk = clk_get(&pdev->dev, NULL); |
177 | if (IS_ERR(pwm->clk)) { | 177 | if (IS_ERR(pwm->clk)) { |
178 | ret = PTR_ERR(pwm->clk); | 178 | ret = PTR_ERR(pwm->clk); |
179 | goto err_free; | 179 | goto err_free; |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 25d17a1dab78..6c57522e2469 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
@@ -36,12 +36,6 @@ | |||
36 | #include "devices.h" | 36 | #include "devices.h" |
37 | #include "clock.h" | 37 | #include "clock.h" |
38 | 38 | ||
39 | int cpu_is_pxa26x(void) | ||
40 | { | ||
41 | return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0); | ||
42 | } | ||
43 | EXPORT_SYMBOL_GPL(cpu_is_pxa26x); | ||
44 | |||
45 | /* | 39 | /* |
46 | * Various clock factors driven by the CCCR register. | 40 | * Various clock factors driven by the CCCR register. |
47 | */ | 41 | */ |
@@ -167,36 +161,51 @@ static const struct clkops clk_pxa25x_gpio11_ops = { | |||
167 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz | 161 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz |
168 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) | 162 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) |
169 | */ | 163 | */ |
170 | static struct clk pxa25x_hwuart_clk = | 164 | static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1); |
171 | INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) | 165 | |
172 | ; | 166 | static struct clk_lookup pxa25x_hwuart_clkreg = |
167 | INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL); | ||
173 | 168 | ||
174 | /* | 169 | /* |
175 | * PXA 2xx clock declarations. | 170 | * PXA 2xx clock declarations. |
176 | */ | 171 | */ |
177 | static struct clk pxa25x_clks[] = { | 172 | static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); |
178 | INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), | 173 | static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1); |
179 | INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), | 174 | static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1); |
180 | INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), | 175 | static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1); |
181 | INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), | 176 | static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5); |
182 | INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev), | 177 | static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); |
183 | INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL), | 178 | static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); |
184 | INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL), | 179 | static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0); |
185 | INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), | 180 | static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0); |
186 | INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), | 181 | static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0); |
187 | 182 | static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0); | |
188 | INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), | 183 | static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0); |
189 | INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), | 184 | static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0); |
190 | INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), | 185 | static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0); |
191 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev), | 186 | static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0); |
192 | INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev), | 187 | static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0); |
193 | 188 | static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0); | |
194 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), | 189 | |
195 | 190 | static struct clk_lookup pxa25x_clkregs[] = { | |
196 | /* | 191 | INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), |
197 | INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), | 192 | INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL), |
198 | */ | 193 | INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL), |
199 | INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), | 194 | INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL), |
195 | INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL), | ||
196 | INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL), | ||
197 | INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL), | ||
198 | INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL), | ||
199 | INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL), | ||
200 | INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL), | ||
201 | INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL), | ||
202 | INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL), | ||
203 | INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL), | ||
204 | INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"), | ||
205 | INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"), | ||
206 | INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), | ||
207 | INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), | ||
208 | INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), | ||
200 | }; | 209 | }; |
201 | 210 | ||
202 | #ifdef CONFIG_PM | 211 | #ifdef CONFIG_PM |
@@ -304,13 +313,21 @@ void __init pxa25x_init_irq(void) | |||
304 | pxa_init_gpio(85, pxa25x_set_wake); | 313 | pxa_init_gpio(85, pxa25x_set_wake); |
305 | } | 314 | } |
306 | 315 | ||
316 | #ifdef CONFIG_CPU_PXA26x | ||
317 | void __init pxa26x_init_irq(void) | ||
318 | { | ||
319 | pxa_init_irq(32, pxa25x_set_wake); | ||
320 | pxa_init_gpio(90, pxa25x_set_wake); | ||
321 | } | ||
322 | #endif | ||
323 | |||
307 | static struct platform_device *pxa25x_devices[] __initdata = { | 324 | static struct platform_device *pxa25x_devices[] __initdata = { |
308 | &pxa25x_device_udc, | 325 | &pxa25x_device_udc, |
309 | &pxa_device_ffuart, | 326 | &pxa_device_ffuart, |
310 | &pxa_device_btuart, | 327 | &pxa_device_btuart, |
311 | &pxa_device_stuart, | 328 | &pxa_device_stuart, |
312 | &pxa_device_i2s, | 329 | &pxa_device_i2s, |
313 | &pxa_device_rtc, | 330 | &sa1100_device_rtc, |
314 | &pxa25x_device_ssp, | 331 | &pxa25x_device_ssp, |
315 | &pxa25x_device_nssp, | 332 | &pxa25x_device_nssp, |
316 | &pxa25x_device_assp, | 333 | &pxa25x_device_assp, |
@@ -336,7 +353,7 @@ static int __init pxa25x_init(void) | |||
336 | 353 | ||
337 | reset_status = RCSR; | 354 | reset_status = RCSR; |
338 | 355 | ||
339 | clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); | 356 | clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs)); |
340 | 357 | ||
341 | if ((ret = pxa_init_dma(16))) | 358 | if ((ret = pxa_init_dma(16))) |
342 | return ret; | 359 | return ret; |
@@ -356,8 +373,8 @@ static int __init pxa25x_init(void) | |||
356 | } | 373 | } |
357 | 374 | ||
358 | /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ | 375 | /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ |
359 | if (cpu_is_pxa255() || cpu_is_pxa26x()) { | 376 | if (cpu_is_pxa255()) { |
360 | clks_register(&pxa25x_hwuart_clk, 1); | 377 | clks_register(&pxa25x_hwuart_clkreg, 1); |
361 | ret = platform_device_register(&pxa_device_hwuart); | 378 | ret = platform_device_register(&pxa_device_hwuart); |
362 | } | 379 | } |
363 | 380 | ||
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 3e4ab2279c99..411bec54fdc4 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
@@ -144,40 +144,59 @@ static const struct clkops clk_pxa27x_lcd_ops = { | |||
144 | .getrate = clk_pxa27x_lcd_getrate, | 144 | .getrate = clk_pxa27x_lcd_getrate, |
145 | }; | 145 | }; |
146 | 146 | ||
147 | static struct clk pxa27x_clks[] = { | 147 | static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); |
148 | INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), | 148 | static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); |
149 | INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), | 149 | static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); |
150 | 150 | static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1); | |
151 | INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), | 151 | static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1); |
152 | INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | 152 | static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0); |
153 | INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), | 153 | static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0); |
154 | 154 | static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5); | |
155 | INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), | 155 | static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0); |
156 | INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), | 156 | static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0); |
157 | INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa27x_device_udc.dev), | 157 | static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); |
158 | INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), | 158 | static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); |
159 | INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), | 159 | static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); |
160 | 160 | static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); | |
161 | INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), | 161 | static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); |
162 | INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), | 162 | static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); |
163 | INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), | 163 | static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); |
164 | 164 | static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); | |
165 | INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), | 165 | static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0); |
166 | INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), | 166 | static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); |
167 | INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), | 167 | static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0); |
168 | INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), | 168 | static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0); |
169 | INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), | 169 | static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); |
170 | 170 | static DEFINE_CKEN(pxa27x_im, IM, 0, 0); | |
171 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), | 171 | static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0); |
172 | INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), | 172 | |
173 | 173 | static struct clk_lookup pxa27x_clkregs[] = { | |
174 | /* | 174 | INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), |
175 | INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), | 175 | INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL), |
176 | INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), | 176 | INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL), |
177 | INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), | 177 | INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL), |
178 | INIT_CKEN("IMCLK", IM, 0, 0, NULL), | 178 | INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL), |
179 | INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), | 179 | INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL), |
180 | */ | 180 | INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL), |
181 | INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL), | ||
182 | INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL), | ||
183 | INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"), | ||
184 | INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"), | ||
185 | INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL), | ||
186 | INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL), | ||
187 | INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL), | ||
188 | INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL), | ||
189 | INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL), | ||
190 | INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL), | ||
191 | INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL), | ||
192 | INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL), | ||
193 | INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"), | ||
194 | INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"), | ||
195 | INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"), | ||
196 | INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"), | ||
197 | INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), | ||
198 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), | ||
199 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), | ||
181 | }; | 200 | }; |
182 | 201 | ||
183 | #ifdef CONFIG_PM | 202 | #ifdef CONFIG_PM |
@@ -313,38 +332,18 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on) | |||
313 | void __init pxa27x_init_irq(void) | 332 | void __init pxa27x_init_irq(void) |
314 | { | 333 | { |
315 | pxa_init_irq(34, pxa27x_set_wake); | 334 | pxa_init_irq(34, pxa27x_set_wake); |
316 | pxa_init_gpio(128, pxa27x_set_wake); | 335 | pxa_init_gpio(121, pxa27x_set_wake); |
317 | } | 336 | } |
318 | 337 | ||
319 | /* | 338 | /* |
320 | * device registration specific to PXA27x. | 339 | * device registration specific to PXA27x. |
321 | */ | 340 | */ |
322 | |||
323 | static struct resource i2c_power_resources[] = { | ||
324 | { | ||
325 | .start = 0x40f00180, | ||
326 | .end = 0x40f001a3, | ||
327 | .flags = IORESOURCE_MEM, | ||
328 | }, { | ||
329 | .start = IRQ_PWRI2C, | ||
330 | .end = IRQ_PWRI2C, | ||
331 | .flags = IORESOURCE_IRQ, | ||
332 | }, | ||
333 | }; | ||
334 | |||
335 | struct platform_device pxa27x_device_i2c_power = { | ||
336 | .name = "pxa2xx-i2c", | ||
337 | .id = 1, | ||
338 | .resource = i2c_power_resources, | ||
339 | .num_resources = ARRAY_SIZE(i2c_power_resources), | ||
340 | }; | ||
341 | |||
342 | void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) | 341 | void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
343 | { | 342 | { |
344 | local_irq_disable(); | 343 | local_irq_disable(); |
345 | PCFR |= PCFR_PI2CEN; | 344 | PCFR |= PCFR_PI2CEN; |
346 | local_irq_enable(); | 345 | local_irq_enable(); |
347 | pxa27x_device_i2c_power.dev.platform_data = info; | 346 | pxa_register_device(&pxa27x_device_i2c_power, info); |
348 | } | 347 | } |
349 | 348 | ||
350 | static struct platform_device *devices[] __initdata = { | 349 | static struct platform_device *devices[] __initdata = { |
@@ -353,8 +352,8 @@ static struct platform_device *devices[] __initdata = { | |||
353 | &pxa_device_btuart, | 352 | &pxa_device_btuart, |
354 | &pxa_device_stuart, | 353 | &pxa_device_stuart, |
355 | &pxa_device_i2s, | 354 | &pxa_device_i2s, |
355 | &sa1100_device_rtc, | ||
356 | &pxa_device_rtc, | 356 | &pxa_device_rtc, |
357 | &pxa27x_device_i2c_power, | ||
358 | &pxa27x_device_ssp1, | 357 | &pxa27x_device_ssp1, |
359 | &pxa27x_device_ssp2, | 358 | &pxa27x_device_ssp2, |
360 | &pxa27x_device_ssp3, | 359 | &pxa27x_device_ssp3, |
@@ -380,7 +379,7 @@ static int __init pxa27x_init(void) | |||
380 | 379 | ||
381 | reset_status = RCSR; | 380 | reset_status = RCSR; |
382 | 381 | ||
383 | clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); | 382 | clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); |
384 | 383 | ||
385 | if ((ret = pxa_init_dma(32))) | 384 | if ((ret = pxa_init_dma(32))) |
386 | return ret; | 385 | return ret; |
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 9adc7fc4618a..f735e58e6669 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c | |||
@@ -85,14 +85,16 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { | |||
85 | MFP_ADDR_END, | 85 | MFP_ADDR_END, |
86 | }; | 86 | }; |
87 | 87 | ||
88 | static struct clk common_clks[] = { | 88 | static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0); |
89 | PXA3xx_CKEN("NANDCLK", NAND, 156000000, 0, &pxa3xx_device_nand.dev), | 89 | |
90 | static struct clk_lookup common_clkregs[] = { | ||
91 | INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", "NANDCLK"), | ||
90 | }; | 92 | }; |
91 | 93 | ||
92 | static struct clk pxa310_clks[] = { | 94 | static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); |
93 | #ifdef CONFIG_CPU_PXA310 | 95 | |
94 | PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), | 96 | static struct clk_lookup pxa310_clkregs[] = { |
95 | #endif | 97 | INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", "MMCCLK"), |
96 | }; | 98 | }; |
97 | 99 | ||
98 | static int __init pxa300_init(void) | 100 | static int __init pxa300_init(void) |
@@ -100,12 +102,12 @@ static int __init pxa300_init(void) | |||
100 | if (cpu_is_pxa300() || cpu_is_pxa310()) { | 102 | if (cpu_is_pxa300() || cpu_is_pxa310()) { |
101 | pxa3xx_init_mfp(); | 103 | pxa3xx_init_mfp(); |
102 | pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); | 104 | pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); |
103 | clks_register(ARRAY_AND_SIZE(common_clks)); | 105 | clks_register(ARRAY_AND_SIZE(common_clkregs)); |
104 | } | 106 | } |
105 | 107 | ||
106 | if (cpu_is_pxa310()) { | 108 | if (cpu_is_pxa310()) { |
107 | pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); | 109 | pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); |
108 | clks_register(ARRAY_AND_SIZE(pxa310_clks)); | 110 | clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); |
109 | } | 111 | } |
110 | 112 | ||
111 | return 0; | 113 | return 0; |
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 016eb18f01a3..effe408c186f 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c | |||
@@ -80,8 +80,10 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { | |||
80 | MFP_ADDR_END, | 80 | MFP_ADDR_END, |
81 | }; | 81 | }; |
82 | 82 | ||
83 | static struct clk pxa320_clks[] = { | 83 | static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0); |
84 | PXA3xx_CKEN("NANDCLK", NAND, 104000000, 0, &pxa3xx_device_nand.dev), | 84 | |
85 | static struct clk_lookup pxa320_clkregs[] = { | ||
86 | INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", "NANDCLK"), | ||
85 | }; | 87 | }; |
86 | 88 | ||
87 | static int __init pxa320_init(void) | 89 | static int __init pxa320_init(void) |
@@ -89,7 +91,7 @@ static int __init pxa320_init(void) | |||
89 | if (cpu_is_pxa320()) { | 91 | if (cpu_is_pxa320()) { |
90 | pxa3xx_init_mfp(); | 92 | pxa3xx_init_mfp(); |
91 | pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); | 93 | pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); |
92 | clks_register(ARRAY_AND_SIZE(pxa320_clks)); | 94 | clks_register(ARRAY_AND_SIZE(pxa320_clkregs)); |
93 | } | 95 | } |
94 | 96 | ||
95 | return 0; | 97 | return 0; |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index b3cd5d0b0f35..490893824e78 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <mach/pm.h> | 29 | #include <mach/pm.h> |
30 | #include <mach/dma.h> | 30 | #include <mach/dma.h> |
31 | #include <mach/ssp.h> | 31 | #include <mach/ssp.h> |
32 | #include <mach/i2c.h> | ||
32 | 33 | ||
33 | #include "generic.h" | 34 | #include "generic.h" |
34 | #include "devices.h" | 35 | #include "devices.h" |
@@ -216,43 +217,58 @@ static const struct clkops clk_dummy_ops = { | |||
216 | .disable = clk_dummy_disable, | 217 | .disable = clk_dummy_disable, |
217 | }; | 218 | }; |
218 | 219 | ||
219 | static struct clk pxa3xx_clks[] = { | 220 | static struct clk clk_pxa3xx_pout = { |
220 | { | 221 | .ops = &clk_pout_ops, |
221 | .name = "CLK_POUT", | 222 | .rate = 13000000, |
222 | .ops = &clk_pout_ops, | 223 | .delay = 70, |
223 | .rate = 13000000, | 224 | }; |
224 | .delay = 70, | ||
225 | }, | ||
226 | |||
227 | /* Power I2C clock is always on */ | ||
228 | { | ||
229 | .name = "I2CCLK", | ||
230 | .ops = &clk_dummy_ops, | ||
231 | .dev = &pxa3xx_device_i2c_power.dev, | ||
232 | }, | ||
233 | |||
234 | PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), | ||
235 | PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), | ||
236 | PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), | ||
237 | |||
238 | PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), | ||
239 | PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | ||
240 | PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), | ||
241 | |||
242 | PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), | ||
243 | PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa27x_device_udc.dev), | ||
244 | PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), | ||
245 | PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), | ||
246 | 225 | ||
247 | PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), | 226 | static struct clk clk_dummy = { |
248 | PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), | 227 | .ops = &clk_dummy_ops, |
249 | PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), | 228 | }; |
250 | PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), | ||
251 | PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), | ||
252 | PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), | ||
253 | 229 | ||
254 | PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), | 230 | static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); |
255 | PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), | 231 | static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); |
232 | static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); | ||
233 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); | ||
234 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); | ||
235 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | ||
236 | static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); | ||
237 | static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); | ||
238 | static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); | ||
239 | static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); | ||
240 | static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); | ||
241 | static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); | ||
242 | static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); | ||
243 | static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); | ||
244 | static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); | ||
245 | static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); | ||
246 | static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); | ||
247 | static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); | ||
248 | |||
249 | static struct clk_lookup pxa3xx_clkregs[] = { | ||
250 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), | ||
251 | /* Power I2C clock is always on */ | ||
252 | INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL), | ||
253 | INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), | ||
254 | INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), | ||
255 | INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), | ||
256 | INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), | ||
257 | INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), | ||
258 | INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), | ||
259 | INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), | ||
260 | INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), | ||
261 | INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), | ||
262 | INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), | ||
263 | INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), | ||
264 | INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), | ||
265 | INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), | ||
266 | INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), | ||
267 | INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), | ||
268 | INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), | ||
269 | INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), | ||
270 | INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), | ||
271 | INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), | ||
256 | }; | 272 | }; |
257 | 273 | ||
258 | #ifdef CONFIG_PM | 274 | #ifdef CONFIG_PM |
@@ -529,28 +545,9 @@ void __init pxa3xx_init_irq(void) | |||
529 | * device registration specific to PXA3xx. | 545 | * device registration specific to PXA3xx. |
530 | */ | 546 | */ |
531 | 547 | ||
532 | static struct resource i2c_power_resources[] = { | ||
533 | { | ||
534 | .start = 0x40f500c0, | ||
535 | .end = 0x40f500d3, | ||
536 | .flags = IORESOURCE_MEM, | ||
537 | }, { | ||
538 | .start = IRQ_PWRI2C, | ||
539 | .end = IRQ_PWRI2C, | ||
540 | .flags = IORESOURCE_IRQ, | ||
541 | }, | ||
542 | }; | ||
543 | |||
544 | struct platform_device pxa3xx_device_i2c_power = { | ||
545 | .name = "pxa2xx-i2c", | ||
546 | .id = 1, | ||
547 | .resource = i2c_power_resources, | ||
548 | .num_resources = ARRAY_SIZE(i2c_power_resources), | ||
549 | }; | ||
550 | |||
551 | void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) | 548 | void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
552 | { | 549 | { |
553 | pxa3xx_device_i2c_power.dev.platform_data = info; | 550 | pxa_register_device(&pxa3xx_device_i2c_power, info); |
554 | } | 551 | } |
555 | 552 | ||
556 | static struct platform_device *devices[] __initdata = { | 553 | static struct platform_device *devices[] __initdata = { |
@@ -559,6 +556,7 @@ static struct platform_device *devices[] __initdata = { | |||
559 | &pxa_device_btuart, | 556 | &pxa_device_btuart, |
560 | &pxa_device_stuart, | 557 | &pxa_device_stuart, |
561 | &pxa_device_i2s, | 558 | &pxa_device_i2s, |
559 | &sa1100_device_rtc, | ||
562 | &pxa_device_rtc, | 560 | &pxa_device_rtc, |
563 | &pxa27x_device_ssp1, | 561 | &pxa27x_device_ssp1, |
564 | &pxa27x_device_ssp2, | 562 | &pxa27x_device_ssp2, |
@@ -566,7 +564,6 @@ static struct platform_device *devices[] __initdata = { | |||
566 | &pxa3xx_device_ssp4, | 564 | &pxa3xx_device_ssp4, |
567 | &pxa27x_device_pwm0, | 565 | &pxa27x_device_pwm0, |
568 | &pxa27x_device_pwm1, | 566 | &pxa27x_device_pwm1, |
569 | &pxa3xx_device_i2c_power, | ||
570 | }; | 567 | }; |
571 | 568 | ||
572 | static struct sys_device pxa3xx_sysdev[] = { | 569 | static struct sys_device pxa3xx_sysdev[] = { |
@@ -595,7 +592,7 @@ static int __init pxa3xx_init(void) | |||
595 | */ | 592 | */ |
596 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); | 593 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); |
597 | 594 | ||
598 | clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); | 595 | clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); |
599 | 596 | ||
600 | if ((ret = pxa_init_dma(32))) | 597 | if ((ret = pxa_init_dma(32))) |
601 | return ret; | 598 | return ret; |
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index e7ea91ce7f02..5d02a7325586 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c | |||
@@ -17,19 +17,44 @@ | |||
17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
20 | #include <linux/delay.h> | ||
21 | #include <linux/fb.h> | ||
22 | #include <linux/i2c.h> | ||
20 | #include <linux/smc91x.h> | 23 | #include <linux/smc91x.h> |
24 | #include <linux/mfd/da903x.h> | ||
21 | 25 | ||
22 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
23 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
24 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
25 | #include <mach/pxa3xx-regs.h> | 29 | #include <mach/pxa3xx-regs.h> |
26 | #include <mach/mfp-pxa930.h> | 30 | #include <mach/mfp-pxa930.h> |
31 | #include <mach/i2c.h> | ||
32 | #include <mach/regs-lcd.h> | ||
33 | #include <mach/pxafb.h> | ||
27 | 34 | ||
28 | #include "devices.h" | 35 | #include "devices.h" |
29 | #include "generic.h" | 36 | #include "generic.h" |
30 | 37 | ||
38 | #define GPIO_LCD_RESET (16) | ||
39 | |||
31 | /* SAAR MFP configurations */ | 40 | /* SAAR MFP configurations */ |
32 | static mfp_cfg_t saar_mfp_cfg[] __initdata = { | 41 | static mfp_cfg_t saar_mfp_cfg[] __initdata = { |
42 | /* LCD */ | ||
43 | GPIO23_LCD_DD0, | ||
44 | GPIO24_LCD_DD1, | ||
45 | GPIO25_LCD_DD2, | ||
46 | GPIO26_LCD_DD3, | ||
47 | GPIO27_LCD_DD4, | ||
48 | GPIO28_LCD_DD5, | ||
49 | GPIO29_LCD_DD6, | ||
50 | GPIO44_LCD_DD7, | ||
51 | GPIO21_LCD_CS, | ||
52 | GPIO22_LCD_VSYNC, | ||
53 | GPIO17_LCD_FCLK_RD, | ||
54 | GPIO18_LCD_LCLK_A0, | ||
55 | GPIO19_LCD_PCLK_WR, | ||
56 | GPIO16_GPIO, /* LCD reset */ | ||
57 | |||
33 | /* Ethernet */ | 58 | /* Ethernet */ |
34 | DF_nCS1_nCS3, | 59 | DF_nCS1_nCS3, |
35 | GPIO97_GPIO, | 60 | GPIO97_GPIO, |
@@ -64,12 +89,408 @@ static struct platform_device smc91x_device = { | |||
64 | }, | 89 | }, |
65 | }; | 90 | }; |
66 | 91 | ||
92 | #if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULE) | ||
93 | static uint16_t lcd_power_on[] = { | ||
94 | /* single frame */ | ||
95 | SMART_CMD_NOOP, | ||
96 | SMART_CMD(0x00), | ||
97 | SMART_DELAY(0), | ||
98 | |||
99 | SMART_CMD_NOOP, | ||
100 | SMART_CMD(0x00), | ||
101 | SMART_DELAY(0), | ||
102 | |||
103 | SMART_CMD_NOOP, | ||
104 | SMART_CMD(0x00), | ||
105 | SMART_DELAY(0), | ||
106 | |||
107 | SMART_CMD_NOOP, | ||
108 | SMART_CMD(0x00), | ||
109 | SMART_DELAY(10), | ||
110 | |||
111 | /* calibration control */ | ||
112 | SMART_CMD(0x00), | ||
113 | SMART_CMD(0xA4), | ||
114 | SMART_DAT(0x80), | ||
115 | SMART_DAT(0x01), | ||
116 | SMART_DELAY(150), | ||
117 | |||
118 | /*Power-On Init sequence*/ | ||
119 | SMART_CMD(0x00), /* output ctrl */ | ||
120 | SMART_CMD(0x01), | ||
121 | SMART_DAT(0x01), | ||
122 | SMART_DAT(0x00), | ||
123 | SMART_CMD(0x00), /* wave ctrl */ | ||
124 | SMART_CMD(0x02), | ||
125 | SMART_DAT(0x07), | ||
126 | SMART_DAT(0x00), | ||
127 | SMART_CMD(0x00), | ||
128 | SMART_CMD(0x03), /* entry mode */ | ||
129 | SMART_DAT(0xD0), | ||
130 | SMART_DAT(0x30), | ||
131 | SMART_CMD(0x00), | ||
132 | SMART_CMD(0x08), /* display ctrl 2 */ | ||
133 | SMART_DAT(0x08), | ||
134 | SMART_DAT(0x08), | ||
135 | SMART_CMD(0x00), | ||
136 | SMART_CMD(0x09), /* display ctrl 3 */ | ||
137 | SMART_DAT(0x04), | ||
138 | SMART_DAT(0x2F), | ||
139 | SMART_CMD(0x00), | ||
140 | SMART_CMD(0x0A), /* display ctrl 4 */ | ||
141 | SMART_DAT(0x00), | ||
142 | SMART_DAT(0x08), | ||
143 | SMART_CMD(0x00), | ||
144 | SMART_CMD(0x0D), /* Frame Marker position */ | ||
145 | SMART_DAT(0x00), | ||
146 | SMART_DAT(0x08), | ||
147 | SMART_CMD(0x00), | ||
148 | SMART_CMD(0x60), /* Driver output control */ | ||
149 | SMART_DAT(0x27), | ||
150 | SMART_DAT(0x00), | ||
151 | SMART_CMD(0x00), | ||
152 | SMART_CMD(0x61), /* Base image display control */ | ||
153 | SMART_DAT(0x00), | ||
154 | SMART_DAT(0x01), | ||
155 | SMART_CMD(0x00), | ||
156 | SMART_CMD(0x30), /* Y settings 30h-3Dh */ | ||
157 | SMART_DAT(0x07), | ||
158 | SMART_DAT(0x07), | ||
159 | SMART_CMD(0x00), | ||
160 | SMART_CMD(0x31), | ||
161 | SMART_DAT(0x00), | ||
162 | SMART_DAT(0x07), | ||
163 | SMART_CMD(0x00), | ||
164 | SMART_CMD(0x32), /* Timing(3), ASW HOLD=0.5CLK */ | ||
165 | SMART_DAT(0x04), | ||
166 | SMART_DAT(0x00), | ||
167 | SMART_CMD(0x00), | ||
168 | SMART_CMD(0x33), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */ | ||
169 | SMART_DAT(0x03), | ||
170 | SMART_DAT(0x03), | ||
171 | SMART_CMD(0x00), | ||
172 | SMART_CMD(0x34), | ||
173 | SMART_DAT(0x00), | ||
174 | SMART_DAT(0x00), | ||
175 | SMART_CMD(0x00), | ||
176 | SMART_CMD(0x35), | ||
177 | SMART_DAT(0x02), | ||
178 | SMART_DAT(0x05), | ||
179 | SMART_CMD(0x00), | ||
180 | SMART_CMD(0x36), | ||
181 | SMART_DAT(0x1F), | ||
182 | SMART_DAT(0x1F), | ||
183 | SMART_CMD(0x00), | ||
184 | SMART_CMD(0x37), | ||
185 | SMART_DAT(0x07), | ||
186 | SMART_DAT(0x07), | ||
187 | SMART_CMD(0x00), | ||
188 | SMART_CMD(0x38), | ||
189 | SMART_DAT(0x00), | ||
190 | SMART_DAT(0x07), | ||
191 | SMART_CMD(0x00), | ||
192 | SMART_CMD(0x39), | ||
193 | SMART_DAT(0x04), | ||
194 | SMART_DAT(0x00), | ||
195 | SMART_CMD(0x00), | ||
196 | SMART_CMD(0x3A), | ||
197 | SMART_DAT(0x03), | ||
198 | SMART_DAT(0x03), | ||
199 | SMART_CMD(0x00), | ||
200 | SMART_CMD(0x3B), | ||
201 | SMART_DAT(0x00), | ||
202 | SMART_DAT(0x00), | ||
203 | SMART_CMD(0x00), | ||
204 | SMART_CMD(0x3C), | ||
205 | SMART_DAT(0x02), | ||
206 | SMART_DAT(0x05), | ||
207 | SMART_CMD(0x00), | ||
208 | SMART_CMD(0x3D), | ||
209 | SMART_DAT(0x1F), | ||
210 | SMART_DAT(0x1F), | ||
211 | SMART_CMD(0x00), /* Display control 1 */ | ||
212 | SMART_CMD(0x07), | ||
213 | SMART_DAT(0x00), | ||
214 | SMART_DAT(0x01), | ||
215 | SMART_CMD(0x00), /* Power control 5 */ | ||
216 | SMART_CMD(0x17), | ||
217 | SMART_DAT(0x00), | ||
218 | SMART_DAT(0x01), | ||
219 | SMART_CMD(0x00), /* Power control 1 */ | ||
220 | SMART_CMD(0x10), | ||
221 | SMART_DAT(0x10), | ||
222 | SMART_DAT(0xB0), | ||
223 | SMART_CMD(0x00), /* Power control 2 */ | ||
224 | SMART_CMD(0x11), | ||
225 | SMART_DAT(0x01), | ||
226 | SMART_DAT(0x30), | ||
227 | SMART_CMD(0x00), /* Power control 3 */ | ||
228 | SMART_CMD(0x12), | ||
229 | SMART_DAT(0x01), | ||
230 | SMART_DAT(0x9E), | ||
231 | SMART_CMD(0x00), /* Power control 4 */ | ||
232 | SMART_CMD(0x13), | ||
233 | SMART_DAT(0x17), | ||
234 | SMART_DAT(0x00), | ||
235 | SMART_CMD(0x00), /* Power control 3 */ | ||
236 | SMART_CMD(0x12), | ||
237 | SMART_DAT(0x01), | ||
238 | SMART_DAT(0xBE), | ||
239 | SMART_DELAY(100), | ||
240 | |||
241 | /* display mode : 240*320 */ | ||
242 | SMART_CMD(0x00), /* RAM address set(H) 0*/ | ||
243 | SMART_CMD(0x20), | ||
244 | SMART_DAT(0x00), | ||
245 | SMART_DAT(0x00), | ||
246 | SMART_CMD(0x00), /* RAM address set(V) 4*/ | ||
247 | SMART_CMD(0x21), | ||
248 | SMART_DAT(0x00), | ||
249 | SMART_DAT(0x00), | ||
250 | SMART_CMD(0x00), /* Start of Window RAM address set(H) 8*/ | ||
251 | SMART_CMD(0x50), | ||
252 | SMART_DAT(0x00), | ||
253 | SMART_DAT(0x00), | ||
254 | SMART_CMD(0x00), /* End of Window RAM address set(H) 12*/ | ||
255 | SMART_CMD(0x51), | ||
256 | SMART_DAT(0x00), | ||
257 | SMART_DAT(0xEF), | ||
258 | SMART_CMD(0x00), /* Start of Window RAM address set(V) 16*/ | ||
259 | SMART_CMD(0x52), | ||
260 | SMART_DAT(0x00), | ||
261 | SMART_DAT(0x00), | ||
262 | SMART_CMD(0x00), /* End of Window RAM address set(V) 20*/ | ||
263 | SMART_CMD(0x53), | ||
264 | SMART_DAT(0x01), | ||
265 | SMART_DAT(0x3F), | ||
266 | SMART_CMD(0x00), /* Panel interface control 1 */ | ||
267 | SMART_CMD(0x90), | ||
268 | SMART_DAT(0x00), | ||
269 | SMART_DAT(0x1A), | ||
270 | SMART_CMD(0x00), /* Panel interface control 2 */ | ||
271 | SMART_CMD(0x92), | ||
272 | SMART_DAT(0x04), | ||
273 | SMART_DAT(0x00), | ||
274 | SMART_CMD(0x00), /* Panel interface control 3 */ | ||
275 | SMART_CMD(0x93), | ||
276 | SMART_DAT(0x00), | ||
277 | SMART_DAT(0x05), | ||
278 | SMART_DELAY(20), | ||
279 | }; | ||
280 | |||
281 | static uint16_t lcd_panel_on[] = { | ||
282 | SMART_CMD(0x00), | ||
283 | SMART_CMD(0x07), | ||
284 | SMART_DAT(0x00), | ||
285 | SMART_DAT(0x21), | ||
286 | SMART_DELAY(1), | ||
287 | |||
288 | SMART_CMD(0x00), | ||
289 | SMART_CMD(0x07), | ||
290 | SMART_DAT(0x00), | ||
291 | SMART_DAT(0x61), | ||
292 | SMART_DELAY(100), | ||
293 | |||
294 | SMART_CMD(0x00), | ||
295 | SMART_CMD(0x07), | ||
296 | SMART_DAT(0x01), | ||
297 | SMART_DAT(0x73), | ||
298 | SMART_DELAY(1), | ||
299 | }; | ||
300 | |||
301 | static uint16_t lcd_panel_off[] = { | ||
302 | SMART_CMD(0x00), | ||
303 | SMART_CMD(0x07), | ||
304 | SMART_DAT(0x00), | ||
305 | SMART_DAT(0x72), | ||
306 | SMART_DELAY(40), | ||
307 | |||
308 | SMART_CMD(0x00), | ||
309 | SMART_CMD(0x07), | ||
310 | SMART_DAT(0x00), | ||
311 | SMART_DAT(0x01), | ||
312 | SMART_DELAY(1), | ||
313 | |||
314 | SMART_CMD(0x00), | ||
315 | SMART_CMD(0x07), | ||
316 | SMART_DAT(0x00), | ||
317 | SMART_DAT(0x00), | ||
318 | SMART_DELAY(1), | ||
319 | }; | ||
320 | |||
321 | static uint16_t lcd_power_off[] = { | ||
322 | SMART_CMD(0x00), | ||
323 | SMART_CMD(0x10), | ||
324 | SMART_DAT(0x00), | ||
325 | SMART_DAT(0x80), | ||
326 | |||
327 | SMART_CMD(0x00), | ||
328 | SMART_CMD(0x11), | ||
329 | SMART_DAT(0x01), | ||
330 | SMART_DAT(0x60), | ||
331 | |||
332 | SMART_CMD(0x00), | ||
333 | SMART_CMD(0x12), | ||
334 | SMART_DAT(0x01), | ||
335 | SMART_DAT(0xAE), | ||
336 | SMART_DELAY(40), | ||
337 | |||
338 | SMART_CMD(0x00), | ||
339 | SMART_CMD(0x10), | ||
340 | SMART_DAT(0x00), | ||
341 | SMART_DAT(0x00), | ||
342 | }; | ||
343 | |||
344 | static uint16_t update_framedata[] = { | ||
345 | /* set display ram: 240*320 */ | ||
346 | SMART_CMD(0x00), /* RAM address set(H) 0*/ | ||
347 | SMART_CMD(0x20), | ||
348 | SMART_DAT(0x00), | ||
349 | SMART_DAT(0x00), | ||
350 | SMART_CMD(0x00), /* RAM address set(V) 4*/ | ||
351 | SMART_CMD(0x21), | ||
352 | SMART_DAT(0x00), | ||
353 | SMART_DAT(0x00), | ||
354 | SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */ | ||
355 | SMART_CMD(0x50), | ||
356 | SMART_DAT(0x00), | ||
357 | SMART_DAT(0x00), | ||
358 | SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */ | ||
359 | SMART_CMD(0x51), | ||
360 | SMART_DAT(0x00), | ||
361 | SMART_DAT(0xEF), | ||
362 | SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */ | ||
363 | SMART_CMD(0x52), | ||
364 | SMART_DAT(0x00), | ||
365 | SMART_DAT(0x00), | ||
366 | SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */ | ||
367 | SMART_CMD(0x53), | ||
368 | SMART_DAT(0x01), | ||
369 | SMART_DAT(0x3F), | ||
370 | |||
371 | /* wait for vsync cmd before transferring frame data */ | ||
372 | SMART_CMD_WAIT_FOR_VSYNC, | ||
373 | |||
374 | /* write ram */ | ||
375 | SMART_CMD(0x00), | ||
376 | SMART_CMD(0x22), | ||
377 | |||
378 | /* write frame data */ | ||
379 | SMART_CMD_WRITE_FRAME, | ||
380 | }; | ||
381 | |||
382 | static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var) | ||
383 | { | ||
384 | static int pin_requested = 0; | ||
385 | struct fb_info *info = container_of(var, struct fb_info, var); | ||
386 | int err; | ||
387 | |||
388 | if (!pin_requested) { | ||
389 | err = gpio_request(GPIO_LCD_RESET, "lcd reset"); | ||
390 | if (err) { | ||
391 | pr_err("failed to request gpio for LCD reset\n"); | ||
392 | return; | ||
393 | } | ||
394 | |||
395 | gpio_direction_output(GPIO_LCD_RESET, 0); | ||
396 | pin_requested = 1; | ||
397 | } | ||
398 | |||
399 | if (on) { | ||
400 | gpio_set_value(GPIO_LCD_RESET, 0); msleep(100); | ||
401 | gpio_set_value(GPIO_LCD_RESET, 1); msleep(10); | ||
402 | |||
403 | pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on)); | ||
404 | pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on)); | ||
405 | } else { | ||
406 | pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off)); | ||
407 | pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off)); | ||
408 | } | ||
409 | |||
410 | err = pxafb_smart_flush(info); | ||
411 | if (err) | ||
412 | pr_err("%s: timed out\n", __func__); | ||
413 | } | ||
414 | |||
415 | static void ltm022a97a_update(struct fb_info *info) | ||
416 | { | ||
417 | pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata)); | ||
418 | pxafb_smart_flush(info); | ||
419 | } | ||
420 | |||
421 | static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = { | ||
422 | [0] = { | ||
423 | .xres = 240, | ||
424 | .yres = 320, | ||
425 | .bpp = 16, | ||
426 | .a0csrd_set_hld = 30, | ||
427 | .a0cswr_set_hld = 30, | ||
428 | .wr_pulse_width = 30, | ||
429 | .rd_pulse_width = 30, | ||
430 | .op_hold_time = 30, | ||
431 | .cmd_inh_time = 60, | ||
432 | |||
433 | /* L_LCLK_A0 and L_LCLK_RD active low */ | ||
434 | .sync = FB_SYNC_HOR_HIGH_ACT | | ||
435 | FB_SYNC_VERT_HIGH_ACT, | ||
436 | }, | ||
437 | }; | ||
438 | |||
439 | static struct pxafb_mach_info saar_lcd_info = { | ||
440 | .modes = toshiba_ltm022a97a_modes, | ||
441 | .num_modes = 1, | ||
442 | .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL, | ||
443 | .pxafb_lcd_power = ltm022a97a_lcd_power, | ||
444 | .smart_update = ltm022a97a_update, | ||
445 | }; | ||
446 | |||
447 | static void __init saar_init_lcd(void) | ||
448 | { | ||
449 | set_pxa_fb_info(&saar_lcd_info); | ||
450 | } | ||
451 | #else | ||
452 | static inline void saar_init_lcd(void) {} | ||
453 | #endif | ||
454 | |||
455 | #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) | ||
456 | static struct da903x_subdev_info saar_da9034_subdevs[] = { | ||
457 | [0] = { | ||
458 | .name = "da903x-backlight", | ||
459 | .id = DA9034_ID_WLED, | ||
460 | }, | ||
461 | }; | ||
462 | |||
463 | static struct da903x_platform_data saar_da9034_info = { | ||
464 | .num_subdevs = ARRAY_SIZE(saar_da9034_subdevs), | ||
465 | .subdevs = saar_da9034_subdevs, | ||
466 | }; | ||
467 | |||
468 | static struct i2c_board_info saar_i2c_info[] = { | ||
469 | [0] = { | ||
470 | .type = "da9034", | ||
471 | .addr = 0x34, | ||
472 | .platform_data = &saar_da9034_info, | ||
473 | .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), | ||
474 | }, | ||
475 | }; | ||
476 | |||
477 | static void __init saar_init_i2c(void) | ||
478 | { | ||
479 | pxa_set_i2c_info(NULL); | ||
480 | i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info)); | ||
481 | } | ||
482 | #else | ||
483 | static inline void saar_init_i2c(void) {} | ||
484 | #endif | ||
67 | static void __init saar_init(void) | 485 | static void __init saar_init(void) |
68 | { | 486 | { |
69 | /* initialize MFP configurations */ | 487 | /* initialize MFP configurations */ |
70 | pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg)); | 488 | pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg)); |
71 | 489 | ||
72 | platform_device_register(&smc91x_device); | 490 | platform_device_register(&smc91x_device); |
491 | |||
492 | saar_init_i2c(); | ||
493 | saar_init_lcd(); | ||
73 | } | 494 | } |
74 | 495 | ||
75 | MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") | 496 | MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") |
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index ad346addc028..d6f6904132a6 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c | |||
@@ -8,6 +8,8 @@ | |||
8 | #include <linux/io.h> | 8 | #include <linux/io.h> |
9 | #include <linux/sysdev.h> | 9 | #include <linux/sysdev.h> |
10 | 10 | ||
11 | #include <mach/hardware.h> | ||
12 | |||
11 | #define SMEMC_PHYS_BASE (0x4A000000) | 13 | #define SMEMC_PHYS_BASE (0x4A000000) |
12 | #define SMEMC_PHYS_SIZE (0x90) | 14 | #define SMEMC_PHYS_SIZE (0x90) |
13 | 15 | ||
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 7672b09c31b9..6d447c9ce8ab 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
23 | #include <linux/leds.h> | 23 | #include <linux/leds.h> |
24 | #include <linux/mmc/host.h> | 24 | #include <linux/mmc/host.h> |
25 | #include <linux/mtd/physmap.h> | ||
25 | #include <linux/pm.h> | 26 | #include <linux/pm.h> |
26 | #include <linux/backlight.h> | 27 | #include <linux/backlight.h> |
27 | #include <linux/io.h> | 28 | #include <linux/io.h> |
@@ -123,6 +124,10 @@ static unsigned long spitz_pin_config[] __initdata = { | |||
123 | GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */ | 124 | GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */ |
124 | GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */ | 125 | GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */ |
125 | 126 | ||
127 | /* I2C */ | ||
128 | GPIO117_I2C_SCL, | ||
129 | GPIO118_I2C_SDA, | ||
130 | |||
126 | GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, | 131 | GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, |
127 | }; | 132 | }; |
128 | 133 | ||
@@ -658,11 +663,42 @@ static struct platform_device sharpsl_nand_device = { | |||
658 | }; | 663 | }; |
659 | 664 | ||
660 | 665 | ||
666 | static struct mtd_partition sharpsl_rom_parts[] = { | ||
667 | { | ||
668 | .name ="Boot PROM Filesystem", | ||
669 | .offset = 0x00140000, | ||
670 | .size = MTDPART_SIZ_FULL, | ||
671 | }, | ||
672 | }; | ||
673 | |||
674 | static struct physmap_flash_data sharpsl_rom_data = { | ||
675 | .width = 2, | ||
676 | .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), | ||
677 | .parts = sharpsl_rom_parts, | ||
678 | }; | ||
679 | |||
680 | static struct resource sharpsl_rom_resources[] = { | ||
681 | { | ||
682 | .start = 0x00000000, | ||
683 | .end = 0x007fffff, | ||
684 | .flags = IORESOURCE_MEM, | ||
685 | }, | ||
686 | }; | ||
687 | |||
688 | static struct platform_device sharpsl_rom_device = { | ||
689 | .name = "physmap-flash", | ||
690 | .id = -1, | ||
691 | .resource = sharpsl_rom_resources, | ||
692 | .num_resources = ARRAY_SIZE(sharpsl_rom_resources), | ||
693 | .dev.platform_data = &sharpsl_rom_data, | ||
694 | }; | ||
695 | |||
661 | static struct platform_device *devices[] __initdata = { | 696 | static struct platform_device *devices[] __initdata = { |
662 | &spitzscoop_device, | 697 | &spitzscoop_device, |
663 | &spitzkbd_device, | 698 | &spitzkbd_device, |
664 | &spitzled_device, | 699 | &spitzled_device, |
665 | &sharpsl_nand_device, | 700 | &sharpsl_nand_device, |
701 | &sharpsl_rom_device, | ||
666 | }; | 702 | }; |
667 | 703 | ||
668 | static void spitz_poweroff(void) | 704 | static void spitz_poweroff(void) |
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 2c31ec725688..6f42004db3ed 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c | |||
@@ -356,7 +356,7 @@ static int __devinit ssp_probe(struct platform_device *pdev, int type) | |||
356 | } | 356 | } |
357 | ssp->pdev = pdev; | 357 | ssp->pdev = pdev; |
358 | 358 | ||
359 | ssp->clk = clk_get(&pdev->dev, "SSPCLK"); | 359 | ssp->clk = clk_get(&pdev->dev, NULL); |
360 | if (IS_ERR(ssp->clk)) { | 360 | if (IS_ERR(ssp->clk)) { |
361 | ret = PTR_ERR(ssp->clk); | 361 | ret = PTR_ERR(ssp->clk); |
362 | goto err_free; | 362 | goto err_free; |
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 589d32b4fc46..58ef08a5224b 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c | |||
@@ -18,12 +18,15 @@ | |||
18 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
20 | #include <linux/smc91x.h> | 20 | #include <linux/smc91x.h> |
21 | #include <linux/pwm_backlight.h> | ||
21 | 22 | ||
22 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
23 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
25 | #include <mach/pxa3xx-regs.h> | 26 | #include <mach/pxa3xx-regs.h> |
26 | #include <mach/mfp-pxa930.h> | 27 | #include <mach/mfp-pxa930.h> |
28 | #include <mach/pxafb.h> | ||
29 | #include <mach/pxa27x_keypad.h> | ||
27 | 30 | ||
28 | #include "devices.h" | 31 | #include "devices.h" |
29 | #include "generic.h" | 32 | #include "generic.h" |
@@ -33,6 +36,45 @@ static mfp_cfg_t tavorevb_mfp_cfg[] __initdata = { | |||
33 | /* Ethernet */ | 36 | /* Ethernet */ |
34 | DF_nCS1_nCS3, | 37 | DF_nCS1_nCS3, |
35 | GPIO47_GPIO, | 38 | GPIO47_GPIO, |
39 | |||
40 | /* LCD */ | ||
41 | GPIO23_LCD_DD0, | ||
42 | GPIO24_LCD_DD1, | ||
43 | GPIO25_LCD_DD2, | ||
44 | GPIO26_LCD_DD3, | ||
45 | GPIO27_LCD_DD4, | ||
46 | GPIO28_LCD_DD5, | ||
47 | GPIO29_LCD_DD6, | ||
48 | GPIO44_LCD_DD7, | ||
49 | GPIO21_LCD_CS, | ||
50 | GPIO22_LCD_CS2, | ||
51 | |||
52 | GPIO17_LCD_FCLK_RD, | ||
53 | GPIO18_LCD_LCLK_A0, | ||
54 | GPIO19_LCD_PCLK_WR, | ||
55 | |||
56 | /* LCD Backlight */ | ||
57 | GPIO43_PWM3, /* primary backlight */ | ||
58 | GPIO32_PWM0, /* secondary backlight */ | ||
59 | |||
60 | /* Keypad */ | ||
61 | GPIO0_KP_MKIN_0, | ||
62 | GPIO2_KP_MKIN_1, | ||
63 | GPIO4_KP_MKIN_2, | ||
64 | GPIO6_KP_MKIN_3, | ||
65 | GPIO8_KP_MKIN_4, | ||
66 | GPIO10_KP_MKIN_5, | ||
67 | GPIO12_KP_MKIN_6, | ||
68 | GPIO1_KP_MKOUT_0, | ||
69 | GPIO3_KP_MKOUT_1, | ||
70 | GPIO5_KP_MKOUT_2, | ||
71 | GPIO7_KP_MKOUT_3, | ||
72 | GPIO9_KP_MKOUT_4, | ||
73 | GPIO11_KP_MKOUT_5, | ||
74 | GPIO13_KP_MKOUT_6, | ||
75 | |||
76 | GPIO14_KP_DKIN_2, | ||
77 | GPIO15_KP_DKIN_3, | ||
36 | }; | 78 | }; |
37 | 79 | ||
38 | #define TAVOREVB_ETH_PHYS (0x14000000) | 80 | #define TAVOREVB_ETH_PHYS (0x14000000) |
@@ -64,12 +106,382 @@ static struct platform_device smc91x_device = { | |||
64 | }, | 106 | }, |
65 | }; | 107 | }; |
66 | 108 | ||
109 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) | ||
110 | static unsigned int tavorevb_matrix_key_map[] = { | ||
111 | /* KEY(row, col, key_code) */ | ||
112 | KEY(0, 4, KEY_A), KEY(0, 5, KEY_B), KEY(0, 6, KEY_C), | ||
113 | KEY(1, 4, KEY_E), KEY(1, 5, KEY_F), KEY(1, 6, KEY_G), | ||
114 | KEY(2, 4, KEY_I), KEY(2, 5, KEY_J), KEY(2, 6, KEY_K), | ||
115 | KEY(3, 4, KEY_M), KEY(3, 5, KEY_N), KEY(3, 6, KEY_O), | ||
116 | KEY(4, 5, KEY_R), KEY(4, 6, KEY_S), | ||
117 | KEY(5, 4, KEY_U), KEY(5, 4, KEY_V), KEY(5, 6, KEY_W), | ||
118 | |||
119 | KEY(6, 4, KEY_Y), KEY(6, 5, KEY_Z), | ||
120 | |||
121 | KEY(0, 3, KEY_0), KEY(2, 0, KEY_1), KEY(2, 1, KEY_2), KEY(2, 2, KEY_3), | ||
122 | KEY(2, 3, KEY_4), KEY(1, 0, KEY_5), KEY(1, 1, KEY_6), KEY(1, 2, KEY_7), | ||
123 | KEY(1, 3, KEY_8), KEY(0, 2, KEY_9), | ||
124 | |||
125 | KEY(6, 6, KEY_SPACE), | ||
126 | KEY(0, 0, KEY_KPASTERISK), /* * */ | ||
127 | KEY(0, 1, KEY_KPDOT), /* # */ | ||
128 | |||
129 | KEY(4, 1, KEY_UP), | ||
130 | KEY(4, 3, KEY_DOWN), | ||
131 | KEY(4, 0, KEY_LEFT), | ||
132 | KEY(4, 2, KEY_RIGHT), | ||
133 | KEY(6, 0, KEY_HOME), | ||
134 | KEY(3, 2, KEY_END), | ||
135 | KEY(6, 1, KEY_DELETE), | ||
136 | KEY(5, 2, KEY_BACK), | ||
137 | KEY(6, 3, KEY_CAPSLOCK), /* KEY_LEFTSHIFT), */ | ||
138 | |||
139 | KEY(4, 4, KEY_ENTER), /* scroll push */ | ||
140 | KEY(6, 2, KEY_ENTER), /* keypad action */ | ||
141 | |||
142 | KEY(3, 1, KEY_SEND), | ||
143 | KEY(5, 3, KEY_RECORD), | ||
144 | KEY(5, 0, KEY_VOLUMEUP), | ||
145 | KEY(5, 1, KEY_VOLUMEDOWN), | ||
146 | |||
147 | KEY(3, 0, KEY_F22), /* soft1 */ | ||
148 | KEY(3, 3, KEY_F23), /* soft2 */ | ||
149 | }; | ||
150 | |||
151 | static struct pxa27x_keypad_platform_data tavorevb_keypad_info = { | ||
152 | .matrix_key_rows = 7, | ||
153 | .matrix_key_cols = 7, | ||
154 | .matrix_key_map = tavorevb_matrix_key_map, | ||
155 | .matrix_key_map_size = ARRAY_SIZE(tavorevb_matrix_key_map), | ||
156 | .debounce_interval = 30, | ||
157 | }; | ||
158 | |||
159 | static void __init tavorevb_init_keypad(void) | ||
160 | { | ||
161 | pxa_set_keypad_info(&tavorevb_keypad_info); | ||
162 | } | ||
163 | #else | ||
164 | static inline void tavorevb_init_keypad(void) {} | ||
165 | #endif /* CONFIG_KEYBOARD_PXA27x || CONFIG_KEYBOARD_PXA27x_MODULE */ | ||
166 | |||
167 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
168 | static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { | ||
169 | [0] = { | ||
170 | /* primary backlight */ | ||
171 | .pwm_id = 2, | ||
172 | .max_brightness = 100, | ||
173 | .dft_brightness = 100, | ||
174 | .pwm_period_ns = 100000, | ||
175 | }, | ||
176 | [1] = { | ||
177 | /* secondary backlight */ | ||
178 | .pwm_id = 0, | ||
179 | .max_brightness = 100, | ||
180 | .dft_brightness = 100, | ||
181 | .pwm_period_ns = 100000, | ||
182 | }, | ||
183 | }; | ||
184 | |||
185 | static struct platform_device tavorevb_backlight_devices[] = { | ||
186 | [0] = { | ||
187 | .name = "pwm-backlight", | ||
188 | .id = 0, | ||
189 | .dev = { | ||
190 | .platform_data = &tavorevb_backlight_data[0], | ||
191 | }, | ||
192 | }, | ||
193 | [1] = { | ||
194 | .name = "pwm-backlight", | ||
195 | .id = 1, | ||
196 | .dev = { | ||
197 | .platform_data = &tavorevb_backlight_data[1], | ||
198 | }, | ||
199 | }, | ||
200 | }; | ||
201 | |||
202 | static uint16_t panel_init[] = { | ||
203 | /* DSTB OUT */ | ||
204 | SMART_CMD(0x00), | ||
205 | SMART_CMD_NOOP, | ||
206 | SMART_DELAY(1), | ||
207 | |||
208 | SMART_CMD(0x00), | ||
209 | SMART_CMD_NOOP, | ||
210 | SMART_DELAY(1), | ||
211 | |||
212 | SMART_CMD(0x00), | ||
213 | SMART_CMD_NOOP, | ||
214 | SMART_DELAY(1), | ||
215 | |||
216 | /* STB OUT */ | ||
217 | SMART_CMD(0x00), | ||
218 | SMART_CMD(0x1D), | ||
219 | SMART_DAT(0x00), | ||
220 | SMART_DAT(0x05), | ||
221 | SMART_DELAY(1), | ||
222 | |||
223 | /* P-ON Init sequence */ | ||
224 | SMART_CMD(0x00), /* OSC ON */ | ||
225 | SMART_CMD(0x00), | ||
226 | SMART_DAT(0x00), | ||
227 | SMART_DAT(0x01), | ||
228 | SMART_CMD(0x00), | ||
229 | SMART_CMD(0x01), /* SOURCE DRIVER SHIFT DIRECTION and display RAM setting */ | ||
230 | SMART_DAT(0x01), | ||
231 | SMART_DAT(0x27), | ||
232 | SMART_CMD(0x00), | ||
233 | SMART_CMD(0x02), /* LINE INV */ | ||
234 | SMART_DAT(0x02), | ||
235 | SMART_DAT(0x00), | ||
236 | SMART_CMD(0x00), | ||
237 | SMART_CMD(0x03), /* IF mode(1) */ | ||
238 | SMART_DAT(0x01), /* 8bit smart mode(8-8),high speed write mode */ | ||
239 | SMART_DAT(0x30), | ||
240 | SMART_CMD(0x07), | ||
241 | SMART_CMD(0x00), /* RAM Write Mode */ | ||
242 | SMART_DAT(0x00), | ||
243 | SMART_DAT(0x03), | ||
244 | SMART_CMD(0x00), | ||
245 | |||
246 | /* DISPLAY Setting, 262K, fixed(NO scroll), no split screen */ | ||
247 | SMART_CMD(0x07), | ||
248 | SMART_DAT(0x40), /* 16/18/19 BPP */ | ||
249 | SMART_DAT(0x00), | ||
250 | SMART_CMD(0x00), | ||
251 | SMART_CMD(0x08), /* BP, FP Seting, BP=2H, FP=3H */ | ||
252 | SMART_DAT(0x03), | ||
253 | SMART_DAT(0x02), | ||
254 | SMART_CMD(0x00), | ||
255 | SMART_CMD(0x0C), /* IF mode(2), using internal clock & MPU */ | ||
256 | SMART_DAT(0x00), | ||
257 | SMART_DAT(0x00), | ||
258 | SMART_CMD(0x00), | ||
259 | SMART_CMD(0x0D), /* Frame setting, 1Min. Frequence, 16CLK */ | ||
260 | SMART_DAT(0x00), | ||
261 | SMART_DAT(0x10), | ||
262 | SMART_CMD(0x00), | ||
263 | SMART_CMD(0x12), /* Timing(1),ASW W=4CLK, ASW ST=1CLK */ | ||
264 | SMART_DAT(0x03), | ||
265 | SMART_DAT(0x02), | ||
266 | SMART_CMD(0x00), | ||
267 | SMART_CMD(0x13), /* Timing(2),OEV ST=0.5CLK, OEV ED=1CLK */ | ||
268 | SMART_DAT(0x01), | ||
269 | SMART_DAT(0x02), | ||
270 | SMART_CMD(0x00), | ||
271 | SMART_CMD(0x14), /* Timing(3), ASW HOLD=0.5CLK */ | ||
272 | SMART_DAT(0x00), | ||
273 | SMART_DAT(0x00), | ||
274 | SMART_CMD(0x00), | ||
275 | SMART_CMD(0x15), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */ | ||
276 | SMART_DAT(0x20), | ||
277 | SMART_DAT(0x00), | ||
278 | SMART_CMD(0x00), | ||
279 | SMART_CMD(0x1C), | ||
280 | SMART_DAT(0x00), | ||
281 | SMART_DAT(0x00), | ||
282 | SMART_CMD(0x03), | ||
283 | SMART_CMD(0x00), | ||
284 | SMART_DAT(0x04), | ||
285 | SMART_DAT(0x03), | ||
286 | SMART_CMD(0x03), | ||
287 | SMART_CMD(0x01), | ||
288 | SMART_DAT(0x03), | ||
289 | SMART_DAT(0x04), | ||
290 | SMART_CMD(0x03), | ||
291 | SMART_CMD(0x02), | ||
292 | SMART_DAT(0x04), | ||
293 | SMART_DAT(0x03), | ||
294 | SMART_CMD(0x03), | ||
295 | SMART_CMD(0x03), | ||
296 | SMART_DAT(0x03), | ||
297 | SMART_DAT(0x03), | ||
298 | SMART_CMD(0x03), | ||
299 | SMART_CMD(0x04), | ||
300 | SMART_DAT(0x01), | ||
301 | SMART_DAT(0x01), | ||
302 | SMART_CMD(0x03), | ||
303 | SMART_CMD(0x05), | ||
304 | SMART_DAT(0x00), | ||
305 | SMART_DAT(0x00), | ||
306 | SMART_CMD(0x04), | ||
307 | SMART_CMD(0x02), | ||
308 | SMART_DAT(0x00), | ||
309 | SMART_DAT(0x00), | ||
310 | SMART_CMD(0x04), | ||
311 | SMART_CMD(0x03), | ||
312 | SMART_DAT(0x01), | ||
313 | SMART_DAT(0x3F), | ||
314 | SMART_DELAY(0), | ||
315 | |||
316 | /* DISP RAM setting: 240*320 */ | ||
317 | SMART_CMD(0x04), /* HADDR, START 0 */ | ||
318 | SMART_CMD(0x06), | ||
319 | SMART_DAT(0x00), | ||
320 | SMART_DAT(0x00), /* x1,3 */ | ||
321 | SMART_CMD(0x04), /* HADDR, END 4 */ | ||
322 | SMART_CMD(0x07), | ||
323 | SMART_DAT(0x00), | ||
324 | SMART_DAT(0xEF), /* x2, 7 */ | ||
325 | SMART_CMD(0x04), /* VADDR, START 8 */ | ||
326 | SMART_CMD(0x08), | ||
327 | SMART_DAT(0x00), /* y1, 10 */ | ||
328 | SMART_DAT(0x00), /* y1, 11 */ | ||
329 | SMART_CMD(0x04), /* VADDR, END 12 */ | ||
330 | SMART_CMD(0x09), | ||
331 | SMART_DAT(0x01), /* y2, 14 */ | ||
332 | SMART_DAT(0x3F), /* y2, 15 */ | ||
333 | SMART_CMD(0x02), /* RAM ADDR SETTING 16 */ | ||
334 | SMART_CMD(0x00), | ||
335 | SMART_DAT(0x00), | ||
336 | SMART_DAT(0x00), /* x1, 19 */ | ||
337 | SMART_CMD(0x02), /* RAM ADDR SETTING 20 */ | ||
338 | SMART_CMD(0x01), | ||
339 | SMART_DAT(0x00), /* y1, 22 */ | ||
340 | SMART_DAT(0x00), /* y1, 23 */ | ||
341 | }; | ||
342 | |||
343 | static uint16_t panel_on[] = { | ||
344 | /* Power-IC ON */ | ||
345 | SMART_CMD(0x01), | ||
346 | SMART_CMD(0x02), | ||
347 | SMART_DAT(0x07), | ||
348 | SMART_DAT(0x7D), | ||
349 | SMART_CMD(0x01), | ||
350 | SMART_CMD(0x03), | ||
351 | SMART_DAT(0x00), | ||
352 | SMART_DAT(0x05), | ||
353 | SMART_CMD(0x01), | ||
354 | SMART_CMD(0x04), | ||
355 | SMART_DAT(0x00), | ||
356 | SMART_DAT(0x00), | ||
357 | SMART_CMD(0x01), | ||
358 | SMART_CMD(0x05), | ||
359 | SMART_DAT(0x00), | ||
360 | SMART_DAT(0x15), | ||
361 | SMART_CMD(0x01), | ||
362 | SMART_CMD(0x00), | ||
363 | SMART_DAT(0xC0), | ||
364 | SMART_DAT(0x10), | ||
365 | SMART_DELAY(30), | ||
366 | |||
367 | /* DISP ON */ | ||
368 | SMART_CMD(0x01), | ||
369 | SMART_CMD(0x01), | ||
370 | SMART_DAT(0x00), | ||
371 | SMART_DAT(0x01), | ||
372 | SMART_CMD(0x01), | ||
373 | SMART_CMD(0x00), | ||
374 | SMART_DAT(0xFF), | ||
375 | SMART_DAT(0xFE), | ||
376 | SMART_DELAY(150), | ||
377 | }; | ||
378 | |||
379 | static uint16_t panel_off[] = { | ||
380 | SMART_CMD(0x00), | ||
381 | SMART_CMD(0x1E), | ||
382 | SMART_DAT(0x00), | ||
383 | SMART_DAT(0x0A), | ||
384 | SMART_CMD(0x01), | ||
385 | SMART_CMD(0x00), | ||
386 | SMART_DAT(0xFF), | ||
387 | SMART_DAT(0xEE), | ||
388 | SMART_CMD(0x01), | ||
389 | SMART_CMD(0x00), | ||
390 | SMART_DAT(0xF8), | ||
391 | SMART_DAT(0x12), | ||
392 | SMART_CMD(0x01), | ||
393 | SMART_CMD(0x00), | ||
394 | SMART_DAT(0xE8), | ||
395 | SMART_DAT(0x11), | ||
396 | SMART_CMD(0x01), | ||
397 | SMART_CMD(0x00), | ||
398 | SMART_DAT(0xC0), | ||
399 | SMART_DAT(0x11), | ||
400 | SMART_CMD(0x01), | ||
401 | SMART_CMD(0x00), | ||
402 | SMART_DAT(0x40), | ||
403 | SMART_DAT(0x11), | ||
404 | SMART_CMD(0x01), | ||
405 | SMART_CMD(0x00), | ||
406 | SMART_DAT(0x00), | ||
407 | SMART_DAT(0x10), | ||
408 | }; | ||
409 | |||
410 | static uint16_t update_framedata[] = { | ||
411 | /* write ram */ | ||
412 | SMART_CMD(0x02), | ||
413 | SMART_CMD(0x02), | ||
414 | |||
415 | /* write frame data */ | ||
416 | SMART_CMD_WRITE_FRAME, | ||
417 | }; | ||
418 | |||
419 | static void ltm020d550_lcd_power(int on, struct fb_var_screeninfo *var) | ||
420 | { | ||
421 | struct fb_info *info = container_of(var, struct fb_info, var); | ||
422 | |||
423 | if (on) { | ||
424 | pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_init)); | ||
425 | pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_on)); | ||
426 | } else { | ||
427 | pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_off)); | ||
428 | } | ||
429 | |||
430 | if (pxafb_smart_flush(info)) | ||
431 | pr_err("%s: timed out\n", __func__); | ||
432 | } | ||
433 | |||
434 | static void ltm020d550_update(struct fb_info *info) | ||
435 | { | ||
436 | pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata)); | ||
437 | pxafb_smart_flush(info); | ||
438 | } | ||
439 | |||
440 | static struct pxafb_mode_info toshiba_ltm020d550_modes[] = { | ||
441 | [0] = { | ||
442 | .xres = 240, | ||
443 | .yres = 320, | ||
444 | .bpp = 16, | ||
445 | .a0csrd_set_hld = 30, | ||
446 | .a0cswr_set_hld = 30, | ||
447 | .wr_pulse_width = 30, | ||
448 | .rd_pulse_width = 170, | ||
449 | .op_hold_time = 30, | ||
450 | .cmd_inh_time = 60, | ||
451 | |||
452 | /* L_LCLK_A0 and L_LCLK_RD active low */ | ||
453 | .sync = FB_SYNC_HOR_HIGH_ACT | | ||
454 | FB_SYNC_VERT_HIGH_ACT, | ||
455 | }, | ||
456 | }; | ||
457 | |||
458 | static struct pxafb_mach_info tavorevb_lcd_info = { | ||
459 | .modes = toshiba_ltm020d550_modes, | ||
460 | .num_modes = 1, | ||
461 | .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL, | ||
462 | .pxafb_lcd_power = ltm020d550_lcd_power, | ||
463 | .smart_update = ltm020d550_update, | ||
464 | }; | ||
465 | |||
466 | static void __init tavorevb_init_lcd(void) | ||
467 | { | ||
468 | platform_device_register(&tavorevb_backlight_devices[0]); | ||
469 | platform_device_register(&tavorevb_backlight_devices[1]); | ||
470 | set_pxa_fb_info(&tavorevb_lcd_info); | ||
471 | } | ||
472 | #else | ||
473 | static inline void tavorevb_init_lcd(void) {} | ||
474 | #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */ | ||
475 | |||
67 | static void __init tavorevb_init(void) | 476 | static void __init tavorevb_init(void) |
68 | { | 477 | { |
69 | /* initialize MFP configurations */ | 478 | /* initialize MFP configurations */ |
70 | pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg)); | 479 | pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg)); |
71 | 480 | ||
72 | platform_device_register(&smc91x_device); | 481 | platform_device_register(&smc91x_device); |
482 | |||
483 | tavorevb_init_lcd(); | ||
484 | tavorevb_init_keypad(); | ||
73 | } | 485 | } |
74 | 486 | ||
75 | MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") | 487 | MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") |
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index f8a9a62959e5..95656a72268d 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c | |||
@@ -22,8 +22,8 @@ | |||
22 | #include <asm/div64.h> | 22 | #include <asm/div64.h> |
23 | #include <asm/mach/irq.h> | 23 | #include <asm/mach/irq.h> |
24 | #include <asm/mach/time.h> | 24 | #include <asm/mach/time.h> |
25 | #include <mach/hardware.h> | ||
25 | #include <mach/pxa-regs.h> | 26 | #include <mach/pxa-regs.h> |
26 | #include <asm/mach-types.h> | ||
27 | 27 | ||
28 | /* | 28 | /* |
29 | * This is PXA's sched_clock implementation. This has a resolution | 29 | * This is PXA's sched_clock implementation. This has a resolution |
@@ -122,7 +122,6 @@ static struct clock_event_device ckevt_pxa_osmr0 = { | |||
122 | .features = CLOCK_EVT_FEAT_ONESHOT, | 122 | .features = CLOCK_EVT_FEAT_ONESHOT, |
123 | .shift = 32, | 123 | .shift = 32, |
124 | .rating = 200, | 124 | .rating = 200, |
125 | .cpumask = CPU_MASK_CPU0, | ||
126 | .set_next_event = pxa_osmr0_set_next_event, | 125 | .set_next_event = pxa_osmr0_set_next_event, |
127 | .set_mode = pxa_osmr0_set_mode, | 126 | .set_mode = pxa_osmr0_set_mode, |
128 | }; | 127 | }; |
@@ -150,18 +149,11 @@ static struct irqaction pxa_ost0_irq = { | |||
150 | 149 | ||
151 | static void __init pxa_timer_init(void) | 150 | static void __init pxa_timer_init(void) |
152 | { | 151 | { |
153 | unsigned long clock_tick_rate; | 152 | unsigned long clock_tick_rate = get_clock_tick_rate(); |
154 | 153 | ||
155 | OIER = 0; | 154 | OIER = 0; |
156 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; | 155 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; |
157 | 156 | ||
158 | if (cpu_is_pxa25x()) | ||
159 | clock_tick_rate = 3686400; | ||
160 | else if (machine_is_mainstone()) | ||
161 | clock_tick_rate = 3249600; | ||
162 | else | ||
163 | clock_tick_rate = 3250000; | ||
164 | |||
165 | set_oscr2ns_scale(clock_tick_rate); | 157 | set_oscr2ns_scale(clock_tick_rate); |
166 | 158 | ||
167 | ckevt_pxa_osmr0.mult = | 159 | ckevt_pxa_osmr0.mult = |
@@ -170,6 +162,7 @@ static void __init pxa_timer_init(void) | |||
170 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); | 162 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); |
171 | ckevt_pxa_osmr0.min_delta_ns = | 163 | ckevt_pxa_osmr0.min_delta_ns = |
172 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; | 164 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; |
165 | ckevt_pxa_osmr0.cpumask = cpumask_of(0); | ||
173 | 166 | ||
174 | cksrc_pxa_oscr0.mult = | 167 | cksrc_pxa_oscr0.mult = |
175 | clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); | 168 | clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 224897a67d15..3332e5d0356c 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/mfd/tmio.h> | 25 | #include <linux/mfd/tmio.h> |
26 | #include <linux/mtd/nand.h> | 26 | #include <linux/mtd/nand.h> |
27 | #include <linux/mtd/partitions.h> | 27 | #include <linux/mtd/partitions.h> |
28 | #include <linux/mtd/physmap.h> | ||
28 | #include <linux/pm.h> | 29 | #include <linux/pm.h> |
29 | #include <linux/gpio_keys.h> | 30 | #include <linux/gpio_keys.h> |
30 | #include <linux/input.h> | 31 | #include <linux/input.h> |
@@ -733,6 +734,45 @@ static void tosa_tc6393xb_teardown(struct platform_device *dev) | |||
733 | gpio_free(TOSA_GPIO_CARD_VCC_ON); | 734 | gpio_free(TOSA_GPIO_CARD_VCC_ON); |
734 | } | 735 | } |
735 | 736 | ||
737 | #ifdef CONFIG_MFD_TC6393XB | ||
738 | static struct fb_videomode tosa_tc6393xb_lcd_mode[] = { | ||
739 | { | ||
740 | .xres = 480, | ||
741 | .yres = 640, | ||
742 | .pixclock = 0x002cdf00,/* PLL divisor */ | ||
743 | .left_margin = 0x004c, | ||
744 | .right_margin = 0x005b, | ||
745 | .upper_margin = 0x0001, | ||
746 | .lower_margin = 0x000d, | ||
747 | .hsync_len = 0x0002, | ||
748 | .vsync_len = 0x0001, | ||
749 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
750 | .vmode = FB_VMODE_NONINTERLACED, | ||
751 | },{ | ||
752 | .xres = 240, | ||
753 | .yres = 320, | ||
754 | .pixclock = 0x00e7f203,/* PLL divisor */ | ||
755 | .left_margin = 0x0024, | ||
756 | .right_margin = 0x002f, | ||
757 | .upper_margin = 0x0001, | ||
758 | .lower_margin = 0x000d, | ||
759 | .hsync_len = 0x0002, | ||
760 | .vsync_len = 0x0001, | ||
761 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
762 | .vmode = FB_VMODE_NONINTERLACED, | ||
763 | } | ||
764 | }; | ||
765 | |||
766 | static struct tmio_fb_data tosa_tc6393xb_fb_config = { | ||
767 | .lcd_set_power = tc6393xb_lcd_set_power, | ||
768 | .lcd_mode = tc6393xb_lcd_mode, | ||
769 | .num_modes = ARRAY_SIZE(tosa_tc6393xb_lcd_mode), | ||
770 | .modes = &tosa_tc6393xb_lcd_mode[0], | ||
771 | .height = 82, | ||
772 | .width = 60, | ||
773 | }; | ||
774 | #endif | ||
775 | |||
736 | static struct tc6393xb_platform_data tosa_tc6393xb_data = { | 776 | static struct tc6393xb_platform_data tosa_tc6393xb_data = { |
737 | .scr_pll2cr = 0x0cc1, | 777 | .scr_pll2cr = 0x0cc1, |
738 | .scr_gper = 0x3300, | 778 | .scr_gper = 0x3300, |
@@ -748,6 +788,9 @@ static struct tc6393xb_platform_data tosa_tc6393xb_data = { | |||
748 | .resume = tosa_tc6393xb_resume, | 788 | .resume = tosa_tc6393xb_resume, |
749 | 789 | ||
750 | .nand_data = &tosa_tc6393xb_nand_config, | 790 | .nand_data = &tosa_tc6393xb_nand_config, |
791 | #ifdef CONFIG_MFD_TC6393XB | ||
792 | .fb_data = &tosa_tc6393xb_fb_config, | ||
793 | #endif | ||
751 | 794 | ||
752 | .resume_restore = 1, | 795 | .resume_restore = 1, |
753 | }; | 796 | }; |
@@ -789,6 +832,36 @@ static struct spi_board_info spi_board_info[] __initdata = { | |||
789 | }, | 832 | }, |
790 | }; | 833 | }; |
791 | 834 | ||
835 | static struct mtd_partition sharpsl_rom_parts[] = { | ||
836 | { | ||
837 | .name ="Boot PROM Filesystem", | ||
838 | .offset = 0x00160000, | ||
839 | .size = MTDPART_SIZ_FULL, | ||
840 | }, | ||
841 | }; | ||
842 | |||
843 | static struct physmap_flash_data sharpsl_rom_data = { | ||
844 | .width = 2, | ||
845 | .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), | ||
846 | .parts = sharpsl_rom_parts, | ||
847 | }; | ||
848 | |||
849 | static struct resource sharpsl_rom_resources[] = { | ||
850 | { | ||
851 | .start = 0x00000000, | ||
852 | .end = 0x007fffff, | ||
853 | .flags = IORESOURCE_MEM, | ||
854 | }, | ||
855 | }; | ||
856 | |||
857 | static struct platform_device sharpsl_rom_device = { | ||
858 | .name = "physmap-flash", | ||
859 | .id = -1, | ||
860 | .resource = sharpsl_rom_resources, | ||
861 | .num_resources = ARRAY_SIZE(sharpsl_rom_resources), | ||
862 | .dev.platform_data = &sharpsl_rom_data, | ||
863 | }; | ||
864 | |||
792 | static struct platform_device *devices[] __initdata = { | 865 | static struct platform_device *devices[] __initdata = { |
793 | &tosascoop_device, | 866 | &tosascoop_device, |
794 | &tosascoop_jc_device, | 867 | &tosascoop_jc_device, |
@@ -798,6 +871,7 @@ static struct platform_device *devices[] __initdata = { | |||
798 | &tosa_gpio_keys_device, | 871 | &tosa_gpio_keys_device, |
799 | &tosaled_device, | 872 | &tosaled_device, |
800 | &tosa_bt_device, | 873 | &tosa_bt_device, |
874 | &sharpsl_rom_device, | ||
801 | }; | 875 | }; |
802 | 876 | ||
803 | static void tosa_poweroff(void) | 877 | static void tosa_poweroff(void) |
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 813804433466..218d2001f1df 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/gpio.h> | ||
21 | #include <linux/pwm_backlight.h> | 22 | #include <linux/pwm_backlight.h> |
22 | #include <linux/smc91x.h> | 23 | #include <linux/smc91x.h> |
23 | 24 | ||
@@ -25,7 +26,6 @@ | |||
25 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
27 | #include <mach/audio.h> | 28 | #include <mach/audio.h> |
28 | #include <mach/gpio.h> | ||
29 | #include <mach/pxafb.h> | 29 | #include <mach/pxafb.h> |
30 | #include <mach/zylonite.h> | 30 | #include <mach/zylonite.h> |
31 | #include <mach/mmc.h> | 31 | #include <mach/mmc.h> |
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 0f244744daae..28e4e623780b 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c | |||
@@ -16,8 +16,8 @@ | |||
16 | #include <linux/module.h> | 16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/gpio.h> | ||
19 | 20 | ||
20 | #include <mach/gpio.h> | ||
21 | #include <mach/mfp-pxa320.h> | 21 | #include <mach/mfp-pxa320.h> |
22 | #include <mach/zylonite.h> | 22 | #include <mach/zylonite.h> |
23 | 23 | ||