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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 19:06:58 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 19:06:58 -0400 |
commit | 85082fd7cbe3173198aac0eb5e85ab1edcc6352c (patch) | |
tree | edbc09b7945994f78668d218fa02e991c3b3b365 /arch/arm/mach-pxa/standby.S | |
parent | 666484f0250db2e016948d63b3ef33e202e3b8d0 (diff) | |
parent | 53ffe3b440aa85af6fc4eda09b2d44bcdd312d4d (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (241 commits)
[ARM] 5171/1: ep93xx: fix compilation of modules using clocks
[ARM] 5133/2: at91sam9g20 defconfig file
[ARM] 5130/4: Support for the at91sam9g20
[ARM] 5160/1: IOP3XX: gpio/gpiolib support
[ARM] at91: Fix NAND FLASH timings for at91sam9x evaluation kits.
[ARM] 5084/1: zylonite: Register AC97 device
[ARM] 5085/2: PXA: Move AC97 over to the new central device declaration model
[ARM] 5120/1: pxa: correct platform driver names for PXA25x and PXA27x UDC drivers
[ARM] 5147/1: pxaficp_ir: drop pxa_gpio_mode calls, as pin setting
[ARM] 5145/1: PXA2xx: provide api to control IrDA pins state
[ARM] 5144/1: pxaficp_ir: cleanup includes
[ARM] pxa: remove pxa_set_cken()
[ARM] pxa: allow clk aliases
[ARM] Feroceon: don't disable BPU on boot
[ARM] Orion: LED support for HP mv2120
[ARM] Orion: add RD88F5181L-FXO support
[ARM] Orion: add RD88F5181L-GE support
[ARM] Orion: add Netgear WNR854T support
[ARM] s3c2410_defconfig: update for current build
[ARM] Acer n30: Minor style and indentation fixes.
...
Diffstat (limited to 'arch/arm/mach-pxa/standby.S')
-rw-r--r-- | arch/arm/mach-pxa/standby.S | 83 |
1 files changed, 42 insertions, 41 deletions
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S index 167412e6bec8..40bb70eff3fe 100644 --- a/arch/arm/mach-pxa/standby.S +++ b/arch/arm/mach-pxa/standby.S | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
15 | 15 | ||
16 | #include <asm/arch/pxa-regs.h> | 16 | #include <asm/arch/pxa-regs.h> |
17 | #include <asm/arch/pxa2xx-regs.h> | ||
17 | 18 | ||
18 | .text | 19 | .text |
19 | 20 | ||
@@ -35,20 +36,20 @@ ENTRY(pxa_cpu_standby) | |||
35 | 36 | ||
36 | #ifdef CONFIG_PXA3xx | 37 | #ifdef CONFIG_PXA3xx |
37 | 38 | ||
38 | #define MDCNFG 0x0000 | 39 | #define PXA3_MDCNFG 0x0000 |
39 | #define MDCNFG_DMCEN (1 << 30) | 40 | #define PXA3_MDCNFG_DMCEN (1 << 30) |
40 | #define DDR_HCAL 0x0060 | 41 | #define PXA3_DDR_HCAL 0x0060 |
41 | #define DDR_HCAL_HCRNG 0x1f | 42 | #define PXA3_DDR_HCAL_HCRNG 0x1f |
42 | #define DDR_HCAL_HCPROG (1 << 28) | 43 | #define PXA3_DDR_HCAL_HCPROG (1 << 28) |
43 | #define DDR_HCAL_HCEN (1 << 31) | 44 | #define PXA3_DDR_HCAL_HCEN (1 << 31) |
44 | #define DMCIER 0x0070 | 45 | #define PXA3_DMCIER 0x0070 |
45 | #define DMCIER_EDLP (1 << 29) | 46 | #define PXA3_DMCIER_EDLP (1 << 29) |
46 | #define DMCISR 0x0078 | 47 | #define PXA3_DMCISR 0x0078 |
47 | #define RCOMP 0x0100 | 48 | #define PXA3_RCOMP 0x0100 |
48 | #define RCOMP_SWEVAL (1 << 31) | 49 | #define PXA3_RCOMP_SWEVAL (1 << 31) |
49 | 50 | ||
50 | ENTRY(pm_enter_standby_start) | 51 | ENTRY(pm_enter_standby_start) |
51 | mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG) | 52 | mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG) |
52 | add r1, r1, #0x00100000 | 53 | add r1, r1, #0x00100000 |
53 | 54 | ||
54 | /* | 55 | /* |
@@ -59,54 +60,54 @@ ENTRY(pm_enter_standby_start) | |||
59 | * This also means that only the dynamic memory controller | 60 | * This also means that only the dynamic memory controller |
60 | * can be reliably accessed in the code following standby. | 61 | * can be reliably accessed in the code following standby. |
61 | */ | 62 | */ |
62 | ldr r2, [r1] @ Dummy read MDCNFG | 63 | ldr r2, [r1] @ Dummy read PXA3_MDCNFG |
63 | 64 | ||
64 | mcr p14, 0, r0, c7, c0, 0 | 65 | mcr p14, 0, r0, c7, c0, 0 |
65 | .rept 8 | 66 | .rept 8 |
66 | nop | 67 | nop |
67 | .endr | 68 | .endr |
68 | 69 | ||
69 | ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN | 70 | ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN |
70 | bic r0, r0, #DDR_HCAL_HCEN | 71 | bic r0, r0, #PXA3_DDR_HCAL_HCEN |
71 | str r0, [r1, #DDR_HCAL] | 72 | str r0, [r1, #PXA3_DDR_HCAL] |
72 | 1: ldr r0, [r1, #DDR_HCAL] | 73 | 1: ldr r0, [r1, #PXA3_DDR_HCAL] |
73 | tst r0, #DDR_HCAL_HCEN | 74 | tst r0, #PXA3_DDR_HCAL_HCEN |
74 | bne 1b | 75 | bne 1b |
75 | 76 | ||
76 | ldr r0, [r1, #RCOMP] @ Initiate RCOMP | 77 | ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP |
77 | orr r0, r0, #RCOMP_SWEVAL | 78 | orr r0, r0, #PXA3_RCOMP_SWEVAL |
78 | str r0, [r1, #RCOMP] | 79 | str r0, [r1, #PXA3_RCOMP] |
79 | 80 | ||
80 | mov r0, #~0 @ Clear interrupts | 81 | mov r0, #~0 @ Clear interrupts |
81 | str r0, [r1, #DMCISR] | 82 | str r0, [r1, #PXA3_DMCISR] |
82 | 83 | ||
83 | ldr r0, [r1, #DMCIER] @ set DMIER[EDLP] | 84 | ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP] |
84 | orr r0, r0, #DMCIER_EDLP | 85 | orr r0, r0, #PXA3_DMCIER_EDLP |
85 | str r0, [r1, #DMCIER] | 86 | str r0, [r1, #PXA3_DMCIER] |
86 | 87 | ||
87 | ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN | 88 | ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN |
88 | bic r0, r0, #DDR_HCAL_HCRNG | 89 | bic r0, r0, #PXA3_DDR_HCAL_HCRNG |
89 | orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG | 90 | orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG |
90 | str r0, [r1, #DDR_HCAL] | 91 | str r0, [r1, #PXA3_DDR_HCAL] |
91 | 92 | ||
92 | 1: ldr r0, [r1, #DMCISR] | 93 | 1: ldr r0, [r1, #PXA3_DMCISR] |
93 | tst r0, #DMCIER_EDLP | 94 | tst r0, #PXA3_DMCIER_EDLP |
94 | beq 1b | 95 | beq 1b |
95 | 96 | ||
96 | ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN] | 97 | ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN] |
97 | orr r0, r0, #MDCNFG_DMCEN | 98 | orr r0, r0, #PXA3_MDCNFG_DMCEN |
98 | str r0, [r1, #MDCNFG] | 99 | str r0, [r1, #PXA3_MDCNFG] |
99 | 1: ldr r0, [r1, #MDCNFG] | 100 | 1: ldr r0, [r1, #PXA3_MDCNFG] |
100 | tst r0, #MDCNFG_DMCEN | 101 | tst r0, #PXA3_MDCNFG_DMCEN |
101 | beq 1b | 102 | beq 1b |
102 | 103 | ||
103 | ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG] | 104 | ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG] |
104 | orr r0, r0, #2 @ HCRNG | 105 | orr r0, r0, #2 @ HCRNG |
105 | str r0, [r1, #DDR_HCAL] | 106 | str r0, [r1, #PXA3_DDR_HCAL] |
106 | 107 | ||
107 | ldr r0, [r1, #DMCIER] @ Clear the interrupt | 108 | ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt |
108 | bic r0, r0, #0x20000000 | 109 | bic r0, r0, #0x20000000 |
109 | str r0, [r1, #DMCIER] | 110 | str r0, [r1, #PXA3_DMCIER] |
110 | 111 | ||
111 | mov pc, lr | 112 | mov pc, lr |
112 | ENTRY(pm_enter_standby_end) | 113 | ENTRY(pm_enter_standby_end) |