[ARM] 3848/1: pxafb: Add option of fixing video modes and spitz QVGA mode support

Add the ability to have pxafb use only certain fixed video modes
(selected on a per platform basis). This is useful on production
hardware such as the Zaurus cxx00 models where the valid modes are
known in advance and any other modes could result in hardware damage.

Following this, add support for the cxx00 QVGA mode. Mode information
is passed to the lcd_power call to allowing the panel drivers to
configure the display hardware accordingly (corgi_lcd already contains
the functionality for the cxx00 panel).

This mirrors the setup already used by w100fb.

Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 36 insertions, 15 deletions

diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 1c32a9310dc2..401cdb850fbc 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -407,21 +407,42 @@ static struct pxaficp_platform_data spitz_ficp_platform_data = {
 /*
  * Spitz PXA Framebuffer
  */
-static struct pxafb_mach_info spitz_pxafb_info __initdata = {
-        .pixclock       = 19231,
-        .xres           = 480,
-        .yres           = 640,
-        .bpp            = 16,
-        .hsync_len      = 40,
-        .left_margin    = 46,
-        .right_margin   = 125,
-        .vsync_len      = 3,
-        .upper_margin   = 1,
-        .lower_margin   = 0,
-        .sync           = 0,
-        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act | LCCR0_LDDALT | LCCR0_OUC | LCCR0_CMDIM | LCCR0_RDSTM,
-        .lccr3          = LCCR3_PixRsEdg | LCCR3_OutEnH,
-        .pxafb_lcd_power = spitz_lcd_power,
+
+static struct pxafb_mode_info spitz_pxafb_modes[] = {
+{
+        .pixclock       = 19231,
+        .xres           = 480,
+        .yres           = 640,
+        .bpp            = 16,
+        .hsync_len      = 40,
+        .left_margin    = 46,
+        .right_margin   = 125,
+        .vsync_len      = 3,
+        .upper_margin   = 1,
+        .lower_margin   = 0,
+        .sync           = 0,
+},{
+        .pixclock       = 134617,
+        .xres           = 240,
+        .yres           = 320,
+        .bpp            = 16,
+        .hsync_len      = 20,
+        .left_margin    = 20,
+        .right_margin   = 46,
+        .vsync_len      = 2,
+        .upper_margin   = 1,
+        .lower_margin   = 0,
+        .sync           = 0,
+},
+};
+
+static struct pxafb_mach_info spitz_pxafb_info = {
+        .modes          = &spitz_pxafb_modes[0],
+        .num_modes      = 2,
+        .fixed_modes    = 1,
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act | LCCR0_LDDALT | LCCR0_OUC | LCCR0_CMDIM | LCCR0_RDSTM,
+        .lccr3          = LCCR3_PixRsEdg | LCCR3_OutEnH,
+        .pxafb_lcd_power = spitz_lcd_power,
 };