diff options
author | Mark Brown <broonie@sirena.org.uk> | 2008-02-13 10:39:21 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-19 06:29:02 -0400 |
commit | dcc88a170ce9f90e4b819c67feebb16e8a123f79 (patch) | |
tree | a4407f2d6ebdce9d386c27252dbaeec3f210abc1 /arch/arm/mach-pxa/pxa3xx.c | |
parent | 184dd48102425467fbbb209765894b04f668a9de (diff) |
[ARM] 4830/1: Add support for the CLK_POUT pin on PXA3xx CPUs
Expose control of the PXA3xx 13MHz CLK_POUT pin via the clock API
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/pxa3xx.c')
-rw-r--r-- | arch/arm/mach-pxa/pxa3xx.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 35f25fdaeba3..54c9e8371a21 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -156,6 +156,21 @@ static const struct clkops clk_pxa3xx_hsio_ops = { | |||
156 | .getrate = clk_pxa3xx_hsio_getrate, | 156 | .getrate = clk_pxa3xx_hsio_getrate, |
157 | }; | 157 | }; |
158 | 158 | ||
159 | static void clk_pout_enable(struct clk *clk) | ||
160 | { | ||
161 | OSCC |= OSCC_PEN; | ||
162 | } | ||
163 | |||
164 | static void clk_pout_disable(struct clk *clk) | ||
165 | { | ||
166 | OSCC &= ~OSCC_PEN; | ||
167 | } | ||
168 | |||
169 | static const struct clkops clk_pout_ops = { | ||
170 | .enable = clk_pout_enable, | ||
171 | .disable = clk_pout_disable, | ||
172 | }; | ||
173 | |||
159 | #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ | 174 | #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ |
160 | { \ | 175 | { \ |
161 | .name = _name, \ | 176 | .name = _name, \ |
@@ -175,6 +190,13 @@ static const struct clkops clk_pxa3xx_hsio_ops = { | |||
175 | } | 190 | } |
176 | 191 | ||
177 | static struct clk pxa3xx_clks[] = { | 192 | static struct clk pxa3xx_clks[] = { |
193 | { | ||
194 | .name = "CLK_POUT", | ||
195 | .ops = &clk_pout_ops, | ||
196 | .rate = 13000000, | ||
197 | .delay = 70, | ||
198 | }, | ||
199 | |||
178 | PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), | 200 | PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), |
179 | PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), | 201 | PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), |
180 | 202 | ||