diff options
author | Eric Miao <eric.y.miao@gmail.com> | 2010-11-21 21:49:55 -0500 |
---|---|---|
committer | Eric Miao <eric.y.miao@gmail.com> | 2010-12-16 01:31:19 -0500 |
commit | 4029813c89926ae5d78cc2dff49d845d934424f6 (patch) | |
tree | eaa7e075d3f369aa710ae4e26fdf80ab9cdd588b /arch/arm/mach-pxa/pxa3xx.c | |
parent | 2e8581e756ddbd0dea8b0d4059e9a82d2929de01 (diff) |
ARM: pxa: separate the clock support into clock-{pxa2xx,pxa3xx}.c
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-pxa/pxa3xx.c')
-rw-r--r-- | arch/arm/mach-pxa/pxa3xx.c | 170 |
1 files changed, 1 insertions, 169 deletions
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index a0b123c99a4d..b239c1ab3ed9 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -38,184 +38,15 @@ | |||
38 | #include "devices.h" | 38 | #include "devices.h" |
39 | #include "clock.h" | 39 | #include "clock.h" |
40 | 40 | ||
41 | /* Crystal clock: 13MHz */ | ||
42 | #define BASE_CLK 13000000 | ||
43 | |||
44 | /* Ring Oscillator Clock: 60MHz */ | ||
45 | #define RO_CLK 60000000 | ||
46 | |||
47 | #define ACCR_D0CS (1 << 26) | ||
48 | #define ACCR_PCCE (1 << 11) | ||
49 | |||
50 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) | 41 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) |
51 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) | 42 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) |
52 | 43 | ||
53 | /* crystal frequency to static memory controller multiplier (SMCFS) */ | ||
54 | static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; | ||
55 | |||
56 | /* crystal frequency to HSIO bus frequency multiplier (HSS) */ | ||
57 | static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; | ||
58 | |||
59 | /* | ||
60 | * Get the clock frequency as reflected by CCSR and the turbo flag. | ||
61 | * We assume these values have been applied via a fcs. | ||
62 | * If info is not 0 we also display the current settings. | ||
63 | */ | ||
64 | unsigned int pxa3xx_get_clk_frequency_khz(int info) | ||
65 | { | ||
66 | unsigned long acsr, xclkcfg; | ||
67 | unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; | ||
68 | |||
69 | /* Read XCLKCFG register turbo bit */ | ||
70 | __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); | ||
71 | t = xclkcfg & 0x1; | ||
72 | |||
73 | acsr = ACSR; | ||
74 | |||
75 | xl = acsr & 0x1f; | ||
76 | xn = (acsr >> 8) & 0x7; | ||
77 | hss = (acsr >> 14) & 0x3; | ||
78 | |||
79 | XL = xl * BASE_CLK; | ||
80 | XN = xn * XL; | ||
81 | |||
82 | ro = acsr & ACCR_D0CS; | ||
83 | |||
84 | CLK = (ro) ? RO_CLK : ((t) ? XN : XL); | ||
85 | HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
86 | |||
87 | if (info) { | ||
88 | pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", | ||
89 | RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, | ||
90 | (ro) ? "" : "in"); | ||
91 | pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", | ||
92 | XL / 1000000, (XL % 1000000) / 10000, xl); | ||
93 | pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", | ||
94 | XN / 1000000, (XN % 1000000) / 10000, xn, | ||
95 | (t) ? "" : "in"); | ||
96 | pr_info("HSIO bus clock: %d.%02dMHz\n", | ||
97 | HSS / 1000000, (HSS % 1000000) / 10000); | ||
98 | } | ||
99 | |||
100 | return CLK / 1000; | ||
101 | } | ||
102 | |||
103 | void pxa3xx_clear_reset_status(unsigned int mask) | 44 | void pxa3xx_clear_reset_status(unsigned int mask) |
104 | { | 45 | { |
105 | /* RESET_STATUS_* has a 1:1 mapping with ARSR */ | 46 | /* RESET_STATUS_* has a 1:1 mapping with ARSR */ |
106 | ARSR = mask; | 47 | ARSR = mask; |
107 | } | 48 | } |
108 | 49 | ||
109 | /* | ||
110 | * Return the current AC97 clock frequency. | ||
111 | */ | ||
112 | static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) | ||
113 | { | ||
114 | unsigned long rate = 312000000; | ||
115 | unsigned long ac97_div; | ||
116 | |||
117 | ac97_div = AC97_DIV; | ||
118 | |||
119 | /* This may loose precision for some rates but won't for the | ||
120 | * standard 24.576MHz. | ||
121 | */ | ||
122 | rate /= (ac97_div >> 12) & 0x7fff; | ||
123 | rate *= (ac97_div & 0xfff); | ||
124 | |||
125 | return rate; | ||
126 | } | ||
127 | |||
128 | /* | ||
129 | * Return the current HSIO bus clock frequency | ||
130 | */ | ||
131 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | ||
132 | { | ||
133 | unsigned long acsr; | ||
134 | unsigned int hss, hsio_clk; | ||
135 | |||
136 | acsr = ACSR; | ||
137 | |||
138 | hss = (acsr >> 14) & 0x3; | ||
139 | hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
140 | |||
141 | return hsio_clk; | ||
142 | } | ||
143 | |||
144 | void clk_pxa3xx_cken_enable(struct clk *clk) | ||
145 | { | ||
146 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
147 | |||
148 | if (clk->cken < 32) | ||
149 | CKENA |= mask; | ||
150 | else | ||
151 | CKENB |= mask; | ||
152 | } | ||
153 | |||
154 | void clk_pxa3xx_cken_disable(struct clk *clk) | ||
155 | { | ||
156 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
157 | |||
158 | if (clk->cken < 32) | ||
159 | CKENA &= ~mask; | ||
160 | else | ||
161 | CKENB &= ~mask; | ||
162 | } | ||
163 | |||
164 | const struct clkops clk_pxa3xx_cken_ops = { | ||
165 | .enable = clk_pxa3xx_cken_enable, | ||
166 | .disable = clk_pxa3xx_cken_disable, | ||
167 | }; | ||
168 | |||
169 | static const struct clkops clk_pxa3xx_hsio_ops = { | ||
170 | .enable = clk_pxa3xx_cken_enable, | ||
171 | .disable = clk_pxa3xx_cken_disable, | ||
172 | .getrate = clk_pxa3xx_hsio_getrate, | ||
173 | }; | ||
174 | |||
175 | static const struct clkops clk_pxa3xx_ac97_ops = { | ||
176 | .enable = clk_pxa3xx_cken_enable, | ||
177 | .disable = clk_pxa3xx_cken_disable, | ||
178 | .getrate = clk_pxa3xx_ac97_getrate, | ||
179 | }; | ||
180 | |||
181 | static void clk_pout_enable(struct clk *clk) | ||
182 | { | ||
183 | OSCC |= OSCC_PEN; | ||
184 | } | ||
185 | |||
186 | static void clk_pout_disable(struct clk *clk) | ||
187 | { | ||
188 | OSCC &= ~OSCC_PEN; | ||
189 | } | ||
190 | |||
191 | static const struct clkops clk_pout_ops = { | ||
192 | .enable = clk_pout_enable, | ||
193 | .disable = clk_pout_disable, | ||
194 | }; | ||
195 | |||
196 | static void clk_dummy_enable(struct clk *clk) | ||
197 | { | ||
198 | } | ||
199 | |||
200 | static void clk_dummy_disable(struct clk *clk) | ||
201 | { | ||
202 | } | ||
203 | |||
204 | static const struct clkops clk_dummy_ops = { | ||
205 | .enable = clk_dummy_enable, | ||
206 | .disable = clk_dummy_disable, | ||
207 | }; | ||
208 | |||
209 | static struct clk clk_pxa3xx_pout = { | ||
210 | .ops = &clk_pout_ops, | ||
211 | .rate = 13000000, | ||
212 | .delay = 70, | ||
213 | }; | ||
214 | |||
215 | static struct clk clk_dummy = { | ||
216 | .ops = &clk_dummy_ops, | ||
217 | }; | ||
218 | |||
219 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); | 50 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); |
220 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); | 51 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); |
221 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | 52 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); |
@@ -236,6 +67,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); | |||
236 | static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); | 67 | static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); |
237 | static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); | 68 | static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); |
238 | static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); | 69 | static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); |
70 | static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); | ||
239 | 71 | ||
240 | static struct clk_lookup pxa3xx_clkregs[] = { | 72 | static struct clk_lookup pxa3xx_clkregs[] = { |
241 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), | 73 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), |