diff options
author | Eric Miao <eric.y.miao@gmail.com> | 2007-07-18 06:38:45 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-07-20 12:25:10 -0400 |
commit | 711be5ccfe9a02ba560aa918a008c31ea4760163 (patch) | |
tree | b54cba04944a5ae0cb8a2d8ecd4d8efd14f2e495 /arch/arm/mach-pxa/pxa27x.c | |
parent | e09d02e123fb6944af23a0697369ebcfc15acf73 (diff) |
[ARM] 4488/1: pxa: move pxa25x/pxa27x specific code out of pm.c
1. introduce a structure pxa_cpu_pm_fns for pxa25x/pxa27x specific
operations as follows:
struct pxa_cpu_pm_fns {
int save_size;
void (*save)(unsigned long *);
void (*restore)(unsigned long *);
int (*valid)(suspend_state_t state);
void (*enter)(suspend_state_t state);
}
2. processor specific registers saving and restoring are performed
by calling the corresponding (*save) and (*restore)
3. pxa_cpu_pm_fns->save_size should be initialized to the required
size for processor specific registers saving, the allocated
memory address will be passed to (*save) and (*restore)
memory allocation happens early in pxa_pm_init(), and save_size
should be assigned prior to this (which is usually true, since
pxa_pm_init() happens in device_initcall()
4. there're some redundancies for those SLEEP_SAVE_XXX and related
macros, will be fixed later, one way possible is for the system
devices to handle the specific registers saving and restoring
Signed-off-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/pxa27x.c')
-rw-r--r-- | arch/arm/mach-pxa/pxa27x.c | 117 |
1 files changed, 110 insertions, 7 deletions
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index c85f0b01c326..9240d37e23fa 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
@@ -126,14 +126,109 @@ EXPORT_SYMBOL(get_lcdclk_frequency_10khz); | |||
126 | 126 | ||
127 | #ifdef CONFIG_PM | 127 | #ifdef CONFIG_PM |
128 | 128 | ||
129 | void pxa_cpu_pm_enter(suspend_state_t state) | 129 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
130 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | ||
131 | |||
132 | #define RESTORE_GPLEVEL(n) do { \ | ||
133 | GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ | ||
134 | GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ | ||
135 | } while (0) | ||
136 | |||
137 | /* | ||
138 | * List of global PXA peripheral registers to preserve. | ||
139 | * More ones like CP and general purpose register values are preserved | ||
140 | * with the stack pointer in sleep.S. | ||
141 | */ | ||
142 | enum { SLEEP_SAVE_START = 0, | ||
143 | |||
144 | SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3, | ||
145 | SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3, | ||
146 | SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3, | ||
147 | SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3, | ||
148 | SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, | ||
149 | |||
150 | SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, | ||
151 | SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, | ||
152 | SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, | ||
153 | SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, | ||
154 | |||
155 | SLEEP_SAVE_PSTR, | ||
156 | |||
157 | SLEEP_SAVE_ICMR, | ||
158 | SLEEP_SAVE_CKEN, | ||
159 | |||
160 | SLEEP_SAVE_MDREFR, | ||
161 | SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, | ||
162 | SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, | ||
163 | |||
164 | SLEEP_SAVE_SIZE | ||
165 | }; | ||
166 | |||
167 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | ||
168 | { | ||
169 | SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3); | ||
170 | SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3); | ||
171 | SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3); | ||
172 | SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3); | ||
173 | SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); | ||
174 | |||
175 | SAVE(GAFR0_L); SAVE(GAFR0_U); | ||
176 | SAVE(GAFR1_L); SAVE(GAFR1_U); | ||
177 | SAVE(GAFR2_L); SAVE(GAFR2_U); | ||
178 | SAVE(GAFR3_L); SAVE(GAFR3_U); | ||
179 | |||
180 | SAVE(MDREFR); | ||
181 | SAVE(PWER); SAVE(PCFR); SAVE(PRER); | ||
182 | SAVE(PFER); SAVE(PKWR); | ||
183 | |||
184 | SAVE(ICMR); ICMR = 0; | ||
185 | SAVE(CKEN); | ||
186 | SAVE(PSTR); | ||
187 | |||
188 | /* Clear GPIO transition detect bits */ | ||
189 | GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3; | ||
190 | } | ||
191 | |||
192 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | ||
193 | { | ||
194 | /* ensure not to come back here if it wasn't intended */ | ||
195 | PSPR = 0; | ||
196 | |||
197 | /* restore registers */ | ||
198 | RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); | ||
199 | RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3); | ||
200 | RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3); | ||
201 | RESTORE(GAFR0_L); RESTORE(GAFR0_U); | ||
202 | RESTORE(GAFR1_L); RESTORE(GAFR1_U); | ||
203 | RESTORE(GAFR2_L); RESTORE(GAFR2_U); | ||
204 | RESTORE(GAFR3_L); RESTORE(GAFR3_U); | ||
205 | RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3); | ||
206 | RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3); | ||
207 | RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); | ||
208 | |||
209 | RESTORE(MDREFR); | ||
210 | RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); | ||
211 | RESTORE(PFER); RESTORE(PKWR); | ||
212 | |||
213 | PSSR = PSSR_RDH | PSSR_PH; | ||
214 | |||
215 | RESTORE(CKEN); | ||
216 | |||
217 | ICLR = 0; | ||
218 | ICCR = 1; | ||
219 | RESTORE(ICMR); | ||
220 | RESTORE(PSTR); | ||
221 | } | ||
222 | |||
223 | void pxa27x_cpu_pm_enter(suspend_state_t state) | ||
130 | { | 224 | { |
131 | extern void pxa_cpu_standby(void); | 225 | extern void pxa_cpu_standby(void); |
132 | extern void pxa_cpu_suspend(unsigned int); | 226 | extern void pxa_cpu_suspend(unsigned int); |
133 | extern void pxa_cpu_resume(void); | 227 | extern void pxa_cpu_resume(void); |
134 | 228 | ||
135 | if (state == PM_SUSPEND_STANDBY) | 229 | if (state == PM_SUSPEND_STANDBY) |
136 | CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0); | 230 | CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | |
231 | (1 << CKEN_LCD) | (1 << CKEN_PWM0); | ||
137 | else | 232 | else |
138 | CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER); | 233 | CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER); |
139 | 234 | ||
@@ -155,15 +250,23 @@ void pxa_cpu_pm_enter(suspend_state_t state) | |||
155 | } | 250 | } |
156 | } | 251 | } |
157 | 252 | ||
158 | static int pxa27x_pm_valid(suspend_state_t state) | 253 | static int pxa27x_cpu_pm_valid(suspend_state_t state) |
159 | { | 254 | { |
160 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | 255 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; |
161 | } | 256 | } |
162 | 257 | ||
163 | static struct pm_ops pxa27x_pm_ops = { | 258 | static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { |
164 | .enter = pxa_pm_enter, | 259 | .save_size = SLEEP_SAVE_SIZE, |
165 | .valid = pxa27x_pm_valid, | 260 | .save = pxa27x_cpu_pm_save, |
261 | .restore = pxa27x_cpu_pm_restore, | ||
262 | .valid = pxa27x_cpu_pm_valid, | ||
263 | .enter = pxa27x_cpu_pm_enter, | ||
166 | }; | 264 | }; |
265 | |||
266 | static void __init pxa27x_init_pm(void) | ||
267 | { | ||
268 | pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; | ||
269 | } | ||
167 | #endif | 270 | #endif |
168 | 271 | ||
169 | /* | 272 | /* |
@@ -249,7 +352,7 @@ static int __init pxa27x_init(void) | |||
249 | if ((ret = pxa_init_dma(32))) | 352 | if ((ret = pxa_init_dma(32))) |
250 | return ret; | 353 | return ret; |
251 | #ifdef CONFIG_PM | 354 | #ifdef CONFIG_PM |
252 | pm_set_ops(&pxa27x_pm_ops); | 355 | pxa27x_init_pm(); |
253 | #endif | 356 | #endif |
254 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | 357 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
255 | } | 358 | } |