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authorEric Miao <eric.y.miao@gmail.com>2010-11-22 09:48:49 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-12-16 01:31:19 -0500
commit2a125dd56b3a853701063fe8a678ad7603e385fd (patch)
tree279a16da435e810fa8490fe4a1557486a54e9cf3 /arch/arm/mach-pxa/pxa25x.c
parent4029813c89926ae5d78cc2dff49d845d934424f6 (diff)
ARM: pxa: remove get_memclk_frequency_10khz()
Introduce 'struct clk' for memory and remove get_memclk_frequency_10khz(). Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-pxa/pxa25x.c')
-rw-r--r--arch/arm/mach-pxa/pxa25x.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index f29775e3e18d..65051bb6d62c 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -92,23 +92,21 @@ unsigned int pxa25x_get_clk_frequency_khz(int info)
92 return (turbo & 1) ? (N/1000) : (M/1000); 92 return (turbo & 1) ? (N/1000) : (M/1000);
93} 93}
94 94
95/* 95static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
96 * Return the current memory clock frequency in units of 10kHz
97 */
98unsigned int pxa25x_get_memclk_frequency_10khz(void)
99{ 96{
100 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 97 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
101} 98}
102 99
103static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) 100static const struct clkops clk_pxa25x_mem_ops = {
104{ 101 .enable = clk_dummy_enable,
105 return pxa25x_get_memclk_frequency_10khz() * 10000; 102 .disable = clk_dummy_disable,
106} 103 .getrate = clk_pxa25x_mem_getrate,
104};
107 105
108static const struct clkops clk_pxa25x_lcd_ops = { 106static const struct clkops clk_pxa25x_lcd_ops = {
109 .enable = clk_pxa2xx_cken_enable, 107 .enable = clk_pxa2xx_cken_enable,
110 .disable = clk_pxa2xx_cken_disable, 108 .disable = clk_pxa2xx_cken_disable,
111 .getrate = clk_pxa25x_lcd_getrate, 109 .getrate = clk_pxa25x_mem_getrate,
112}; 110};
113 111
114static unsigned long gpio12_config_32k[] = { 112static unsigned long gpio12_config_32k[] = {
@@ -185,6 +183,7 @@ static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
185static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); 183static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
186static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); 184static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
187static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); 185static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
186static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
188 187
189static struct clk_lookup pxa25x_clkregs[] = { 188static struct clk_lookup pxa25x_clkregs[] = {
190 INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), 189 INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
@@ -205,6 +204,7 @@ static struct clk_lookup pxa25x_clkregs[] = {
205 INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), 204 INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
206 INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), 205 INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
207 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), 206 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
207 INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
208}; 208};
209 209
210static struct clk_lookup pxa25x_hwuart_clkreg = 210static struct clk_lookup pxa25x_hwuart_clkreg =