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authoreric miao <eric.y.miao@gmail.com>2007-08-29 05:22:17 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-10-12 16:15:33 -0400
commitc95530c7798b760901c5d6212e528b03e323b8ac (patch)
tree9bb58fcfaa0b7d44da117d94fc2b7606bbb9d98e /arch/arm/mach-pxa/irq.c
parent30f0b40844e5add7ad879e2f5939ff498f72f3e6 (diff)
[ARM] 4560/1: pxa: move processor specific set_wake logic out of irq.c
a function pxa_init_irq_set_wake() was introduced, so that processor specific code could install their own version code setting PFER and PRER registers within pxa_gpio_irq_type are removed, and the edge configuration is postponed to the (*set_wake) and copies the GRER and GFER register, which will always be set up correctly by pxa_gpio_irq_type() Signed-off-by: eric miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/irq.c')
-rw-r--r--arch/arm/mach-pxa/irq.c76
1 files changed, 10 insertions, 66 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 3d95442d4168..294cc6758d55 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -38,33 +38,11 @@ static void pxa_unmask_low_irq(unsigned int irq)
38 ICMR |= (1 << irq); 38 ICMR |= (1 << irq);
39} 39}
40 40
41static int pxa_set_wake(unsigned int irq, unsigned int on)
42{
43 u32 mask;
44
45 switch (irq) {
46 case IRQ_RTCAlrm:
47 mask = PWER_RTC;
48 break;
49#ifdef CONFIG_PXA27x
50 /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
51#endif
52 default:
53 return -EINVAL;
54 }
55 if (on)
56 PWER |= mask;
57 else
58 PWER &= ~mask;
59 return 0;
60}
61
62static struct irq_chip pxa_internal_chip_low = { 41static struct irq_chip pxa_internal_chip_low = {
63 .name = "SC", 42 .name = "SC",
64 .ack = pxa_mask_low_irq, 43 .ack = pxa_mask_low_irq,
65 .mask = pxa_mask_low_irq, 44 .mask = pxa_mask_low_irq,
66 .unmask = pxa_unmask_low_irq, 45 .unmask = pxa_unmask_low_irq,
67 .set_wake = pxa_set_wake,
68}; 46};
69 47
70void __init pxa_init_irq_low(void) 48void __init pxa_init_irq_low(void)
@@ -125,26 +103,6 @@ void __init pxa_init_irq_high(void)
125} 103}
126#endif 104#endif
127 105
128/* Note that if an input/irq line ever gets changed to an output during
129 * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
130 */
131#ifdef CONFIG_PXA27x
132
133/* PXA27x: Various gpios can issue wakeup events. This logic only
134 * handles the simple cases, not the WEMUX2 and WEMUX3 options
135 */
136#define PXA27x_GPIO_NOWAKE_MASK \
137 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
138#define WAKEMASK(gpio) \
139 (((gpio) <= 15) \
140 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
141 : ((gpio == 35) ? (1 << 24) : 0))
142#else
143
144/* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */
145#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
146#endif
147
148/* 106/*
149 * PXA GPIO edge detection for IRQs: 107 * PXA GPIO edge detection for IRQs:
150 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 108 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
@@ -158,11 +116,9 @@ static long GPIO_IRQ_mask[4];
158static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 116static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
159{ 117{
160 int gpio, idx; 118 int gpio, idx;
161 u32 mask;
162 119
163 gpio = IRQ_TO_GPIO(irq); 120 gpio = IRQ_TO_GPIO(irq);
164 idx = gpio >> 5; 121 idx = gpio >> 5;
165 mask = WAKEMASK(gpio);
166 122
167 if (type == IRQT_PROBE) { 123 if (type == IRQT_PROBE) {
168 /* Don't mess with enabled GPIOs using preconfigured edges or 124 /* Don't mess with enabled GPIOs using preconfigured edges or
@@ -182,19 +138,15 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
182 if (type & __IRQT_RISEDGE) { 138 if (type & __IRQT_RISEDGE) {
183 /* printk("rising "); */ 139 /* printk("rising "); */
184 __set_bit (gpio, GPIO_IRQ_rising_edge); 140 __set_bit (gpio, GPIO_IRQ_rising_edge);
185 PRER |= mask;
186 } else { 141 } else {
187 __clear_bit (gpio, GPIO_IRQ_rising_edge); 142 __clear_bit (gpio, GPIO_IRQ_rising_edge);
188 PRER &= ~mask;
189 } 143 }
190 144
191 if (type & __IRQT_FALEDGE) { 145 if (type & __IRQT_FALEDGE) {
192 /* printk("falling "); */ 146 /* printk("falling "); */
193 __set_bit (gpio, GPIO_IRQ_falling_edge); 147 __set_bit (gpio, GPIO_IRQ_falling_edge);
194 PFER |= mask;
195 } else { 148 } else {
196 __clear_bit (gpio, GPIO_IRQ_falling_edge); 149 __clear_bit (gpio, GPIO_IRQ_falling_edge);
197 PFER &= ~mask;
198 } 150 }
199 151
200 /* printk("edges\n"); */ 152 /* printk("edges\n"); */
@@ -213,29 +165,12 @@ static void pxa_ack_low_gpio(unsigned int irq)
213 GEDR0 = (1 << (irq - IRQ_GPIO0)); 165 GEDR0 = (1 << (irq - IRQ_GPIO0));
214} 166}
215 167
216static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
217{
218 int gpio = IRQ_TO_GPIO(irq);
219 u32 mask = WAKEMASK(gpio);
220
221 if (!mask)
222 return -EINVAL;
223
224 if (on)
225 PWER |= mask;
226 else
227 PWER &= ~mask;
228 return 0;
229}
230
231
232static struct irq_chip pxa_low_gpio_chip = { 168static struct irq_chip pxa_low_gpio_chip = {
233 .name = "GPIO-l", 169 .name = "GPIO-l",
234 .ack = pxa_ack_low_gpio, 170 .ack = pxa_ack_low_gpio,
235 .mask = pxa_mask_low_irq, 171 .mask = pxa_mask_low_irq,
236 .unmask = pxa_unmask_low_irq, 172 .unmask = pxa_unmask_low_irq,
237 .set_type = pxa_gpio_irq_type, 173 .set_type = pxa_gpio_irq_type,
238 .set_wake = pxa_set_gpio_wake,
239}; 174};
240 175
241/* 176/*
@@ -342,7 +277,6 @@ static struct irq_chip pxa_muxed_gpio_chip = {
342 .mask = pxa_mask_muxed_gpio, 277 .mask = pxa_mask_muxed_gpio,
343 .unmask = pxa_unmask_muxed_gpio, 278 .unmask = pxa_unmask_muxed_gpio,
344 .set_type = pxa_gpio_irq_type, 279 .set_type = pxa_gpio_irq_type,
345 .set_wake = pxa_set_gpio_wake,
346}; 280};
347 281
348void __init pxa_init_irq_gpio(int gpio_nr) 282void __init pxa_init_irq_gpio(int gpio_nr)
@@ -377,3 +311,13 @@ void __init pxa_init_irq_gpio(int gpio_nr)
377 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 311 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
378 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 312 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
379} 313}
314
315void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
316{
317 pxa_internal_chip_low.set_wake = set_wake;
318#ifdef CONFIG_PXA27x
319 pxa_internal_chip_high.set_wake = set_wake;
320#endif
321 pxa_low_gpio_chip.set_wake = set_wake;
322 pxa_muxed_gpio_chip.set_wake = set_wake;
323}