diff options
author | Eric Miao <eric.y.miao@gmail.com> | 2007-06-06 01:32:38 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-07-12 09:28:10 -0400 |
commit | c08b7b3ef6bf489ddabadc03e050f3db2ea44b5d (patch) | |
tree | 7933a8126ed112ae1cb7c40de14904d01c2fde86 /arch/arm/mach-pxa/irq.c | |
parent | 486c955118dbbb0f13dc4d40cc5dac2b23f82676 (diff) |
[ARM] 4435/1: PXA: remove PXA_INTERNAL_IRQS
1. define PXA_GPIO_IRQ_BASE to be right after the internal IRQs,
and define PXA_GPIO_IRQ_NUM to be 128 for all PXA2xx variants
2. make the code specific to the high IRQ numbers (32..64) to be
PXA27x specific
3. add a function pxa_init_irq_high() to initialize the internal
high IRQ chip, the invoke of this function could be moved to
PXA27x specific initialization code
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/irq.c')
-rw-r--r-- | arch/arm/mach-pxa/irq.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 45ce711f0472..844d3de3ef44 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -67,7 +67,7 @@ static struct irq_chip pxa_internal_chip_low = { | |||
67 | .set_wake = pxa_set_wake, | 67 | .set_wake = pxa_set_wake, |
68 | }; | 68 | }; |
69 | 69 | ||
70 | #if PXA_INTERNAL_IRQS > 32 | 70 | #ifdef CONFIG_PXA27x |
71 | 71 | ||
72 | /* | 72 | /* |
73 | * This is for the second set of internal IRQs as found on the PXA27x. | 73 | * This is for the second set of internal IRQs as found on the PXA27x. |
@@ -90,6 +90,19 @@ static struct irq_chip pxa_internal_chip_high = { | |||
90 | .unmask = pxa_unmask_high_irq, | 90 | .unmask = pxa_unmask_high_irq, |
91 | }; | 91 | }; |
92 | 92 | ||
93 | void __init pxa_init_irq_high(void) | ||
94 | { | ||
95 | int irq; | ||
96 | |||
97 | ICMR2 = 0; | ||
98 | ICLR2 = 0; | ||
99 | |||
100 | for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { | ||
101 | set_irq_chip(irq, &pxa_internal_chip_high); | ||
102 | set_irq_handler(irq, handle_level_irq); | ||
103 | set_irq_flags(irq, IRQF_VALID); | ||
104 | } | ||
105 | } | ||
93 | #endif | 106 | #endif |
94 | 107 | ||
95 | /* Note that if an input/irq line ever gets changed to an output during | 108 | /* Note that if an input/irq line ever gets changed to an output during |
@@ -314,7 +327,6 @@ static struct irq_chip pxa_muxed_gpio_chip = { | |||
314 | .set_wake = pxa_set_gpio_wake, | 327 | .set_wake = pxa_set_gpio_wake, |
315 | }; | 328 | }; |
316 | 329 | ||
317 | |||
318 | void __init pxa_init_irq(void) | 330 | void __init pxa_init_irq(void) |
319 | { | 331 | { |
320 | int irq; | 332 | int irq; |
@@ -338,8 +350,6 @@ void __init pxa_init_irq(void) | |||
338 | 350 | ||
339 | #ifdef CONFIG_PXA27x | 351 | #ifdef CONFIG_PXA27x |
340 | /* And similarly for the extra regs on the PXA27x */ | 352 | /* And similarly for the extra regs on the PXA27x */ |
341 | ICMR2 = 0; | ||
342 | ICLR2 = 0; | ||
343 | GFER3 = 0; | 353 | GFER3 = 0; |
344 | GRER3 = 0; | 354 | GRER3 = 0; |
345 | GEDR3 = GEDR3; | 355 | GEDR3 = GEDR3; |
@@ -357,12 +367,8 @@ void __init pxa_init_irq(void) | |||
357 | set_irq_flags(irq, IRQF_VALID); | 367 | set_irq_flags(irq, IRQF_VALID); |
358 | } | 368 | } |
359 | 369 | ||
360 | #if PXA_INTERNAL_IRQS > 32 | 370 | #ifdef CONFIG_PXA27x |
361 | for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { | 371 | pxa_init_irq_high(); |
362 | set_irq_chip(irq, &pxa_internal_chip_high); | ||
363 | set_irq_handler(irq, handle_level_irq); | ||
364 | set_irq_flags(irq, IRQF_VALID); | ||
365 | } | ||
366 | #endif | 372 | #endif |
367 | 373 | ||
368 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | 374 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { |