diff options
author | eric miao <eric.miao@marvell.com> | 2008-03-03 22:42:26 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-19 06:29:03 -0400 |
commit | e3630db1fa7677b350fd5a1ac5498cc48448ae28 (patch) | |
tree | 13fb517ac69a7a7a34851a0c4019d65f0b1bab8c /arch/arm/mach-pxa/irq.c | |
parent | 0e037bbb4a639fff01cebf552db19237ec688678 (diff) |
[ARM] pxa: move GPIO IRQ specific code out of irq.c into gpio.c
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/irq.c')
-rw-r--r-- | arch/arm/mach-pxa/irq.c | 184 |
1 files changed, 1 insertions, 183 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 4fd4560dd3ad..da3a44a4249a 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-pxa/irq.c | 2 | * linux/arch/arm/mach-pxa/irq.c |
3 | * | 3 | * |
4 | * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. | 4 | * Generic PXA IRQ handling |
5 | * | 5 | * |
6 | * Author: Nicolas Pitre | 6 | * Author: Nicolas Pitre |
7 | * Created: Jun 15, 2001 | 7 | * Created: Jun 15, 2001 |
@@ -104,188 +104,6 @@ void __init pxa_init_irq_high(void) | |||
104 | } | 104 | } |
105 | #endif | 105 | #endif |
106 | 106 | ||
107 | /* | ||
108 | * PXA GPIO edge detection for IRQs: | ||
109 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | ||
110 | * Use this instead of directly setting GRER/GFER. | ||
111 | */ | ||
112 | |||
113 | static long GPIO_IRQ_rising_edge[4]; | ||
114 | static long GPIO_IRQ_falling_edge[4]; | ||
115 | static long GPIO_IRQ_mask[4]; | ||
116 | |||
117 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | ||
118 | { | ||
119 | int gpio, idx; | ||
120 | |||
121 | gpio = IRQ_TO_GPIO(irq); | ||
122 | idx = gpio >> 5; | ||
123 | |||
124 | if (type == IRQ_TYPE_PROBE) { | ||
125 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
126 | * GPIOs set to alternate function or to output during probe | ||
127 | */ | ||
128 | if ((GPIO_IRQ_rising_edge[idx] | | ||
129 | GPIO_IRQ_falling_edge[idx] | | ||
130 | GPDR(gpio)) & GPIO_bit(gpio)) | ||
131 | return 0; | ||
132 | if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) | ||
133 | return 0; | ||
134 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | ||
135 | } | ||
136 | |||
137 | pxa_gpio_mode(gpio | GPIO_IN); | ||
138 | |||
139 | if (type & IRQ_TYPE_EDGE_RISING) | ||
140 | __set_bit(gpio, GPIO_IRQ_rising_edge); | ||
141 | else | ||
142 | __clear_bit(gpio, GPIO_IRQ_rising_edge); | ||
143 | |||
144 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
145 | __set_bit(gpio, GPIO_IRQ_falling_edge); | ||
146 | else | ||
147 | __clear_bit(gpio, GPIO_IRQ_falling_edge); | ||
148 | |||
149 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
150 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
151 | |||
152 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | ||
153 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | ||
154 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | ||
155 | return 0; | ||
156 | } | ||
157 | |||
158 | /* | ||
159 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. | ||
160 | */ | ||
161 | |||
162 | static void pxa_ack_low_gpio(unsigned int irq) | ||
163 | { | ||
164 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | ||
165 | } | ||
166 | |||
167 | static void pxa_mask_low_gpio(unsigned int irq) | ||
168 | { | ||
169 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | ||
170 | } | ||
171 | |||
172 | static void pxa_unmask_low_gpio(unsigned int irq) | ||
173 | { | ||
174 | ICMR |= 1 << (irq - PXA_IRQ(0)); | ||
175 | } | ||
176 | |||
177 | static struct irq_chip pxa_low_gpio_chip = { | ||
178 | .name = "GPIO-l", | ||
179 | .ack = pxa_ack_low_gpio, | ||
180 | .mask = pxa_mask_low_gpio, | ||
181 | .unmask = pxa_unmask_low_gpio, | ||
182 | .set_type = pxa_gpio_irq_type, | ||
183 | }; | ||
184 | |||
185 | /* | ||
186 | * Demux handler for GPIO>=2 edge detect interrupts | ||
187 | */ | ||
188 | |||
189 | #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) | ||
190 | |||
191 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | ||
192 | { | ||
193 | int loop, bit, n; | ||
194 | unsigned long gedr[4]; | ||
195 | |||
196 | do { | ||
197 | gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; | ||
198 | gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; | ||
199 | gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; | ||
200 | gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; | ||
201 | |||
202 | GEDR0 = gedr[0]; GEDR1 = gedr[1]; | ||
203 | GEDR2 = gedr[2]; GEDR3 = gedr[3]; | ||
204 | |||
205 | loop = 0; | ||
206 | bit = find_first_bit(gedr, GEDR_BITS); | ||
207 | while (bit < GEDR_BITS) { | ||
208 | loop = 1; | ||
209 | |||
210 | n = PXA_GPIO_IRQ_BASE + bit; | ||
211 | desc_handle_irq(n, irq_desc + n); | ||
212 | |||
213 | bit = find_next_bit(gedr, GEDR_BITS, bit + 1); | ||
214 | } | ||
215 | } while (loop); | ||
216 | } | ||
217 | |||
218 | static void pxa_ack_muxed_gpio(unsigned int irq) | ||
219 | { | ||
220 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
221 | GEDR(gpio) = GPIO_bit(gpio); | ||
222 | } | ||
223 | |||
224 | static void pxa_mask_muxed_gpio(unsigned int irq) | ||
225 | { | ||
226 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
227 | __clear_bit(gpio, GPIO_IRQ_mask); | ||
228 | GRER(gpio) &= ~GPIO_bit(gpio); | ||
229 | GFER(gpio) &= ~GPIO_bit(gpio); | ||
230 | } | ||
231 | |||
232 | static void pxa_unmask_muxed_gpio(unsigned int irq) | ||
233 | { | ||
234 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
235 | int idx = gpio >> 5; | ||
236 | __set_bit(gpio, GPIO_IRQ_mask); | ||
237 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
238 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
239 | } | ||
240 | |||
241 | static struct irq_chip pxa_muxed_gpio_chip = { | ||
242 | .name = "GPIO", | ||
243 | .ack = pxa_ack_muxed_gpio, | ||
244 | .mask = pxa_mask_muxed_gpio, | ||
245 | .unmask = pxa_unmask_muxed_gpio, | ||
246 | .set_type = pxa_gpio_irq_type, | ||
247 | }; | ||
248 | |||
249 | void __init pxa_init_irq_gpio(int gpio_nr) | ||
250 | { | ||
251 | int irq, i; | ||
252 | |||
253 | pxa_last_gpio = gpio_nr - 1; | ||
254 | |||
255 | /* clear all GPIO edge detects */ | ||
256 | for (i = 0; i < gpio_nr; i += 32) { | ||
257 | GFER(i) = 0; | ||
258 | GRER(i) = 0; | ||
259 | GEDR(i) = GEDR(i); | ||
260 | } | ||
261 | |||
262 | /* GPIO 0 and 1 must have their mask bit always set */ | ||
263 | GPIO_IRQ_mask[0] = 3; | ||
264 | |||
265 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | ||
266 | set_irq_chip(irq, &pxa_low_gpio_chip); | ||
267 | set_irq_handler(irq, handle_edge_irq); | ||
268 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
269 | } | ||
270 | |||
271 | for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { | ||
272 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | ||
273 | set_irq_handler(irq, handle_edge_irq); | ||
274 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
275 | } | ||
276 | |||
277 | /* Install handler for GPIO>=2 edge detect interrupts */ | ||
278 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | ||
279 | |||
280 | pxa_init_gpio(gpio_nr); | ||
281 | } | ||
282 | |||
283 | void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int)) | ||
284 | { | ||
285 | pxa_low_gpio_chip.set_wake = set_wake; | ||
286 | pxa_muxed_gpio_chip.set_wake = set_wake; | ||
287 | } | ||
288 | |||
289 | void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) | 107 | void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) |
290 | { | 108 | { |
291 | pxa_internal_chip_low.set_wake = set_wake; | 109 | pxa_internal_chip_low.set_wake = set_wake; |