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authorLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 20:36:49 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 20:36:49 -0500
commit14a3c4ab0e58d143c7928c9eb2f2610205e13bf2 (patch)
tree885992999d7a1a2fd3586efcf32ebcbcbc3a72aa /arch/arm/mach-pxa/include
parent1af237a099a3b8ff56aa384f605c6a68af7bf288 (diff)
parent47992cbdaef2f18a47871b2ed01ad27f568c8b73 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (407 commits) [ARM] pxafb: add support for overlay1 and overlay2 as framebuffer devices [ARM] pxafb: cleanup of the timing checking code [ARM] pxafb: cleanup of the color format manipulation code [ARM] pxafb: add palette format support for LCCR4_PAL_FOR_3 [ARM] pxafb: add support for FBIOPAN_DISPLAY by dma braching [ARM] pxafb: allow pxafb_set_par() to start from arbitrary yoffset [ARM] pxafb: allow video memory size to be configurable [ARM] pxa: add document on the MFP design and how to use it [ARM] sa1100_wdt: don't assume CLOCK_TICK_RATE to be a constant [ARM] rtc-sa1100: don't assume CLOCK_TICK_RATE to be a constant [ARM] pxa/tavorevb: update board support (smartpanel LCD + keypad) [ARM] pxa: Update eseries defconfig [ARM] 5352/1: add w90p910-plat config file [ARM] s3c: S3C options should depend on PLAT_S3C [ARM] mv78xx0: implement GPIO and GPIO interrupt support [ARM] Kirkwood: implement GPIO and GPIO interrupt support [ARM] Orion: share GPIO IRQ handling code [ARM] Orion: share GPIO handling code [ARM] s3c: define __io using the typesafe version [ARM] S3C64XX: Ensure CPU_V6 is selected ...
Diffstat (limited to 'arch/arm/mach-pxa/include')
-rw-r--r--arch/arm/mach-pxa/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-pxa/include/mach/dma.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/eseries-gpio.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/gumstix.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/h5000.h113
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h52
-rw-r--r--arch/arm/mach-pxa/include/mach/io.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/littleton.h11
-rw-r--r--arch/arm/mach-pxa/include/mach/memory.h11
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h31
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa27x.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa930.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/mioa701.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/mtd-xip.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h507
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h5
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h12
-rw-r--r--arch/arm/mach-pxa/include/mach/pxafb.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ac97.h99
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-lcd.h67
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-uart.h143
-rw-r--r--arch/arm/mach-pxa/include/mach/timex.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/uncompress.h4
23 files changed, 536 insertions, 575 deletions
diff --git a/arch/arm/mach-pxa/include/mach/clkdev.h b/arch/arm/mach-pxa/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index 955bfe606067..7804637a6df3 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -30,10 +30,6 @@ typedef enum {
30 DMA_PRIO_LOW = 2 30 DMA_PRIO_LOW = 2
31} pxa_dma_prio; 31} pxa_dma_prio;
32 32
33#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
34#define HAVE_ARCH_PCI_SET_DMA_MASK 1
35#endif
36
37/* 33/*
38 * DMA registration 34 * DMA registration
39 */ 35 */
diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
index 4c90b1310270..efbd2aa9ecec 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
@@ -43,8 +43,10 @@
43#define GPIO_E800_PCMCIA_PWR1 73 43#define GPIO_E800_PCMCIA_PWR1 73
44 44
45/* e7xx IrDA power control */ 45/* e7xx IrDA power control */
46#define GPIO_E7XX_IR_ON 38 46#define GPIO_E7XX_IR_OFF 38
47 47
48/* ASIC related GPIOs */ 48/* ASIC related GPIOs */
49#define GPIO_ESERIES_TMIO_IRQ 5 49#define GPIO_ESERIES_TMIO_IRQ 5
50#define GPIO_ESERIES_TMIO_PCLR 19
51#define GPIO_ESERIES_TMIO_SUSPEND 45
50#define GPIO_E800_ANGELX_IRQ 8 52#define GPIO_E800_ANGELX_IRQ 8
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index 42ee1956750e..099f54a41de4 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -94,3 +94,7 @@ has detected a cable insertion; driven low otherwise. */
94#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) 94#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
95#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) 95#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
96#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) 96#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
97
98/* for expansion boards that can't be programatically detected */
99extern int am200_init(void);
100
diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h
new file mode 100644
index 000000000000..2a5ae3802787
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/h5000.h
@@ -0,0 +1,113 @@
1/*
2 * Hardware definitions for HP iPAQ h5xxx Handheld Computers
3 *
4 * Copyright(20)02 Hewlett-Packard Company.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
12 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
13 * FITNESS FOR ANY PARTICULAR PURPOSE.
14 *
15 * Author: Jamey Hicks
16 */
17
18#ifndef __ASM_ARCH_H5000_H
19#define __ASM_ARCH_H5000_H
20
21#include <mach/mfp-pxa25x.h>
22
23/*
24 * CPU GPIOs
25 */
26
27#define H5000_GPIO_POWER_BUTTON (0)
28#define H5000_GPIO_RESET_BUTTON_N (1)
29#define H5000_GPIO_OPT_INT (2)
30#define H5000_GPIO_BACKUP_POWER (3)
31#define H5000_GPIO_ACTION_BUTTON (4)
32#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */
33/* 6 not connected */
34#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */
35/* 8 not connected */
36#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */
37#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */
38#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */
39/*(12) not connected */
40#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */
41#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */
42/*(15) is CS1# */
43/*(16) not connected */
44/*(17) not connected */
45/*(18) is pcmcia ready */
46/*(19) is dreq1 */
47/*(20) is dreq0 */
48#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */
49/*(22) is not connected */
50#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */
51#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */
52#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */
53#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */
54/*(27) not connected */
55#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */
56#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */
57#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */
58#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */
59#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */
60/*(33) is CS5# */
61#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */
62#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */
63#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */
64#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */
65#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */
66#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */
67#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */
68#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */
69
70#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */
71#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */
72#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */
73#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */
74
75#define H5000_GPIO_IRDA_RXD (46)
76#define H5000_GPIO_IRDA_TXD (47)
77
78#define H5000_GPIO_POE_N (48) /* used for pcmcia */
79#define H5000_GPIO_PWE_N (49) /* used for pcmcia */
80#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */
81#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */
82#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */
83#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */
84#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */
85#define H5000_GPIO_PREG_N (55) /* used for pcmcia */
86#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */
87#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */
88
89#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */
90/*(59) not connected */
91#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */
92#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */
93#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */
94/*(63) is not connected */
95#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */
96#define H5000_GPIO_CHG_EN (65) /* to sc801 en */
97#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */
98#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */
99#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */
100/*(69) is not connected */
101#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */
102#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71)
103#define H5000_GPIO_BT_M_RESET (72)
104#define H5000_GPIO_STD_CHG_RATE (73)
105#define H5000_GPIO_SD_WP_N (74)
106#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */
107#define H5000_GPIO_HEADPHONE_DETECT (76)
108#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */
109/*(78) is CS2# */
110/*(79) is CS3# */
111/*(80) is CS4# */
112
113#endif /* __ASM_ARCH_H5000_H */
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index a582a6d9b92b..16ab79547dae 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -102,6 +102,9 @@
102 * PXA930 B0 0x69056835 0x5E643013 102 * PXA930 B0 0x69056835 0x5E643013
103 * PXA930 B1 0x69056837 0x7E643013 103 * PXA930 B1 0x69056837 0x7E643013
104 * PXA930 B2 0x69056838 0x8E643013 104 * PXA930 B2 0x69056838 0x8E643013
105 *
106 * PXA935 A0 0x56056931 0x1E653013
107 * PXA935 B0 0x56056936 0x6E653013
105 */ 108 */
106#ifdef CONFIG_PXA25x 109#ifdef CONFIG_PXA25x
107#define __cpu_is_pxa210(id) \ 110#define __cpu_is_pxa210(id) \
@@ -178,12 +181,22 @@
178#define __cpu_is_pxa930(id) \ 181#define __cpu_is_pxa930(id) \
179 ({ \ 182 ({ \
180 unsigned int _id = (id) >> 4 & 0xfff; \ 183 unsigned int _id = (id) >> 4 & 0xfff; \
181 _id == 0x683; \ 184 _id == 0x683; \
182 }) 185 })
183#else 186#else
184#define __cpu_is_pxa930(id) (0) 187#define __cpu_is_pxa930(id) (0)
185#endif 188#endif
186 189
190#ifdef CONFIG_CPU_PXA935
191#define __cpu_is_pxa935(id) \
192 ({ \
193 unsigned int _id = (id) >> 4 & 0xfff; \
194 _id == 0x693; \
195 })
196#else
197#define __cpu_is_pxa935(id) (0)
198#endif
199
187#define cpu_is_pxa210() \ 200#define cpu_is_pxa210() \
188 ({ \ 201 ({ \
189 __cpu_is_pxa210(read_cpuid_id()); \ 202 __cpu_is_pxa210(read_cpuid_id()); \
@@ -204,8 +217,6 @@
204 __cpu_is_pxa25x(read_cpuid_id()); \ 217 __cpu_is_pxa25x(read_cpuid_id()); \
205 }) 218 })
206 219
207extern int cpu_is_pxa26x(void);
208
209#define cpu_is_pxa27x() \ 220#define cpu_is_pxa27x() \
210 ({ \ 221 ({ \
211 __cpu_is_pxa27x(read_cpuid_id()); \ 222 __cpu_is_pxa27x(read_cpuid_id()); \
@@ -232,6 +243,12 @@ extern int cpu_is_pxa26x(void);
232 __cpu_is_pxa930(id); \ 243 __cpu_is_pxa930(id); \
233 }) 244 })
234 245
246#define cpu_is_pxa935() \
247 ({ \
248 unsigned int id = read_cpuid(CPUID_ID); \
249 __cpu_is_pxa935(id); \
250 })
251
235/* 252/*
236 * CPUID Core Generation Bit 253 * CPUID Core Generation Bit
237 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x 254 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
@@ -249,6 +266,12 @@ extern int cpu_is_pxa26x(void);
249 _id == 0x3; \ 266 _id == 0x3; \
250 }) 267 })
251 268
269#define __cpu_is_pxa9xx(id) \
270 ({ \
271 unsigned int _id = (id) >> 4 & 0xfff; \
272 _id == 0x683 || _id == 0x693; \
273 })
274
252#define cpu_is_pxa2xx() \ 275#define cpu_is_pxa2xx() \
253 ({ \ 276 ({ \
254 __cpu_is_pxa2xx(read_cpuid_id()); \ 277 __cpu_is_pxa2xx(read_cpuid_id()); \
@@ -259,32 +282,25 @@ extern int cpu_is_pxa26x(void);
259 __cpu_is_pxa3xx(read_cpuid_id()); \ 282 __cpu_is_pxa3xx(read_cpuid_id()); \
260 }) 283 })
261 284
262/* 285#define cpu_is_pxa9xx() \
263 * Handy routine to set GPIO alternate functions 286 ({ \
264 */ 287 __cpu_is_pxa9xx(read_cpuid_id()); \
265extern int pxa_gpio_mode( int gpio_mode ); 288 })
266
267/*
268 * Return GPIO level, nonzero means high, zero is low
269 */
270extern int pxa_gpio_get_value(unsigned gpio);
271
272/*
273 * Set output GPIO level
274 */
275extern void pxa_gpio_set_value(unsigned gpio, int value);
276
277/* 289/*
278 * return current memory and LCD clock frequency in units of 10kHz 290 * return current memory and LCD clock frequency in units of 10kHz
279 */ 291 */
280extern unsigned int get_memclk_frequency_10khz(void); 292extern unsigned int get_memclk_frequency_10khz(void);
281 293
294/* return the clock tick rate of the OS timer */
295extern unsigned long get_clock_tick_rate(void);
282#endif 296#endif
283 297
284#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 298#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
285#define PCIBIOS_MIN_IO 0 299#define PCIBIOS_MIN_IO 0
286#define PCIBIOS_MIN_MEM 0 300#define PCIBIOS_MIN_MEM 0
287#define pcibios_assign_all_busses() 1 301#define pcibios_assign_all_busses() 1
302#define HAVE_ARCH_PCI_SET_DMA_MASK 1
288#endif 303#endif
289 304
305
290#endif /* _ASM_ARCH_HARDWARE_H */ 306#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index 600fd4f76603..262691fb97d8 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -6,15 +6,13 @@
6#ifndef __ASM_ARM_ARCH_IO_H 6#ifndef __ASM_ARM_ARCH_IO_H
7#define __ASM_ARM_ARCH_IO_H 7#define __ASM_ARM_ARCH_IO_H
8 8
9#include <mach/hardware.h>
10
11#define IO_SPACE_LIMIT 0xffffffff 9#define IO_SPACE_LIMIT 0xffffffff
12 10
13/* 11/*
14 * We don't actually have real ISA nor PCI buses, but there is so many 12 * We don't actually have real ISA nor PCI buses, but there is so many
15 * drivers out there that might just work if we fake them... 13 * drivers out there that might just work if we fake them...
16 */ 14 */
17#define __io(a) ((void __iomem *)(a)) 15#define __io(a) __typesafe_io(a)
18#define __mem_pci(a) (a) 16#define __mem_pci(a) (a)
19 17
20#endif 18#endif
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 5c4e320c1437..6c9b21c51322 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -1,8 +1,13 @@
1#ifndef __ASM_ARCH_ZYLONITE_H 1#ifndef __ASM_ARCH_LITTLETON_H
2#define __ASM_ARCH_ZYLONITE_H 2#define __ASM_ARCH_LITTLETON_H
3
4#include <mach/gpio.h>
3 5
4#define LITTLETON_ETH_PHYS 0x30000000 6#define LITTLETON_ETH_PHYS 0x30000000
5 7
6#define LITTLETON_GPIO_LCD_CS (17) 8#define LITTLETON_GPIO_LCD_CS (17)
7 9
8#endif /* __ASM_ARCH_ZYLONITE_H */ 10#define EXT0_GPIO_BASE (NR_BUILTIN_GPIO)
11#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x))
12
13#endif /* __ASM_ARCH_LITTLETON_H */
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 59aef89808d6..f626730ee42e 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -18,16 +18,6 @@
18#define PHYS_OFFSET UL(0xa0000000) 18#define PHYS_OFFSET UL(0xa0000000)
19 19
20/* 20/*
21 * Virtual view <-> DMA view memory address translations
22 * virt_to_bus: Used to translate the virtual address to an
23 * address suitable to be passed to set_dma_addr
24 * bus_to_virt: Used to convert an address for DMA operations
25 * to an address that the kernel can use.
26 */
27#define __virt_to_bus(x) __virt_to_phys(x)
28#define __bus_to_virt(x) __phys_to_virt(x)
29
30/*
31 * The nodes are matched with the physical SDRAM banks as follows: 21 * The nodes are matched with the physical SDRAM banks as follows:
32 * 22 *
33 * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff 23 * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff
@@ -47,6 +37,7 @@ void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
47 cmx2xx_pci_adjust_zones(node, size, holes) 37 cmx2xx_pci_adjust_zones(node, size, holes)
48 38
49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) 39#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
40#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
50#endif 41#endif
51 42
52#endif 43#endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index 617cab2cc8d0..a72869b73ee3 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -158,4 +158,35 @@
158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) 158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
159#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) 159#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
160 160
161#ifdef CONFIG_CPU_PXA26x
162/* GPIO */
163#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
164#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1)
165#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1)
166#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1)
167#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1)
168
169/* SDRAM */
170#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH)
171#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH)
172#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH)
173#define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH)
174
175/* USB */
176#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1)
177#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2)
178#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2)
179#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW)
180#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
181#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH)
182
183/* ASSP */
184#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3)
185#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW)
186#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3)
187#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
188#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1)
189#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
190#endif
191
161#endif /* __ASM_ARCH_MFP_PXA25X_H */ 192#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index 122bdbd53182..da4f85a4f990 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -11,6 +11,12 @@
11#include <mach/mfp.h> 11#include <mach/mfp.h>
12#include <mach/mfp-pxa2xx.h> 12#include <mach/mfp-pxa2xx.h>
13 13
14/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
15 * bit is set, regardless of the GPIO configuration
16 */
17#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0)
18#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0)
19
14/* GPIO */ 20/* GPIO */
15#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) 21#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
16#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) 22#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0)
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index fabd9b4df827..fa73f56a1372 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -421,6 +421,7 @@
421#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) 421#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
422#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) 422#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
423#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) 423#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
424#define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW)
424 425
425/* CIR */ 426/* CIR */
426#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) 427#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
index 8483cb511831..02868447b0b1 100644
--- a/arch/arm/mach-pxa/include/mach/mioa701.h
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -10,12 +10,14 @@
10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) 10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
11 11
12/* Global GPIOs */ 12/* Global GPIOs */
13#define GPIO9_CHARGE_nEN 9 13#define GPIO9_CHARGE_EN 9
14#define GPIO18_POWEROFF 18 14#define GPIO18_POWEROFF 18
15#define GPIO87_LCD_POWER 87 15#define GPIO87_LCD_POWER 87
16#define GPIO96_AC_DETECT 96
17#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */
16 18
17/* USB */ 19/* USB */
18#define GPIO13_USB_DETECT 13 20#define GPIO13_nUSB_DETECT 13
19#define GPIO22_USB_ENABLE 22 21#define GPIO22_USB_ENABLE 22
20 22
21/* SDIO bits */ 23/* SDIO bits */
@@ -24,7 +26,10 @@
24#define GPIO91_SDIO_EN 91 26#define GPIO91_SDIO_EN 91
25 27
26/* Bluetooth */ 28/* Bluetooth */
29#define GPIO14_BT_nACTIVITY 14
27#define GPIO83_BT_ON 83 30#define GPIO83_BT_ON 83
31#define GPIO77_BT_UNKNOWN1 77
32#define GPIO86_BT_MAYBE_nRESET 86
28 33
29/* GPS */ 34/* GPS */
30#define GPIO23_GPS_UNKNOWN1 23 35#define GPIO23_GPS_UNKNOWN1 23
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
index 4d452fcb1508..cfca8155be72 100644
--- a/arch/arm/mach-pxa/include/mach/mtd-xip.h
+++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h
@@ -15,6 +15,7 @@
15#ifndef __ARCH_PXA_MTD_XIP_H__ 15#ifndef __ARCH_PXA_MTD_XIP_H__
16#define __ARCH_PXA_MTD_XIP_H__ 16#define __ARCH_PXA_MTD_XIP_H__
17 17
18#include <mach/hardware.h>
18#include <mach/pxa-regs.h> 19#include <mach/pxa-regs.h>
19 20
20#define xip_irqpending() (ICIP & ICMR) 21#define xip_irqpending() (ICIP & ICMR)
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index 15295d960000..31d615aa7723 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -13,6 +13,7 @@
13#ifndef __PXA_REGS_H 13#ifndef __PXA_REGS_H
14#define __PXA_REGS_H 14#define __PXA_REGS_H
15 15
16#include <mach/hardware.h>
16 17
17/* 18/*
18 * PXA Chip selects 19 * PXA Chip selects
@@ -123,298 +124,6 @@
123#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ 124#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
124#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 125#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
125 126
126
127/*
128 * UARTs
129 */
130
131/* Full Function UART (FFUART) */
132#define FFUART FFRBR
133#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
134#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
135#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
136#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
137#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
138#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
139#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
140#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
141#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
142#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
143#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
144#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
145#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
146
147/* Bluetooth UART (BTUART) */
148#define BTUART BTRBR
149#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
150#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
151#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
152#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
153#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
154#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
155#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
156#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
157#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
158#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
159#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
160#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
161#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
162
163/* Standard UART (STUART) */
164#define STUART STRBR
165#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
166#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
167#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
168#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
169#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
170#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
171#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
172#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
173#define STMSR __REG(0x40700018) /* Reserved */
174#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
175#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
176#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
177#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
178
179/* Hardware UART (HWUART) */
180#define HWUART HWRBR
181#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
182#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
183#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
184#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
185#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
186#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
187#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
188#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
189#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
190#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
191#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
192#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
193#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
194#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
195#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
196#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
197
198#define IER_DMAE (1 << 7) /* DMA Requests Enable */
199#define IER_UUE (1 << 6) /* UART Unit Enable */
200#define IER_NRZE (1 << 5) /* NRZ coding Enable */
201#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
202#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
203#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
204#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
205#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
206
207#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
208#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
209#define IIR_TOD (1 << 3) /* Time Out Detected */
210#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
211#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
212#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
213
214#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
215#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
216#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
217#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
218#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
219#define FCR_ITL_1 (0)
220#define FCR_ITL_8 (FCR_ITL1)
221#define FCR_ITL_16 (FCR_ITL2)
222#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
223
224#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
225#define LCR_SB (1 << 6) /* Set Break */
226#define LCR_STKYP (1 << 5) /* Sticky Parity */
227#define LCR_EPS (1 << 4) /* Even Parity Select */
228#define LCR_PEN (1 << 3) /* Parity Enable */
229#define LCR_STB (1 << 2) /* Stop Bit */
230#define LCR_WLS1 (1 << 1) /* Word Length Select */
231#define LCR_WLS0 (1 << 0) /* Word Length Select */
232
233#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
234#define LSR_TEMT (1 << 6) /* Transmitter Empty */
235#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
236#define LSR_BI (1 << 4) /* Break Interrupt */
237#define LSR_FE (1 << 3) /* Framing Error */
238#define LSR_PE (1 << 2) /* Parity Error */
239#define LSR_OE (1 << 1) /* Overrun Error */
240#define LSR_DR (1 << 0) /* Data Ready */
241
242#define MCR_LOOP (1 << 4)
243#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
244#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
245#define MCR_RTS (1 << 1) /* Request to Send */
246#define MCR_DTR (1 << 0) /* Data Terminal Ready */
247
248#define MSR_DCD (1 << 7) /* Data Carrier Detect */
249#define MSR_RI (1 << 6) /* Ring Indicator */
250#define MSR_DSR (1 << 5) /* Data Set Ready */
251#define MSR_CTS (1 << 4) /* Clear To Send */
252#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
253#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
254#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
255#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
256
257/*
258 * IrSR (Infrared Selection Register)
259 */
260#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
261#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
262#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
263#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
264#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
265
266
267/*
268 * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
269 */
270
271/*
272 * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
273 */
274
275/*
276 * AC97 Controller registers
277 */
278
279#define POCR __REG(0x40500000) /* PCM Out Control Register */
280#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
281#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
282
283#define PICR __REG(0x40500004) /* PCM In Control Register */
284#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
285#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
286
287#define MCCR __REG(0x40500008) /* Mic In Control Register */
288#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
289#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
290
291#define GCR __REG(0x4050000C) /* Global Control Register */
292#ifdef CONFIG_PXA3xx
293#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
294#endif
295#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
296#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
297#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
298#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
299#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
300#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
301#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
302#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
303#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
304#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
305#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
306
307#define POSR __REG(0x40500010) /* PCM Out Status Register */
308#define POSR_FIFOE (1 << 4) /* FIFO error */
309#define POSR_FSR (1 << 2) /* FIFO Service Request */
310
311#define PISR __REG(0x40500014) /* PCM In Status Register */
312#define PISR_FIFOE (1 << 4) /* FIFO error */
313#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
314#define PISR_FSR (1 << 2) /* FIFO Service Request */
315
316#define MCSR __REG(0x40500018) /* Mic In Status Register */
317#define MCSR_FIFOE (1 << 4) /* FIFO error */
318#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
319#define MCSR_FSR (1 << 2) /* FIFO Service Request */
320
321#define GSR __REG(0x4050001C) /* Global Status Register */
322#define GSR_CDONE (1 << 19) /* Command Done */
323#define GSR_SDONE (1 << 18) /* Status Done */
324#define GSR_RDCS (1 << 15) /* Read Completion Status */
325#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
326#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
327#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
328#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
329#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
330#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
331#define GSR_PCR (1 << 8) /* Primary Codec Ready */
332#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
333#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
334#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
335#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
336#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
337#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
338#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
339
340#define CAR __REG(0x40500020) /* CODEC Access Register */
341#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
342
343#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
344#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
345
346#define MOCR __REG(0x40500100) /* Modem Out Control Register */
347#define MOCR_FEIE (1 << 3) /* FIFO Error */
348#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
349
350#define MICR __REG(0x40500108) /* Modem In Control Register */
351#define MICR_FEIE (1 << 3) /* FIFO Error */
352#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
353
354#define MOSR __REG(0x40500110) /* Modem Out Status Register */
355#define MOSR_FIFOE (1 << 4) /* FIFO error */
356#define MOSR_FSR (1 << 2) /* FIFO Service Request */
357
358#define MISR __REG(0x40500118) /* Modem In Status Register */
359#define MISR_FIFOE (1 << 4) /* FIFO error */
360#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
361#define MISR_FSR (1 << 2) /* FIFO Service Request */
362
363#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
364
365#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
366#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
367#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
368#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
369
370
371/*
372 * Fast Infrared Communication Port
373 */
374
375#define FICP __REG(0x40800000) /* Start of FICP area */
376#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
377#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
378#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
379#define ICDR __REG(0x4080000c) /* ICP Data Register */
380#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
381#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
382
383#define ICCR0_AME (1 << 7) /* Address match enable */
384#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
385#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
386#define ICCR0_RXE (1 << 4) /* Receive enable */
387#define ICCR0_TXE (1 << 3) /* Transmit enable */
388#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
389#define ICCR0_LBM (1 << 1) /* Loopback mode */
390#define ICCR0_ITR (1 << 0) /* IrDA transmission */
391
392#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
393#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
394#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
395#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
396#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
397#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
398
399#ifdef CONFIG_PXA27x
400#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
401#endif
402#define ICSR0_FRE (1 << 5) /* Framing error */
403#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
404#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
405#define ICSR0_RAB (1 << 2) /* Receiver abort */
406#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
407#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
408
409#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
410#define ICSR1_CRE (1 << 5) /* CRC error */
411#define ICSR1_EOF (1 << 4) /* End of frame */
412#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
413#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
414#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
415#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
416
417
418/* 127/*
419 * Real Time Clock 128 * Real Time Clock
420 */ 129 */
@@ -463,19 +172,6 @@
463 172
464 173
465/* 174/*
466 * Pulse Width Modulator
467 */
468
469#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
470#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
471#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
472
473#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
474#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
475#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
476
477
478/*
479 * Interrupt Controller 175 * Interrupt Controller
480 */ 176 */
481 177
@@ -496,19 +192,6 @@
496 * General Purpose I/O 192 * General Purpose I/O
497 */ 193 */
498 194
499#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
500#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
501#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
502#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
503
504#define GPLR_OFFSET 0x00
505#define GPDR_OFFSET 0x0C
506#define GPSR_OFFSET 0x18
507#define GPCR_OFFSET 0x24
508#define GRER_OFFSET 0x30
509#define GFER_OFFSET 0x3C
510#define GEDR_OFFSET 0x48
511
512#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ 195#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
513#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ 196#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
514#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ 197#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
@@ -558,10 +241,6 @@
558 241
559#define GPIO_bit(x) (1 << ((x) & 0x1f)) 242#define GPIO_bit(x) (1 << ((x) & 0x1f))
560 243
561#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
562
563/* Interrupt Controller */
564
565#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) 244#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
566#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) 245#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
567#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) 246#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
@@ -580,189 +259,5 @@
580#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) 259#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
581#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ 260#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
582 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) 261 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
583#else
584
585#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
586#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
587#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
588#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
589#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
590#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
591#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
592#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
593
594#endif
595
596/*
597 * Power Manager - see pxa2xx-regs.h
598 */
599
600/*
601 * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h
602 */
603
604/*
605 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
606 */
607
608/*
609 * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
610 */
611
612#ifdef CONFIG_PXA27x
613
614/* Camera Interface */
615#define CICR0 __REG(0x50000000)
616#define CICR1 __REG(0x50000004)
617#define CICR2 __REG(0x50000008)
618#define CICR3 __REG(0x5000000C)
619#define CICR4 __REG(0x50000010)
620#define CISR __REG(0x50000014)
621#define CIFR __REG(0x50000018)
622#define CITOR __REG(0x5000001C)
623#define CIBR0 __REG(0x50000028)
624#define CIBR1 __REG(0x50000030)
625#define CIBR2 __REG(0x50000038)
626
627#define CICR0_DMAEN (1 << 31) /* DMA request enable */
628#define CICR0_PAR_EN (1 << 30) /* Parity enable */
629#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
630#define CICR0_ENB (1 << 28) /* Camera interface enable */
631#define CICR0_DIS (1 << 27) /* Camera interface disable */
632#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
633#define CICR0_TOM (1 << 9) /* Time-out mask */
634#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
635#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
636#define CICR0_EOLM (1 << 6) /* End-of-line mask */
637#define CICR0_PERRM (1 << 5) /* Parity-error mask */
638#define CICR0_QDM (1 << 4) /* Quick-disable mask */
639#define CICR0_CDM (1 << 3) /* Disable-done mask */
640#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
641#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
642#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
643
644#define CICR1_TBIT (1 << 31) /* Transparency bit */
645#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
646#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
647#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
648#define CICR1_RGB_F (1 << 11) /* RGB format */
649#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
650#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
651#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
652#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
653#define CICR1_DW (0x7 << 0) /* Data width mask */
654
655#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
656 wait count mask */
657#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
658 wait count mask */
659#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
660#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
661 wait count mask */
662#define CICR2_FSW (0x7 << 0) /* Frame stabilization
663 wait count mask */
664
665#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
666 wait count mask */
667#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
668 wait count mask */
669#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
670#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
671 wait count mask */
672#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
673
674#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
675#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
676#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
677#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
678#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
679#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
680#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
681#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
682
683#define CISR_FTO (1 << 15) /* FIFO time-out */
684#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
685#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
686#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
687#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
688#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
689#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
690#define CISR_EOL (1 << 8) /* End of line */
691#define CISR_PAR_ERR (1 << 7) /* Parity error */
692#define CISR_CQD (1 << 6) /* Camera interface quick disable */
693#define CISR_CDD (1 << 5) /* Camera interface disable done */
694#define CISR_SOF (1 << 4) /* Start of frame */
695#define CISR_EOF (1 << 3) /* End of frame */
696#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
697#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
698#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
699
700#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
701#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
702#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
703#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
704#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
705#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
706#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
707#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
708
709#define SRAM_SIZE 0x40000 /* 4x64K */
710
711#define SRAM_MEM_PHYS 0x5C000000
712
713#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
714#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
715
716#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
717#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
718#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
719#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
720
721#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
722#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
723#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
724#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
725
726#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
727#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
728#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
729#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
730
731#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
732#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
733#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
734#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
735
736#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
737#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
738#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
739#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
740
741#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
742
743#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
744#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
745#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
746
747#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
748#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
749#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
750
751#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
752#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
753#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
754
755#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
756#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
757#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
758
759#endif
760
761/* PWRMODE register M field values */
762
763#define PWRMODE_IDLE 0x1
764#define PWRMODE_STANDBY 0x2
765#define PWRMODE_SLEEP 0x3
766#define PWRMODE_DEEPSLEEP 0x7
767 262
768#endif 263#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
index 6ef1dd09970b..d83393e25273 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
@@ -365,4 +365,9 @@
365#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) 365#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
366#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) 366#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
367 367
368/*
369 * Handy routine to set GPIO alternate functions
370 */
371extern int pxa_gpio_mode( int gpio_mode );
372
368#endif /* __ASM_ARCH_PXA2XX_GPIO_H */ 373#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 806ecfea44bf..77102d695cc7 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -49,6 +49,11 @@
49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ 49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ 50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
51 51
52#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
56
52#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ 57#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
53#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ 58#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
54#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ 59#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
@@ -243,4 +248,11 @@
243#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 248#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
244#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 249#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
245 250
251/* PWRMODE register M field values */
252
253#define PWRMODE_IDLE 0x1
254#define PWRMODE_STANDBY 0x2
255#define PWRMODE_SLEEP 0x3
256#define PWRMODE_DEEPSLEEP 0x7
257
246#endif 258#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index cbda4d35c421..6932720ba04e 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -48,6 +48,7 @@
48#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) 48#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
49#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) 49#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
50#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) 50#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
51#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT)
51#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) 52#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
52#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) 53#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
53#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) 54#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
@@ -94,6 +95,10 @@ struct pxafb_mode_info {
94 * in pxa27x and pxa3xx, initialize them to the same value or 95 * in pxa27x and pxa3xx, initialize them to the same value or
95 * the larger one will be used 96 * the larger one will be used
96 * 3. same to {rd,wr}_pulse_width 97 * 3. same to {rd,wr}_pulse_width
98 *
99 * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
100 * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
101 * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
97 */ 102 */
98 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ 103 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
99 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ 104 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
@@ -108,6 +113,7 @@ struct pxafb_mach_info {
108 unsigned int num_modes; 113 unsigned int num_modes;
109 114
110 unsigned int lcd_conn; 115 unsigned int lcd_conn;
116 unsigned long video_mem_size;
111 117
112 u_int fixed_modes:1, 118 u_int fixed_modes:1,
113 cmap_inverse:1, 119 cmap_inverse:1,
diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h
new file mode 100644
index 000000000000..e41b9d202b8c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h
@@ -0,0 +1,99 @@
1#ifndef __ASM_ARCH_REGS_AC97_H
2#define __ASM_ARCH_REGS_AC97_H
3
4/*
5 * AC97 Controller registers
6 */
7
8#define POCR __REG(0x40500000) /* PCM Out Control Register */
9#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
10#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
11
12#define PICR __REG(0x40500004) /* PCM In Control Register */
13#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
14#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
15
16#define MCCR __REG(0x40500008) /* Mic In Control Register */
17#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
18#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
19
20#define GCR __REG(0x4050000C) /* Global Control Register */
21#ifdef CONFIG_PXA3xx
22#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
23#endif
24#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
25#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
26#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
27#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
28#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
29#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
30#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
31#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
32#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
33#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
34#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
35
36#define POSR __REG(0x40500010) /* PCM Out Status Register */
37#define POSR_FIFOE (1 << 4) /* FIFO error */
38#define POSR_FSR (1 << 2) /* FIFO Service Request */
39
40#define PISR __REG(0x40500014) /* PCM In Status Register */
41#define PISR_FIFOE (1 << 4) /* FIFO error */
42#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
43#define PISR_FSR (1 << 2) /* FIFO Service Request */
44
45#define MCSR __REG(0x40500018) /* Mic In Status Register */
46#define MCSR_FIFOE (1 << 4) /* FIFO error */
47#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
48#define MCSR_FSR (1 << 2) /* FIFO Service Request */
49
50#define GSR __REG(0x4050001C) /* Global Status Register */
51#define GSR_CDONE (1 << 19) /* Command Done */
52#define GSR_SDONE (1 << 18) /* Status Done */
53#define GSR_RDCS (1 << 15) /* Read Completion Status */
54#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
55#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
56#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
57#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
58#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
59#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
60#define GSR_PCR (1 << 8) /* Primary Codec Ready */
61#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
62#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
63#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
64#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
65#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
66#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
67#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
68
69#define CAR __REG(0x40500020) /* CODEC Access Register */
70#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
71
72#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
73#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
74
75#define MOCR __REG(0x40500100) /* Modem Out Control Register */
76#define MOCR_FEIE (1 << 3) /* FIFO Error */
77#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
78
79#define MICR __REG(0x40500108) /* Modem In Control Register */
80#define MICR_FEIE (1 << 3) /* FIFO Error */
81#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
82
83#define MOSR __REG(0x40500110) /* Modem Out Status Register */
84#define MOSR_FIFOE (1 << 4) /* FIFO error */
85#define MOSR_FSR (1 << 2) /* FIFO Service Request */
86
87#define MISR __REG(0x40500118) /* Modem In Status Register */
88#define MISR_FIFOE (1 << 4) /* FIFO error */
89#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
90#define MISR_FSR (1 << 2) /* FIFO Service Request */
91
92#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
93
94#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
95#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
96#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
97#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
98
99#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
index c689c4ea769c..f82dcea792d9 100644
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -12,27 +12,29 @@
12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ 12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */ 13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */
14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */ 14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */
15#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ 15#define LCSR (0x038) /* LCD Controller Status Register 0 */
16#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ 16#define LCSR1 (0x034) /* LCD Controller Status Register 1 */
17#define LCSR (0x038) /* LCD Controller Status Register */
18#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ 17#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */
19#define TMEDRGBR (0x040) /* TMED RGB Seed Register */ 18#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
20#define TMEDCR (0x044) /* TMED Control Register */ 19#define TMEDCR (0x044) /* TMED Control Register */
21 20
21#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
22#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
23#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
24#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
25#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
26#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
27#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
28
29#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */
30#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */
31#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */
32#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */
33
22#define CMDCR (0x100) /* Command Control Register */ 34#define CMDCR (0x100) /* Command Control Register */
23#define PRSR (0x104) /* Panel Read Status Register */ 35#define PRSR (0x104) /* Panel Read Status Register */
24 36
25#define LCCR3_1BPP (0 << 24) 37#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))
26#define LCCR3_2BPP (1 << 24)
27#define LCCR3_4BPP (2 << 24)
28#define LCCR3_8BPP (3 << 24)
29#define LCCR3_16BPP (4 << 24)
30#define LCCR3_18BPP (5 << 24)
31#define LCCR3_18BPP_P (6 << 24)
32#define LCCR3_19BPP (7 << 24)
33#define LCCR3_19BPP_P (1 << 29)
34#define LCCR3_24BPP ((1 << 29) | (1 << 24))
35#define LCCR3_25BPP ((1 << 29) | (2 << 24))
36 38
37#define LCCR3_PDFOR_0 (0 << 30) 39#define LCCR3_PDFOR_0 (0 << 30)
38#define LCCR3_PDFOR_1 (1 << 30) 40#define LCCR3_PDFOR_1 (1 << 30)
@@ -42,19 +44,16 @@
42#define LCCR4_PAL_FOR_0 (0 << 15) 44#define LCCR4_PAL_FOR_0 (0 << 15)
43#define LCCR4_PAL_FOR_1 (1 << 15) 45#define LCCR4_PAL_FOR_1 (1 << 15)
44#define LCCR4_PAL_FOR_2 (2 << 15) 46#define LCCR4_PAL_FOR_2 (2 << 15)
47#define LCCR4_PAL_FOR_3 (3 << 15)
45#define LCCR4_PAL_FOR_MASK (3 << 15) 48#define LCCR4_PAL_FOR_MASK (3 << 15)
46 49
47#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ 50#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
48#define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */
49#define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */
50#define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */
51#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ 51#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
52#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */ 52#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */
53#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */ 53#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */
54#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */ 54#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */
55#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */
55#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ 56#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
56#define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */
57#define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */
58 57
59#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ 58#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
60#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ 59#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
@@ -126,9 +125,6 @@
126#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ 125#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
127#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) 126#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD)))
128 127
129#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
130#define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP)))
131
132#define LCCR3_ACB Fld (8, 8) /* AC Bias */ 128#define LCCR3_ACB Fld (8, 8) /* AC Bias */
133#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) 129#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB)))
134 130
@@ -157,8 +153,22 @@
157#define LCSR_RD_ST (1 << 11) /* read status */ 153#define LCSR_RD_ST (1 << 11) /* read status */
158#define LCSR_CMD_INT (1 << 12) /* command interrupt */ 154#define LCSR_CMD_INT (1 << 12) /* command interrupt */
159 155
156#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */
157#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */
158#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */
159#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */
160
160#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 161#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
161 162
163/* overlay control registers */
164#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */
165#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */
166#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */
167#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */
168#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */
169#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */
170#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */
171
162/* smartpanel related */ 172/* smartpanel related */
163#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ 173#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */
164#define PRSR_A0 (1 << 8) /* Read Data Source */ 174#define PRSR_A0 (1 << 8) /* Read Data Source */
@@ -177,4 +187,11 @@
177 187
178#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) 188#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
179#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) 189#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff))
190
191/* SMART_DELAY() is introduced for software controlled delay primitive which
192 * can be inserted between command sequences, unused command 0x6 is used here
193 * and delay ranges from 0ms ~ 255ms
194 */
195#define SMART_CMD_DELAY (0x6 << 9)
196#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff))
180#endif /* __ASM_ARCH_REGS_LCD_H */ 197#endif /* __ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h
new file mode 100644
index 000000000000..55aeb7fb72f6
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-uart.h
@@ -0,0 +1,143 @@
1#ifndef __ASM_ARCH_REGS_UART_H
2#define __ASM_ARCH_REGS_UART_H
3
4/*
5 * UARTs
6 */
7
8/* Full Function UART (FFUART) */
9#define FFUART FFRBR
10#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
11#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
12#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
13#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
14#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
15#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
16#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
17#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
18#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
19#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
20#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
21#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
22#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
23
24/* Bluetooth UART (BTUART) */
25#define BTUART BTRBR
26#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
27#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
28#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
29#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
30#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
31#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
32#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
33#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
34#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
35#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
36#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
37#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
38#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
39
40/* Standard UART (STUART) */
41#define STUART STRBR
42#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
43#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
44#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
45#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
46#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
47#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
48#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
49#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
50#define STMSR __REG(0x40700018) /* Reserved */
51#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
52#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
53#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
54#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
55
56/* Hardware UART (HWUART) */
57#define HWUART HWRBR
58#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
59#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
60#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
61#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
62#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
63#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
64#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
65#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
66#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
67#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
68#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
69#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
70#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
71#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
72#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
73#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
74
75#define IER_DMAE (1 << 7) /* DMA Requests Enable */
76#define IER_UUE (1 << 6) /* UART Unit Enable */
77#define IER_NRZE (1 << 5) /* NRZ coding Enable */
78#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
79#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
80#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
81#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
82#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
83
84#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
85#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
86#define IIR_TOD (1 << 3) /* Time Out Detected */
87#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
88#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
89#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
90
91#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
92#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
93#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
94#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
95#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
96#define FCR_ITL_1 (0)
97#define FCR_ITL_8 (FCR_ITL1)
98#define FCR_ITL_16 (FCR_ITL2)
99#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
100
101#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
102#define LCR_SB (1 << 6) /* Set Break */
103#define LCR_STKYP (1 << 5) /* Sticky Parity */
104#define LCR_EPS (1 << 4) /* Even Parity Select */
105#define LCR_PEN (1 << 3) /* Parity Enable */
106#define LCR_STB (1 << 2) /* Stop Bit */
107#define LCR_WLS1 (1 << 1) /* Word Length Select */
108#define LCR_WLS0 (1 << 0) /* Word Length Select */
109
110#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
111#define LSR_TEMT (1 << 6) /* Transmitter Empty */
112#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
113#define LSR_BI (1 << 4) /* Break Interrupt */
114#define LSR_FE (1 << 3) /* Framing Error */
115#define LSR_PE (1 << 2) /* Parity Error */
116#define LSR_OE (1 << 1) /* Overrun Error */
117#define LSR_DR (1 << 0) /* Data Ready */
118
119#define MCR_LOOP (1 << 4)
120#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
121#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
122#define MCR_RTS (1 << 1) /* Request to Send */
123#define MCR_DTR (1 << 0) /* Data Terminal Ready */
124
125#define MSR_DCD (1 << 7) /* Data Carrier Detect */
126#define MSR_RI (1 << 6) /* Ring Indicator */
127#define MSR_DSR (1 << 5) /* Data Set Ready */
128#define MSR_CTS (1 << 4) /* Clear To Send */
129#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
130#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
131#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
132#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
133
134/*
135 * IrSR (Infrared Selection Register)
136 */
137#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
138#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
139#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
140#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
141#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
142
143#endif /* __ASM_ARCH_REGS_UART_H */
diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h
index b05fc6683c47..af6760a50e1a 100644
--- a/arch/arm/mach-pxa/include/mach/timex.h
+++ b/arch/arm/mach-pxa/include/mach/timex.h
@@ -10,6 +10,14 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13/* Various drivers are still using the constant of CLOCK_TICK_RATE, for
14 * those drivers to at least work, the definition is provided here.
15 *
16 * NOTE: this is no longer accurate when multiple processors and boards
17 * are selected, newer drivers should not depend on this any more. Use
18 * either the clocksource/clockevent or get this at run-time by calling
19 * get_clock_tick_rate() (as defined in generic.c).
20 */
13 21
14#if defined(CONFIG_PXA25x) 22#if defined(CONFIG_PXA25x)
15/* PXA250/210 timer base */ 23/* PXA250/210 timer base */
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 21e3e890af98..f4b029c03957 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13#include <mach/pxa-regs.h> 13#include <mach/regs-uart.h>
14#include <asm/mach-types.h> 14#include <asm/mach-types.h>
15 15
16#define __REG(x) ((volatile unsigned long *)x) 16#define __REG(x) ((volatile unsigned long *)x)
@@ -35,7 +35,7 @@ static inline void flush(void)
35 35
36static inline void arch_decomp_setup(void) 36static inline void arch_decomp_setup(void)
37{ 37{
38 if (machine_is_littleton()) 38 if (machine_is_littleton() || machine_is_intelmote2())
39 UART = STUART; 39 UART = STUART;
40} 40}
41 41
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 06:44:38 -0500