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authorArnd Bergmann <arnd@arndb.de>2011-10-31 17:44:18 -0400
committerArnd Bergmann <arnd@arndb.de>2011-10-31 17:44:18 -0400
commit43872fa788060eef91ae437957e0a5e39f1c56fd (patch)
treedba464da61167d84b4f7470edebd5a769a78f9ee /arch/arm/mach-pxa/include
parent91fed558d0f33c74477569f50ed883fe6d430f1f (diff)
parentf55be1bf52aad524dc1bf556ae26c90262c87825 (diff)
Merge branch 'depends/rmk/gpio' into next/fixes
This sorts out merge conflicts with the arm/gpio branch that already got merged into mainline Linux. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-pxa/include')
-rw-r--r--arch/arm/mach-pxa/include/mach/gpio-pxa.h133
-rw-r--r--arch/arm/mach-pxa/include/mach/gpio.h110
-rw-r--r--arch/arm/mach-pxa/include/mach/littleton.h2
3 files changed, 136 insertions, 109 deletions
diff --git a/arch/arm/mach-pxa/include/mach/gpio-pxa.h b/arch/arm/mach-pxa/include/mach/gpio-pxa.h
new file mode 100644
index 000000000000..576868f8b8c5
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/gpio-pxa.h
@@ -0,0 +1,133 @@
1/*
2 * Written by Philipp Zabel <philipp.zabel@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 */
19#ifndef __MACH_PXA_GPIO_PXA_H
20#define __MACH_PXA_GPIO_PXA_H
21
22#include <mach/irqs.h>
23#include <mach/hardware.h>
24
25#define GPIO_REGS_VIRT io_p2v(0x40E00000)
26
27#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
28#define GPIO_REG(x) (GPIO_REGS_VIRT + (x))
29
30/* GPIO Pin Level Registers */
31#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00)
32#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00)
33#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00)
34#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00)
35
36/* GPIO Pin Direction Registers */
37#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c)
38#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c)
39#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c)
40#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c)
41
42/* GPIO Pin Output Set Registers */
43#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18)
44#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18)
45#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18)
46#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18)
47
48/* GPIO Pin Output Clear Registers */
49#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24)
50#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24)
51#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24)
52#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24)
53
54/* GPIO Rising Edge Detect Registers */
55#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30)
56#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30)
57#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30)
58#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30)
59
60/* GPIO Falling Edge Detect Registers */
61#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c)
62#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c)
63#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c)
64#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c)
65
66/* GPIO Edge Detect Status Registers */
67#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48)
68#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48)
69#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48)
70#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48)
71
72/* GPIO Alternate Function Select Registers */
73#define GAFR0_L GPIO_REG(0x0054)
74#define GAFR0_U GPIO_REG(0x0058)
75#define GAFR1_L GPIO_REG(0x005C)
76#define GAFR1_U GPIO_REG(0x0060)
77#define GAFR2_L GPIO_REG(0x0064)
78#define GAFR2_U GPIO_REG(0x0068)
79#define GAFR3_L GPIO_REG(0x006C)
80#define GAFR3_U GPIO_REG(0x0070)
81
82/* More handy macros. The argument is a literal GPIO number. */
83
84#define GPIO_bit(x) (1 << ((x) & 0x1f))
85
86#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
87#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
88#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
89#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
90#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
91#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
92#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
93#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
94
95
96#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM
97
98#define gpio_to_bank(gpio) ((gpio) >> 5)
99
100#ifdef CONFIG_CPU_PXA26x
101/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
102 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
103 */
104static inline int __gpio_is_inverted(unsigned gpio)
105{
106 return cpu_is_pxa25x() && gpio > 85;
107}
108#else
109static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
110#endif
111
112/*
113 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
114 * function of a GPIO, and GPDRx cannot be altered once configured. It
115 * is attributed as "occupied" here (I know this terminology isn't
116 * accurate, you are welcome to propose a better one :-)
117 */
118static inline int __gpio_is_occupied(unsigned gpio)
119{
120 if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
121 int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
122 int dir = GPDR(gpio) & GPIO_bit(gpio);
123
124 if (__gpio_is_inverted(gpio))
125 return af != 1 || dir == 0;
126 else
127 return af != 0 || dir != 0;
128 } else
129 return GPDR(gpio) & GPIO_bit(gpio);
130}
131
132#include <plat/gpio-pxa.h>
133#endif /* __MACH_PXA_GPIO_PXA_H */
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index c4639502efca..004cade7bb13 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -24,84 +24,10 @@
24#ifndef __ASM_ARCH_PXA_GPIO_H 24#ifndef __ASM_ARCH_PXA_GPIO_H
25#define __ASM_ARCH_PXA_GPIO_H 25#define __ASM_ARCH_PXA_GPIO_H
26 26
27#include <mach/irqs.h>
28#include <mach/hardware.h>
29#include <asm-generic/gpio.h> 27#include <asm-generic/gpio.h>
28/* The defines for the driver are needed for the accelerated accessors */
29#include "gpio-pxa.h"
30 30
31#define GPIO_REGS_VIRT io_p2v(0x40E00000)
32
33#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
34#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
35
36/* GPIO Pin Level Registers */
37#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00)
38#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00)
39#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00)
40#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00)
41
42/* GPIO Pin Direction Registers */
43#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c)
44#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c)
45#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c)
46#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c)
47
48/* GPIO Pin Output Set Registers */
49#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18)
50#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18)
51#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18)
52#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18)
53
54/* GPIO Pin Output Clear Registers */
55#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24)
56#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24)
57#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24)
58#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24)
59
60/* GPIO Rising Edge Detect Registers */
61#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30)
62#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30)
63#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30)
64#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30)
65
66/* GPIO Falling Edge Detect Registers */
67#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c)
68#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c)
69#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c)
70#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c)
71
72/* GPIO Edge Detect Status Registers */
73#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48)
74#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48)
75#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48)
76#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48)
77
78/* GPIO Alternate Function Select Registers */
79#define GAFR0_L GPIO_REG(0x0054)
80#define GAFR0_U GPIO_REG(0x0058)
81#define GAFR1_L GPIO_REG(0x005C)
82#define GAFR1_U GPIO_REG(0x0060)
83#define GAFR2_L GPIO_REG(0x0064)
84#define GAFR2_U GPIO_REG(0x0068)
85#define GAFR3_L GPIO_REG(0x006C)
86#define GAFR3_U GPIO_REG(0x0070)
87
88/* More handy macros. The argument is a literal GPIO number. */
89
90#define GPIO_bit(x) (1 << ((x) & 0x1f))
91
92#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
93#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
94#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
95#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
96#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
97#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
98#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
99#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
100
101
102#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM
103
104#define gpio_to_bank(gpio) ((gpio) >> 5)
105#define gpio_to_irq(gpio) IRQ_GPIO(gpio) 31#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
106 32
107static inline int irq_to_gpio(unsigned int irq) 33static inline int irq_to_gpio(unsigned int irq)
@@ -118,37 +44,5 @@ static inline int irq_to_gpio(unsigned int irq)
118 return -1; 44 return -1;
119} 45}
120 46
121#ifdef CONFIG_CPU_PXA26x
122/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
123 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
124 */
125static inline int __gpio_is_inverted(unsigned gpio)
126{
127 return cpu_is_pxa25x() && gpio > 85;
128}
129#else
130static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
131#endif
132
133/*
134 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
135 * function of a GPIO, and GPDRx cannot be altered once configured. It
136 * is attributed as "occupied" here (I know this terminology isn't
137 * accurate, you are welcome to propose a better one :-)
138 */
139static inline int __gpio_is_occupied(unsigned gpio)
140{
141 if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
142 int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
143 int dir = GPDR(gpio) & GPIO_bit(gpio);
144
145 if (__gpio_is_inverted(gpio))
146 return af != 1 || dir == 0;
147 else
148 return af != 0 || dir != 0;
149 } else
150 return GPDR(gpio) & GPIO_bit(gpio);
151}
152
153#include <plat/gpio.h> 47#include <plat/gpio.h>
154#endif 48#endif
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 2a5726c15e0e..b6238cbd8aea 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_ARCH_LITTLETON_H 1#ifndef __ASM_ARCH_LITTLETON_H
2#define __ASM_ARCH_LITTLETON_H 2#define __ASM_ARCH_LITTLETON_H
3 3
4#include <mach/gpio.h> 4#include <mach/gpio-pxa.h>
5 5
6#define LITTLETON_ETH_PHYS 0x30000000 6#define LITTLETON_ETH_PHYS 0x30000000
7 7
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 19:59:29 -0500