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authorTakashi Iwai <tiwai@suse.de>2009-03-23 19:35:53 -0400
committerTakashi Iwai <tiwai@suse.de>2009-03-23 19:35:53 -0400
commitb5c784894c90042f4fc6348aedc7524e899df281 (patch)
tree0db86a93d73e4aabca04e361d7e6807aa4c1d307 /arch/arm/mach-pxa/include
parentff4fc3656e489ed6ee575959b0510286aefe1e20 (diff)
parent1f2186951e02f2a5bcda9459f63136918932385a (diff)
Merge branch 'topic/asoc' into for-linus
Diffstat (limited to 'arch/arm/mach-pxa/include')
-rw-r--r--arch/arm/mach-pxa/include/mach/eseries-gpio.h15
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ssp.h7
2 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
index efbd2aa9ecec..f3e5509820d7 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
@@ -45,6 +45,21 @@
45/* e7xx IrDA power control */ 45/* e7xx IrDA power control */
46#define GPIO_E7XX_IR_OFF 38 46#define GPIO_E7XX_IR_OFF 38
47 47
48/* e740 audio control GPIOs */
49#define GPIO_E740_WM9705_nAVDD2 16
50#define GPIO_E740_MIC_ON 40
51#define GPIO_E740_AMP_ON 41
52
53/* e750 audio control GPIOs */
54#define GPIO_E750_HP_AMP_OFF 4
55#define GPIO_E750_SPK_AMP_OFF 7
56#define GPIO_E750_HP_DETECT 37
57
58/* e800 audio control GPIOs */
59#define GPIO_E800_HP_DETECT 81
60#define GPIO_E800_HP_AMP_OFF 82
61#define GPIO_E800_SPK_AMP_ON 83
62
48/* ASIC related GPIOs */ 63/* ASIC related GPIOs */
49#define GPIO_ESERIES_TMIO_IRQ 5 64#define GPIO_ESERIES_TMIO_IRQ 5
50#define GPIO_ESERIES_TMIO_PCLR 19 65#define GPIO_ESERIES_TMIO_PCLR 19
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index cf31986f6f05..018f6d65b57b 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -50,7 +50,7 @@
50#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ 50#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
51#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ 51#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
52#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ 52#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
53#define SSCR0_ADC (1 << 30) /* Audio clock select */ 53#define SSCR0_ACS (1 << 30) /* Audio clock select */
54#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 54#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
55#endif 55#endif
56 56
@@ -109,6 +109,11 @@
109#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ 109#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
110#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ 110#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
111 111
112#if defined(CONFIG_PXA3xx)
113#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
114#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
115#endif
116
112#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ 117#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
113#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ 118#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
114#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ 119#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */