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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-10-09 16:33:02 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-09 16:33:02 -0400
commit3f30a09a612bac2b531a206c2a58a292dd7ff182 (patch)
tree62741c2f78aeb3009c66dbcf014ebff2e034e597 /arch/arm/mach-pxa/include
parent9e165acf1b9e37af7c0fa39399b43d0bd8600039 (diff)
parentfda50a1c49ad7483eaa29a268d560422c413933f (diff)
Merge branch 'pxa-all' into devel
Conflicts: arch/arm/mach-pxa/Kconfig arch/arm/mach-pxa/corgi.c arch/arm/mach-pxa/include/mach/hardware.h arch/arm/mach-pxa/spitz.c
Diffstat (limited to 'arch/arm/mach-pxa/include')
-rw-r--r--arch/arm/mach-pxa/include/mach/akita.h32
-rw-r--r--arch/arm/mach-pxa/include/mach/corgi.h11
-rw-r--r--arch/arm/mach-pxa/include/mach/entry-macro.S4
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h79
-rw-r--r--arch/arm/mach-pxa/include/mach/i2c.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/irqs.h19
-rw-r--r--arch/arm/mach-pxa/include/mach/littleton.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/memory.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa320.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp.h5
-rw-r--r--arch/arm/mach-pxa/include/mach/mioa701.h67
-rw-r--r--arch/arm/mach-pxa/include/mach/ohci.h16
-rw-r--r--arch/arm/mach-pxa/include/mach/palmz72.h80
-rw-r--r--arch/arm/mach-pxa/include/mach/pm.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/poodle.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h320
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h22
-rw-r--r--arch/arm/mach-pxa/include/mach/spitz.h42
-rw-r--r--arch/arm/mach-pxa/include/mach/ssp.h24
-rw-r--r--arch/arm/mach-pxa/include/mach/trizeps4.h84
-rw-r--r--arch/arm/mach-pxa/include/mach/viper.h96
22 files changed, 540 insertions, 399 deletions
diff --git a/arch/arm/mach-pxa/include/mach/akita.h b/arch/arm/mach-pxa/include/mach/akita.h
deleted file mode 100644
index 5d8cc1d9cb10..000000000000
--- a/arch/arm/mach-pxa/include/mach/akita.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Hardware specific definitions for SL-C1000 (Akita)
3 *
4 * Copyright (c) 2005 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/* Akita IO Expander GPIOs */
13
14#define AKITA_IOEXP_RESERVED_7 (1 << 7)
15#define AKITA_IOEXP_IR_ON (1 << 6)
16#define AKITA_IOEXP_AKIN_PULLUP (1 << 5)
17#define AKITA_IOEXP_BACKLIGHT_CONT (1 << 4)
18#define AKITA_IOEXP_BACKLIGHT_ON (1 << 3)
19#define AKITA_IOEXP_MIC_BIAS (1 << 2)
20#define AKITA_IOEXP_RESERVED_1 (1 << 1)
21#define AKITA_IOEXP_RESERVED_0 (1 << 0)
22
23/* Direction Bitfield 0=output 1=input */
24#define AKITA_IOEXP_IO_DIR 0
25/* Default Values */
26#define AKITA_IOEXP_IO_OUT (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
27
28extern struct platform_device akitaioexp_device;
29
30void akita_set_ioexp(struct device *dev, unsigned char bitmask);
31void akita_reset_ioexp(struct device *dev, unsigned char bitmask);
32
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index bf856503baf6..585970ef08ce 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -98,12 +98,21 @@
98 CORGI_SCP_MIC_BIAS ) 98 CORGI_SCP_MIC_BIAS )
99#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) 99#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
100 100
101#define CORGI_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO)
102#define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0)
103#define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */
104#define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */
105#define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3)
106#define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4)
107#define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5)
108#define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6)
109#define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7)
110#define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8)
101 111
102/* 112/*
103 * Shared data structures 113 * Shared data structures
104 */ 114 */
105extern struct platform_device corgiscoop_device; 115extern struct platform_device corgiscoop_device;
106extern struct platform_device corgissp_device;
107 116
108#endif /* __ASM_ARCH_CORGI_H */ 117#endif /* __ASM_ARCH_CORGI_H */
109 118
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
index de16c12d5232..f6b4bf3e73d2 100644
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -41,7 +41,7 @@
41 and \irqstat, \irqstat, \irqnr 41 and \irqstat, \irqstat, \irqnr
42 clz \irqnr, \irqstat 42 clz \irqnr, \irqstat
43 rsb \irqnr, \irqnr, #31 43 rsb \irqnr, \irqnr, #31
44 add \irqnr, \irqnr, #32 44 add \irqnr, \irqnr, #(32 + PXA_IRQ(0))
45 b 1001f 45 b 1001f
461003: 461003:
47 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP 47 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
@@ -52,6 +52,6 @@
52 rsb \irqstat, \irqnr, #0 52 rsb \irqstat, \irqnr, #0
53 and \irqstat, \irqstat, \irqnr 53 and \irqstat, \irqstat, \irqnr
54 clz \irqnr, \irqstat 54 clz \irqnr, \irqstat
55 rsb \irqnr, \irqnr, #31 55 rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0))
561001: 561001:
57 .endm 57 .endm
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index a1a0a2ffd642..a582a6d9b92b 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -64,26 +64,72 @@
64 64
65#include <asm/cputype.h> 65#include <asm/cputype.h>
66 66
67/*
68 * CPU Stepping CPU_ID JTAG_ID
69 *
70 * PXA210 B0 0x69052922 0x2926C013
71 * PXA210 B1 0x69052923 0x3926C013
72 * PXA210 B2 0x69052924 0x4926C013
73 * PXA210 C0 0x69052D25 0x5926C013
74 *
75 * PXA250 A0 0x69052100 0x09264013
76 * PXA250 A1 0x69052101 0x19264013
77 * PXA250 B0 0x69052902 0x29264013
78 * PXA250 B1 0x69052903 0x39264013
79 * PXA250 B2 0x69052904 0x49264013
80 * PXA250 C0 0x69052D05 0x59264013
81 *
82 * PXA255 A0 0x69052D06 0x69264013
83 *
84 * PXA26x A0 0x69052903 0x39264013
85 * PXA26x B0 0x69052D05 0x59264013
86 *
87 * PXA27x A0 0x69054110 0x09265013
88 * PXA27x A1 0x69054111 0x19265013
89 * PXA27x B0 0x69054112 0x29265013
90 * PXA27x B1 0x69054113 0x39265013
91 * PXA27x C0 0x69054114 0x49265013
92 * PXA27x C5 0x69054117 0x79265013
93 *
94 * PXA30x A0 0x69056880 0x0E648013
95 * PXA30x A1 0x69056881 0x1E648013
96 * PXA31x A0 0x69056890 0x0E649013
97 * PXA31x A1 0x69056891 0x1E649013
98 * PXA31x A2 0x69056892 0x2E649013
99 * PXA32x B1 0x69056825 0x5E642013
100 * PXA32x B2 0x69056826 0x6E642013
101 *
102 * PXA930 B0 0x69056835 0x5E643013
103 * PXA930 B1 0x69056837 0x7E643013
104 * PXA930 B2 0x69056838 0x8E643013
105 */
67#ifdef CONFIG_PXA25x 106#ifdef CONFIG_PXA25x
68#define __cpu_is_pxa21x(id) \ 107#define __cpu_is_pxa210(id) \
69 ({ \ 108 ({ \
70 unsigned int _id = (id) >> 4 & 0xf3f; \ 109 unsigned int _id = (id) & 0xf3f0; \
71 _id == 0x212; \ 110 _id == 0x2120; \
72 }) 111 })
73 112
74#define __cpu_is_pxa255(id) \ 113#define __cpu_is_pxa250(id) \
75 ({ \ 114 ({ \
76 unsigned int _id = (id) >> 4 & 0xfff; \ 115 unsigned int _id = (id) & 0xf3ff; \
77 _id == 0x2d0; \ 116 _id <= 0x2105; \
78 }) 117 })
118
119#define __cpu_is_pxa255(id) \
120 ({ \
121 unsigned int _id = (id) & 0xffff; \
122 _id == 0x2d06; \
123 })
79 124
80#define __cpu_is_pxa25x(id) \ 125#define __cpu_is_pxa25x(id) \
81 ({ \ 126 ({ \
82 unsigned int _id = (id) >> 4 & 0xfff; \ 127 unsigned int _id = (id) & 0xf300; \
83 _id == 0x2d0 || _id == 0x290; \ 128 _id == 0x2100; \
84 }) 129 })
85#else 130#else
86#define __cpu_is_pxa21x(id) (0) 131#define __cpu_is_pxa210(id) (0)
132#define __cpu_is_pxa250(id) (0)
87#define __cpu_is_pxa255(id) (0) 133#define __cpu_is_pxa255(id) (0)
88#define __cpu_is_pxa25x(id) (0) 134#define __cpu_is_pxa25x(id) (0)
89#endif 135#endif
@@ -138,9 +184,14 @@
138#define __cpu_is_pxa930(id) (0) 184#define __cpu_is_pxa930(id) (0)
139#endif 185#endif
140 186
141#define cpu_is_pxa21x() \ 187#define cpu_is_pxa210() \
142 ({ \ 188 ({ \
143 __cpu_is_pxa21x(read_cpuid_id()); \ 189 __cpu_is_pxa210(read_cpuid_id()); \
190 })
191
192#define cpu_is_pxa250() \
193 ({ \
194 __cpu_is_pxa250(read_cpuid_id()); \
144 }) 195 })
145 196
146#define cpu_is_pxa255() \ 197#define cpu_is_pxa255() \
@@ -153,6 +204,8 @@
153 __cpu_is_pxa25x(read_cpuid_id()); \ 204 __cpu_is_pxa25x(read_cpuid_id()); \
154 }) 205 })
155 206
207extern int cpu_is_pxa26x(void);
208
156#define cpu_is_pxa27x() \ 209#define cpu_is_pxa27x() \
157 ({ \ 210 ({ \
158 __cpu_is_pxa27x(read_cpuid_id()); \ 211 __cpu_is_pxa27x(read_cpuid_id()); \
diff --git a/arch/arm/mach-pxa/include/mach/i2c.h b/arch/arm/mach-pxa/include/mach/i2c.h
index 80596b013443..1a9f65e6ec0f 100644
--- a/arch/arm/mach-pxa/include/mach/i2c.h
+++ b/arch/arm/mach-pxa/include/mach/i2c.h
@@ -65,13 +65,18 @@ struct i2c_pxa_platform_data {
65 unsigned int slave_addr; 65 unsigned int slave_addr;
66 struct i2c_slave_client *slave; 66 struct i2c_slave_client *slave;
67 unsigned int class; 67 unsigned int class;
68 int use_pio; 68 unsigned int use_pio :1;
69 unsigned int fast_mode :1;
69}; 70};
70 71
71extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info); 72extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
72 73
73#ifdef CONFIG_PXA27x 74#ifdef CONFIG_PXA27x
74extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info); 75extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info);
76#endif
77
78#ifdef CONFIG_PXA3xx
79extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info);
75#endif 80#endif
76 81
77#endif 82#endif
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 108b5db9b2af..9c163e19ada9 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -11,7 +11,14 @@
11 */ 11 */
12 12
13 13
14#define PXA_IRQ(x) (x) 14#ifdef CONFIG_PXA_HAVE_ISA_IRQS
15#define PXA_ISA_IRQ(x) (x)
16#define PXA_ISA_IRQ_NUM (16)
17#else
18#define PXA_ISA_IRQ_NUM (0)
19#endif
20
21#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
15 22
16#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 23#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
17#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ 24#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
@@ -73,7 +80,7 @@
73#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ 80#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
74#endif 81#endif
75 82
76#define PXA_GPIO_IRQ_BASE (64) 83#define PXA_GPIO_IRQ_BASE PXA_IRQ(64)
77#define PXA_GPIO_IRQ_NUM (128) 84#define PXA_GPIO_IRQ_NUM (128)
78 85
79#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) 86#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
@@ -178,13 +185,7 @@
178#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) 185#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
179#elif defined(CONFIG_SHARP_LOCOMO) 186#elif defined(CONFIG_SHARP_LOCOMO)
180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 187#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
181#elif defined(CONFIG_ARCH_LUBBOCK) || \ 188#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
182 defined(CONFIG_MACH_LOGICPD_PXA270) || \
183 defined(CONFIG_MACH_TOSA) || \
184 defined(CONFIG_MACH_MAINSTONE) || \
185 defined(CONFIG_MACH_PCM027) || \
186 defined(CONFIG_ARCH_PXA_ESERIES) || \
187 defined(CONFIG_MACH_MAGICIAN)
188#define NR_IRQS (IRQ_BOARD_END) 189#define NR_IRQS (IRQ_BOARD_END)
189#elif defined(CONFIG_MACH_ZYLONITE) 190#elif defined(CONFIG_MACH_ZYLONITE)
190#define NR_IRQS (IRQ_BOARD_START + 32) 191#define NR_IRQS (IRQ_BOARD_START + 32)
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 79d209b826f4..5c4e320c1437 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -3,4 +3,6 @@
3 3
4#define LITTLETON_ETH_PHYS 0x30000000 4#define LITTLETON_ETH_PHYS 0x30000000
5 5
6#define LITTLETON_GPIO_LCD_CS (17)
7
6#endif /* __ASM_ARCH_ZYLONITE_H */ 8#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 552eb7fa6579..59aef89808d6 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -40,11 +40,11 @@
40#define NODE_MEM_SIZE_BITS 26 40#define NODE_MEM_SIZE_BITS 26
41 41
42#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 42#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
43void cmx270_pci_adjust_zones(int node, unsigned long *size, 43void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
44 unsigned long *holes); 44 unsigned long *holes);
45 45
46#define arch_adjust_zones(node, size, holes) \ 46#define arch_adjust_zones(node, size, holes) \
47 cmx270_pci_adjust_zones(node, size, holes) 47 cmx2xx_pci_adjust_zones(node, size, holes)
48 48
49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) 49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
50#endif 50#endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index 6c8e72238bfd..617cab2cc8d0 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -17,7 +17,7 @@
17 17
18/* Crystal and Clock Signals */ 18/* Crystal and Clock Signals */
19#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) 19#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
20#define GPIO70_RTC_CLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW) 20#define GPIO70_RTCCLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
21#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW) 21#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW)
22#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) 22#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
23#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW) 23#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
@@ -156,6 +156,6 @@
156#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) 156#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
157#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) 157#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) 158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
159#define GPIO77_LCD_ACBIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) 159#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
160 160
161#endif /* __ASM_ARCH_MFP_PXA25X_H */ 161#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
index 74990510cf34..67f8385ea548 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -257,10 +257,10 @@
257#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) 257#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
258#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) 258#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
259 259
260#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT) 260#define GPIO69_SSP3_SCLK MFP_CFG_X(GPIO69, AF2, DS08X, FLOAT)
261#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW) 261#define GPIO70_SSP3_FRM MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
262#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT) 262#define GPIO89_SSP3_SCLK MFP_CFG_X(GPIO89, AF1, DS08X, FLOAT)
263#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW) 263#define GPIO90_SSP3_FRM MFP_CFG_X(GPIO90, AF1, DS08X, DRIVE_LOW)
264#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) 264#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
265#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) 265#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
266#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) 266#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h
index 8769567b389b..482185053a92 100644
--- a/arch/arm/mach-pxa/include/mach/mfp.h
+++ b/arch/arm/mach-pxa/include/mach/mfp.h
@@ -274,12 +274,13 @@ typedef unsigned long mfp_cfg_t;
274#define MFP_DS_MASK (0x7 << 13) 274#define MFP_DS_MASK (0x7 << 13)
275#define MFP_DS(x) (((x) >> 13) & 0x7) 275#define MFP_DS(x) (((x) >> 13) & 0x7)
276 276
277#define MFP_LPM_INPUT (0x0 << 16) 277#define MFP_LPM_DEFAULT (0x0 << 16)
278#define MFP_LPM_DRIVE_LOW (0x1 << 16) 278#define MFP_LPM_DRIVE_LOW (0x1 << 16)
279#define MFP_LPM_DRIVE_HIGH (0x2 << 16) 279#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
280#define MFP_LPM_PULL_LOW (0x3 << 16) 280#define MFP_LPM_PULL_LOW (0x3 << 16)
281#define MFP_LPM_PULL_HIGH (0x4 << 16) 281#define MFP_LPM_PULL_HIGH (0x4 << 16)
282#define MFP_LPM_FLOAT (0x5 << 16) 282#define MFP_LPM_FLOAT (0x5 << 16)
283#define MFP_LPM_INPUT (0x6 << 16)
283#define MFP_LPM_STATE_MASK (0x7 << 16) 284#define MFP_LPM_STATE_MASK (0x7 << 16)
284#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) 285#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
285 286
@@ -297,7 +298,7 @@ typedef unsigned long mfp_cfg_t;
297#define MFP_PULL_MASK (0x3 << 21) 298#define MFP_PULL_MASK (0x3 << 21)
298#define MFP_PULL(x) (((x) >> 21) & 0x3) 299#define MFP_PULL(x) (((x) >> 21) & 0x3)
299 300
300#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\ 301#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
301 MFP_LPM_EDGE_NONE | MFP_PULL_NONE) 302 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
302 303
303#define MFP_CFG(pin, af) \ 304#define MFP_CFG(pin, af) \
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
new file mode 100644
index 000000000000..8483cb511831
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -0,0 +1,67 @@
1#ifndef _MIOA701_H_
2#define _MIOA701_H_
3
4#define MIO_CFG_IN(pin, af) \
5 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
6 (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN))
7
8#define MIO_CFG_OUT(pin, af, state) \
9 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
11
12/* Global GPIOs */
13#define GPIO9_CHARGE_nEN 9
14#define GPIO18_POWEROFF 18
15#define GPIO87_LCD_POWER 87
16
17/* USB */
18#define GPIO13_USB_DETECT 13
19#define GPIO22_USB_ENABLE 22
20
21/* SDIO bits */
22#define GPIO78_SDIO_RO 78
23#define GPIO15_SDIO_INSERT 15
24#define GPIO91_SDIO_EN 91
25
26/* Bluetooth */
27#define GPIO83_BT_ON 83
28
29/* GPS */
30#define GPIO23_GPS_UNKNOWN1 23
31#define GPIO26_GPS_ON 26
32#define GPIO27_GPS_RESET 27
33#define GPIO106_GPS_UNKNOWN2 106
34#define GPIO107_GPS_UNKNOWN3 107
35
36/* GSM */
37#define GPIO24_GSM_MOD_RESET_CMD 24
38#define GPIO88_GSM_nMOD_ON_CMD 88
39#define GPIO90_GSM_nMOD_OFF_CMD 90
40#define GPIO114_GSM_nMOD_DTE_UART_STATE 114
41#define GPIO25_GSM_MOD_ON_STATE 25
42#define GPIO113_GSM_EVENT 113
43
44/* SOUND */
45#define GPIO12_HPJACK_INSERT 12
46
47/* LEDS */
48#define GPIO10_LED_nCharging 10
49#define GPIO97_LED_nBlue 97
50#define GPIO98_LED_nOrange 98
51#define GPIO82_LED_nVibra 82
52#define GPIO115_LED_nKeyboard 115
53
54/* Keyboard */
55#define GPIO0_KEY_POWER 0
56#define GPIO93_KEY_VOLUME_UP 93
57#define GPIO94_KEY_VOLUME_DOWN 94
58
59extern struct input_dev *mioa701_evdev;
60extern void mioa701_gpio_lpm_set(unsigned long mfp_pin);
61
62/* Assembler externals mioa701_bootresume.S */
63extern u32 mioa701_bootstrap;
64extern u32 mioa701_jumpaddr;
65extern u32 mioa701_bootstrap_lg;
66
67#endif /* _MIOA701_H */
diff --git a/arch/arm/mach-pxa/include/mach/ohci.h b/arch/arm/mach-pxa/include/mach/ohci.h
index e848a47128cd..95b6e2a6e514 100644
--- a/arch/arm/mach-pxa/include/mach/ohci.h
+++ b/arch/arm/mach-pxa/include/mach/ohci.h
@@ -7,6 +7,22 @@ struct pxaohci_platform_data {
7 int (*init)(struct device *); 7 int (*init)(struct device *);
8 void (*exit)(struct device *); 8 void (*exit)(struct device *);
9 9
10 unsigned long flags;
11#define ENABLE_PORT1 (1 << 0)
12#define ENABLE_PORT2 (1 << 1)
13#define ENABLE_PORT3 (1 << 2)
14#define ENABLE_PORT_ALL (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3)
15
16#define POWER_SENSE_LOW (1 << 3)
17#define POWER_CONTROL_LOW (1 << 4)
18#define NO_OC_PROTECTION (1 << 5)
19#define OC_MODE_GLOBAL (0 << 6)
20#define OC_MODE_PERPORT (1 << 6)
21
22 int power_on_delay; /* Power On to Power Good time - in ms
23 * HCD must wait for this duration before
24 * accessing a powered on port
25 */
10 int port_mode; 26 int port_mode;
11#define PMM_NPS_MODE 1 27#define PMM_NPS_MODE 1
12#define PMM_GLOBAL_MODE 2 28#define PMM_GLOBAL_MODE 2
diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h
new file mode 100644
index 000000000000..5032307ebf7d
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmz72.h
@@ -0,0 +1,80 @@
1/*
2 * GPIOs and interrupts for Palm Zire72 Handheld Computer
3 *
4 * Authors: Alex Osborne <bobofdoom@gmail.com>
5 * Jan Herman <2hp@seznam.cz>
6 * Sergey Lapin <slapin@ossfans.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef _INCLUDE_PALMZ72_H_
15#define _INCLUDE_PALMZ72_H_
16
17/* Power and control */
18#define GPIO_NR_PALMZ72_GPIO_RESET 1
19#define GPIO_NR_PALMZ72_POWER_DETECT 0
20
21/* SD/MMC */
22#define GPIO_NR_PALMZ72_SD_DETECT_N 14
23#define GPIO_NR_PALMZ72_SD_POWER_N 98
24#define GPIO_NR_PALMZ72_SD_RO 115
25
26/* Touchscreen */
27#define GPIO_NR_PALMZ72_WM9712_IRQ 27
28
29/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
30#define GPIO_NR_PALMZ72_IR_DISABLE 49
31
32/* USB */
33#define GPIO_NR_PALMZ72_USB_DETECT_N 15
34#define GPIO_NR_PALMZ72_USB_POWER 95
35#define GPIO_NR_PALMZ72_USB_PULLUP 12
36
37/* LCD/Backlight */
38#define GPIO_NR_PALMZ72_BL_POWER 20
39#define GPIO_NR_PALMZ72_LCD_POWER 96
40
41/* LED */
42#define GPIO_NR_PALMZ72_LED_GREEN 88
43
44/* Bluetooth */
45#define GPIO_NR_PALMZ72_BT_POWER 17
46#define GPIO_NR_PALMZ72_BT_RESET 83
47
48/** Initial values **/
49
50/* Battery */
51#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
52#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
53#define PALMZ72_BAT_MAX_CURRENT 0 /* unknokn */
54#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */
55#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */
56#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */
57#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */
58
59/* Backlight */
60#define PALMZ72_MAX_INTENSITY 0xFE
61#define PALMZ72_DEFAULT_INTENSITY 0x7E
62#define PALMZ72_LIMIT_MASK 0x7F
63#define PALMZ72_PRESCALER 0x3F
64#define PALMZ72_PERIOD_NS 3500
65
66#ifdef CONFIG_PM
67struct palmz72_resume_info {
68 u32 magic0; /* 0x0 */
69 u32 magic1; /* 0x4 */
70 u32 resume_addr; /* 0x8 */
71 u32 pad[11]; /* 0xc..0x37 */
72 u32 arm_control; /* 0x38 */
73 u32 aux_control; /* 0x3c */
74 u32 ttb; /* 0x40 */
75 u32 domain_access; /* 0x44 */
76 u32 process_id; /* 0x48 */
77};
78#endif
79#endif
80
diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index 261e5bc958db..83342469acac 100644
--- a/arch/arm/mach-pxa/include/mach/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
@@ -15,6 +15,8 @@ struct pxa_cpu_pm_fns {
15 void (*restore)(unsigned long *); 15 void (*restore)(unsigned long *);
16 int (*valid)(suspend_state_t state); 16 int (*valid)(suspend_state_t state);
17 void (*enter)(suspend_state_t state); 17 void (*enter)(suspend_state_t state);
18 int (*prepare)(void);
19 void (*finish)(void);
18}; 20};
19 21
20extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; 22extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 67debc47e8c6..0b3e6d051c64 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -23,6 +23,7 @@
23#define POODLE_GPIO_AC_IN (1) 23#define POODLE_GPIO_AC_IN (1)
24#define POODLE_GPIO_CO 16 24#define POODLE_GPIO_CO 16
25#define POODLE_GPIO_TP_INT (5) 25#define POODLE_GPIO_TP_INT (5)
26#define POODLE_GPIO_TP_CS (24)
26#define POODLE_GPIO_WAKEUP (11) /* change battery */ 27#define POODLE_GPIO_WAKEUP (11) /* change battery */
27#define POODLE_GPIO_GA_INT (10) 28#define POODLE_GPIO_GA_INT (10)
28#define POODLE_GPIO_IR_ON (22) 29#define POODLE_GPIO_IR_ON (22)
@@ -70,6 +71,14 @@
70#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) 71#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
71#define POODLE_SCOOP_IO_OUT ( 0 ) 72#define POODLE_SCOOP_IO_OUT ( 0 )
72 73
74#define POODLE_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO)
75#define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0)
76#define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2)
77#define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7)
78#define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9)
79#define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10)
80#define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11)
81
73#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8) 82#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8)
74#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10) 83#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10)
75#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11) 84#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11)
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index 12288ca3cbb2..15295d960000 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -69,30 +69,18 @@
69/* 69/*
70 * DMA Controller 70 * DMA Controller
71 */ 71 */
72
73#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
74#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
75#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
76#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
77#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
78#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
79#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
80#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
81#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
82#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
83#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
84#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
85#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
86#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
87#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
88#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
89
90#define DCSR(x) __REG2(0x40000000, (x) << 2) 72#define DCSR(x) __REG2(0x40000000, (x) << 2)
91 73
92#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ 74#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
93#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ 75#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
94#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ 76#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
95#ifdef CONFIG_PXA27x 77#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
78#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
79#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
80#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
81#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
82
83#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
96#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ 84#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
97#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ 85#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
98#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ 86#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
@@ -101,11 +89,6 @@
101#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ 89#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
102#define DCSR_EORINTR (1 << 9) /* The end of Receive */ 90#define DCSR_EORINTR (1 << 9) /* The end of Receive */
103#endif 91#endif
104#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
105#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
106#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
107#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
108#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
109 92
110#define DALGN __REG(0x400000a0) /* DMA Alignment Register */ 93#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
111#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ 94#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
@@ -114,145 +97,9 @@
114 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ 97 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
115 &__REG2(0x40001100, ((n) & 0x3f) << 2))) 98 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
116 99
117#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
118#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
119#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
120#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
121#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
122#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
123#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
124#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
125#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
126#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
127#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
128#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
129#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
130#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
131#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
132#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
133#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
134#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
135#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
136#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
137#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
138#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
139#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
140#define DRCMR23 __REG(0x4000015c) /* Reserved */
141#define DRCMR24 __REG(0x40000160) /* Reserved */
142#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
143#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
144#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
145#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
146#define DRCMR29 __REG(0x40000174) /* Reserved */
147#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
148#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
149#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
150#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
151#define DRCMR34 __REG(0x40000188) /* Reserved */
152#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
153#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
154#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
155#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
156#define DRCMR39 __REG(0x4000019C) /* Reserved */
157#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
158#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
159#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
160#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
161#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
162
163#define DRCMRRXSADR DRCMR2
164#define DRCMRTXSADR DRCMR3
165#define DRCMRRXBTRBR DRCMR4
166#define DRCMRTXBTTHR DRCMR5
167#define DRCMRRXFFRBR DRCMR6
168#define DRCMRTXFFTHR DRCMR7
169#define DRCMRRXMCDR DRCMR8
170#define DRCMRRXMODR DRCMR9
171#define DRCMRTXMODR DRCMR10
172#define DRCMRRXPCDR DRCMR11
173#define DRCMRTXPCDR DRCMR12
174#define DRCMRRXSSDR DRCMR13
175#define DRCMRTXSSDR DRCMR14
176#define DRCMRRXSS2DR DRCMR15
177#define DRCMRTXSS2DR DRCMR16
178#define DRCMRRXICDR DRCMR17
179#define DRCMRTXICDR DRCMR18
180#define DRCMRRXSTRBR DRCMR19
181#define DRCMRTXSTTHR DRCMR20
182#define DRCMRRXMMC DRCMR21
183#define DRCMRTXMMC DRCMR22
184#define DRCMRRXSS3DR DRCMR66
185#define DRCMRTXSS3DR DRCMR67
186#define DRCMRUDC(x) DRCMR((x) + 24)
187
188#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ 100#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
189#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ 101#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
190 102
191#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
192#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
193#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
194#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
195#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
196#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
197#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
198#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
199#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
200#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
201#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
202#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
203#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
204#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
205#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
206#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
207#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
208#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
209#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
210#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
211#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
212#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
213#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
214#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
215#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
216#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
217#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
218#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
219#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
220#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
221#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
222#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
223#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
224#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
225#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
226#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
227#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
228#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
229#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
230#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
231#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
232#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
233#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
234#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
235#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
236#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
237#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
238#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
239#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
240#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
241#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
242#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
243#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
244#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
245#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
246#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
247#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
248#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
249#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
250#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
251#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
252#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
253#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
254#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
255
256#define DDADR(x) __REG2(0x40000200, (x) << 4) 103#define DDADR(x) __REG2(0x40000200, (x) << 4)
257#define DSADR(x) __REG2(0x40000204, (x) << 4) 104#define DSADR(x) __REG2(0x40000204, (x) << 4)
258#define DTADR(x) __REG2(0x40000208, (x) << 4) 105#define DTADR(x) __REG2(0x40000208, (x) << 4)
@@ -418,91 +265,13 @@
418 265
419 266
420/* 267/*
421 * I2C registers 268 * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
422 */ 269 */
423 270
424#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
425#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
426#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
427#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
428#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
429
430#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
431#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
432#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
433#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
434#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
435
436#define ICR_START (1 << 0) /* start bit */
437#define ICR_STOP (1 << 1) /* stop bit */
438#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
439#define ICR_TB (1 << 3) /* transfer byte bit */
440#define ICR_MA (1 << 4) /* master abort */
441#define ICR_SCLE (1 << 5) /* master clock enable */
442#define ICR_IUE (1 << 6) /* unit enable */
443#define ICR_GCD (1 << 7) /* general call disable */
444#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
445#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
446#define ICR_BEIE (1 << 10) /* enable bus error ints */
447#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
448#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
449#define ICR_SADIE (1 << 13) /* slave address detected int enable */
450#define ICR_UR (1 << 14) /* unit reset */
451
452#define ISR_RWM (1 << 0) /* read/write mode */
453#define ISR_ACKNAK (1 << 1) /* ack/nak status */
454#define ISR_UB (1 << 2) /* unit busy */
455#define ISR_IBB (1 << 3) /* bus busy */
456#define ISR_SSD (1 << 4) /* slave stop detected */
457#define ISR_ALD (1 << 5) /* arbitration loss detected */
458#define ISR_ITE (1 << 6) /* tx buffer empty */
459#define ISR_IRF (1 << 7) /* rx buffer full */
460#define ISR_GCAD (1 << 8) /* general call address detected */
461#define ISR_SAD (1 << 9) /* slave address detected */
462#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
463
464
465/* 271/*
466 * Serial Audio Controller 272 * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
467 */ 273 */
468 274
469#define SACR0 __REG(0x40400000) /* Global Control Register */
470#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
471#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
472#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
473#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
474#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
475#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
476
477#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
478#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
479#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
480#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
481#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
482#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
483#define SACR0_ENB (1 << 0) /* Enable I2S Link */
484#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
485#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
486#define SACR1_DREC (1 << 3) /* Disable Recording Function */
487#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
488
489#define SASR0_I2SOFF (1 << 7) /* Controller Status */
490#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
491#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
492#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
493#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
494#define SASR0_BSY (1 << 2) /* I2S Busy */
495#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
496#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
497
498#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
499#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
500
501#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
502#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
503#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
504#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
505
506/* 275/*
507 * AC97 Controller registers 276 * AC97 Controller registers
508 */ 277 */
@@ -989,77 +758,6 @@
989 758
990#endif 759#endif
991 760
992#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
993/*
994 * UHC: USB Host Controller (OHCI-like) register definitions
995 */
996#define UHC_BASE_PHYS (0x4C000000)
997#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
998#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
999#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
1000#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
1001#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
1002#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
1003#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
1004#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
1005#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
1006#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
1007#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
1008#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
1009#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
1010#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
1011#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
1012#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
1013#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
1014#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
1015
1016#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
1017#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
1018
1019#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
1020#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
1021#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
1022#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
1023#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
1024
1025#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
1026#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
1027#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
1028#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
1029#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
1030#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
1031#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
1032#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
1033#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
1034#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
1035
1036#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
1037#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
1038#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
1039#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
1040#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
1041#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
1042#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
1043#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
1044#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
1045#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
1046#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
1047#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
1048
1049#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
1050#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
1051#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
1052#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
1053#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
1054#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
1055 Interrupt Enable*/
1056#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
1057#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
1058
1059#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
1060
1061#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
1062
1063/* PWRMODE register M field values */ 761/* PWRMODE register M field values */
1064 762
1065#define PWRMODE_IDLE 0x1 763#define PWRMODE_IDLE 0x1
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 39eb68319e28..b1fcd10ab6c6 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,28 @@
131#define CKENB __REG(0x41340010) /* B Clock Enable Register */ 131#define CKENB __REG(0x41340010) /* B Clock Enable Register */
132#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ 132#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
133 133
134#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */
135#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */
136#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */
137#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
138#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
139
140#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */
141#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */
142#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */
143#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
144#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
145#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
146#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */
147
148#define ACCR_SMCFS(x) (((x) & 0x7) << 23)
149#define ACCR_SFLFS(x) (((x) & 0x3) << 18)
150#define ACCR_XSPCLK(x) (((x) & 0x3) << 16)
151#define ACCR_HSS(x) (((x) & 0x3) << 14)
152#define ACCR_DMCFS(x) (((x) & 0x3) << 12)
153#define ACCR_XN(x) (((x) & 0x7) << 8)
154#define ACCR_XL(x) ((x) & 0x1f)
155
134/* 156/*
135 * Clock Enable Bit 157 * Clock Enable Bit
136 */ 158 */
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index bd14365f7ed5..31ac26b55bc1 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -16,6 +16,7 @@
16#endif 16#endif
17 17
18#include <linux/fb.h> 18#include <linux/fb.h>
19#include <linux/gpio.h>
19 20
20/* Spitz/Akita GPIOs */ 21/* Spitz/Akita GPIOs */
21 22
@@ -100,13 +101,24 @@
100#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ 101#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
101#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ 102#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
102 103
103#define SPITZ_SCP_IO_DIR (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ 104#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
104 SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \ 105 SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \
105 SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) 106 SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
106#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) 107#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
107#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) 108#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
108#define SPITZ_SCP_SUS_SET 0 109#define SPITZ_SCP_SUS_SET 0
109 110
111#define SPITZ_SCP_GPIO_BASE (NR_BUILTIN_GPIO)
112#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0)
113#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1)
114#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2)
115#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3)
116#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4)
117#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5)
118#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6)
119#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7)
120#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8)
121
110/* Spitz Scoop Device (No. 2) GPIOs */ 122/* Spitz Scoop Device (No. 2) GPIOs */
111/* Suspend States in comments */ 123/* Suspend States in comments */
112#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ 124#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
@@ -119,15 +131,36 @@
119#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ 131#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
120#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ 132#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
121 133
122#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ 134#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
123 SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ 135 SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
124 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) 136 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
125 137
126#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) 138#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
127#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ 139#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
128 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) 140 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
129#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) 141#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
130 142
143#define SPITZ_SCP2_GPIO_BASE (NR_BUILTIN_GPIO + 12)
144#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0)
145#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1
146#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2)
147#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3)
148#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4)
149#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5)
150#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6)
151#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7)
152#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8)
153
154/* Akita IO Expander GPIOs */
155#define AKITA_IOEXP_GPIO_BASE (NR_BUILTIN_GPIO + 12)
156#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0)
157#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1)
158#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2)
159#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3)
160#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4)
161#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5)
162#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6)
163#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7)
131 164
132/* Spitz IRQ Definitions */ 165/* Spitz IRQ Definitions */
133 166
@@ -154,5 +187,4 @@
154 */ 187 */
155extern struct platform_device spitzscoop_device; 188extern struct platform_device spitzscoop_device;
156extern struct platform_device spitzscoop2_device; 189extern struct platform_device spitzscoop2_device;
157extern struct platform_device spitzssp_device;
158extern struct sharpsl_charger_machinfo spitz_pm_machinfo; 190extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h
index a012882c9ee6..cb5cb766f0f1 100644
--- a/arch/arm/mach-pxa/include/mach/ssp.h
+++ b/arch/arm/mach-pxa/include/mach/ssp.h
@@ -20,6 +20,7 @@
20#define __ASM_ARCH_SSP_H 20#define __ASM_ARCH_SSP_H
21 21
22#include <linux/list.h> 22#include <linux/list.h>
23#include <linux/io.h>
23 24
24enum pxa_ssp_type { 25enum pxa_ssp_type {
25 SSP_UNDEFINED = 0, 26 SSP_UNDEFINED = 0,
@@ -78,6 +79,29 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
78int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); 79int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
79void ssp_exit(struct ssp_dev *dev); 80void ssp_exit(struct ssp_dev *dev);
80 81
82/**
83 * ssp_write_reg - Write to a SSP register
84 *
85 * @dev: SSP device to access
86 * @reg: Register to write to
87 * @val: Value to be written.
88 */
89static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
90{
91 __raw_writel(val, dev->mmio_base + reg);
92}
93
94/**
95 * ssp_read_reg - Read from a SSP register
96 *
97 * @dev: SSP device to access
98 * @reg: Register to read from
99 */
100static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
101{
102 return __raw_readl(dev->mmio_base + reg);
103}
104
81struct ssp_device *ssp_request(int port, const char *label); 105struct ssp_device *ssp_request(int port, const char *label);
82void ssp_free(struct ssp_device *); 106void ssp_free(struct ssp_device *);
83#endif /* __ASM_ARCH_SSP_H */ 107#endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index 641d0ec110bb..903e1a2e6641 100644
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
@@ -17,11 +17,16 @@
17#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ 17#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
18#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ 18#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
19 19
20#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */ 20 /* Logic on ConXS-board CSFR register*/
21#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */ 21#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS)
22#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/ 22 /* Logic on ConXS-board BOCR register*/
23#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/ 23#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000)
24#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/ 24 /* Logic on ConXS-board IRCR register*/
25#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000)
26 /* Logic on ConXS-board UPSR register*/
27#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000)
28 /* Logic on ConXS-board DICR register*/
29#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000)
25 30
26/* virtual memory regions */ 31/* virtual memory regions */
27#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ 32#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
@@ -54,6 +59,15 @@
54#define GPIO_MMC_DET 12 59#define GPIO_MMC_DET 12
55#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) 60#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
56 61
62/* DOC NAND chip */
63#define GPIO_DOC_LOCK 94
64#define GPIO_DOC_IRQ 93
65#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ)
66
67/* SPI interface */
68#define GPIO_SPI 53
69#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI)
70
57/* LEDS using tx2 / rx2 */ 71/* LEDS using tx2 / rx2 */
58#define GPIO_SYS_BUSY_LED 46 72#define GPIO_SYS_BUSY_LED 46
59#define GPIO_HEARTBEAT_LED 47 73#define GPIO_HEARTBEAT_LED 47
@@ -62,24 +76,66 @@
62#define GPIO_PIC 0 76#define GPIO_PIC 0
63#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) 77#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
64 78
65#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) 79#ifdef CONFIG_MACH_TRIZEPS_CONXS
66#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) 80/* for CONXS base board define these registers */
81#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
82#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
67 83
68#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) 84#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
69#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) 85#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
70 86
71#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) 87#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
72#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) 88#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
89
90#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
91#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
73 92
74#ifndef __ASSEMBLY__ 93#ifndef __ASSEMBLY__
75#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000))) 94static inline unsigned short CFSR_readw(void)
76#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000))) 95{
77#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000))) 96 /* [Compact Flash Status Register] is read only */
97 return *((unsigned short *)CFSR_P2V(0x0C000000));
98}
99static inline void BCR_writew(unsigned short value)
100{
101 /* [Board Control Regsiter] is write only */
102 *((unsigned short *)BCR_P2V(0x0E000000)) = value;
103}
104static inline void DCR_writew(unsigned short value)
105{
106 /* [Display Control Register] is write only */
107 *((unsigned short *)DCR_P2V(0x0E000000)) = value;
108}
109static inline void IRCR_writew(unsigned short value)
110{
111 /* [InfraRed data Control Register] is write only */
112 *((unsigned short *)IRCR_P2V(0x0E000000)) = value;
113}
78#else 114#else
79#define ConXS_CFSR CFSR_P2V(0x0C000000) 115#define ConXS_CFSR CFSR_P2V(0x0C000000)
80#define ConXS_BCR BCR_P2V(0x0E000000) 116#define ConXS_BCR BCR_P2V(0x0E000000)
81#define ConXS_DCR DCR_P2V(0x0F800000) 117#define ConXS_DCR DCR_P2V(0x0F800000)
118#define ConXS_IRCR IRCR_P2V(0x0F800000)
82#endif 119#endif
120#else
121/* for whatever baseboard define function registers */
122static inline unsigned short CFSR_readw(void)
123{
124 return 0;
125}
126static inline void BCR_writew(unsigned short value)
127{
128 ;
129}
130static inline void DCR_writew(unsigned short value)
131{
132 ;
133}
134static inline void IRCR_writew(unsigned short value)
135{
136 ;
137}
138#endif /* CONFIG_MACH_TRIZEPS_CONXS */
83 139
84#define ConXS_CFSR_BVD_MASK 0x0003 140#define ConXS_CFSR_BVD_MASK 0x0003
85#define ConXS_CFSR_BVD1 (1 << 0) 141#define ConXS_CFSR_BVD1 (1 << 0)
diff --git a/arch/arm/mach-pxa/include/mach/viper.h b/arch/arm/mach-pxa/include/mach/viper.h
new file mode 100644
index 000000000000..10988c270ca3
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/viper.h
@@ -0,0 +1,96 @@
1/*
2 * arch/arm/mach-pxa/include/mach/viper.h
3 *
4 * Author: Ian Campbell
5 * Created: Feb 03, 2003
6 * Copyright: Arcom Control Systems.
7 *
8 * Maintained by Marc Zyngier <maz@misterjones.org>
9 * <marc.zyngier@altran.com>
10 *
11 * Created based on lubbock.h:
12 * Author: Nicolas Pitre
13 * Created: Jun 15, 2001
14 * Copyright: MontaVista Software Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef ARCH_VIPER_H
22#define ARCH_VIPER_H
23
24#define VIPER_BOOT_PHYS PXA_CS0_PHYS
25#define VIPER_FLASH_PHYS PXA_CS1_PHYS
26#define VIPER_ETH_PHYS PXA_CS2_PHYS
27#define VIPER_USB_PHYS PXA_CS3_PHYS
28#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS
29#define VIPER_CPLD_PHYS PXA_CS5_PHYS
30
31#define VIPER_CPLD_BASE (0xf0000000)
32#define VIPER_PC104IO_BASE (0xf1000000)
33#define VIPER_USB_BASE (0xf1800000)
34
35#define VIPER_ETH_GPIO (0)
36#define VIPER_CPLD_GPIO (1)
37#define VIPER_USB_GPIO (2)
38#define VIPER_UARTA_GPIO (4)
39#define VIPER_UARTB_GPIO (3)
40#define VIPER_CF_CD_GPIO (32)
41#define VIPER_CF_RDY_GPIO (8)
42#define VIPER_BCKLIGHT_EN_GPIO (9)
43#define VIPER_LCD_EN_GPIO (10)
44#define VIPER_PSU_DATA_GPIO (6)
45#define VIPER_PSU_CLK_GPIO (11)
46#define VIPER_UART_SHDN_GPIO (12)
47#define VIPER_BRIGHTNESS_GPIO (16)
48#define VIPER_PSU_nCS_LD_GPIO (19)
49#define VIPER_UPS_GPIO (20)
50#define VIPER_CF_POWER_GPIO (82)
51#define VIPER_TPM_I2C_SDA_GPIO (26)
52#define VIPER_TPM_I2C_SCL_GPIO (27)
53#define VIPER_RTC_I2C_SDA_GPIO (83)
54#define VIPER_RTC_I2C_SCL_GPIO (84)
55
56#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
57#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
58
59#ifndef __ASSEMBLY__
60# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x)))
61#endif
62
63/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
64
65/* ... Physical addresses */
66#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000)
67#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002)
68#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004)
69#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006)
70#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010)
71#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000)
72#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000)
73
74/* ... Virtual addresses */
75#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
76#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
77#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
78#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
79
80/* Decode VIPER_VERSION register */
81#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7)
82#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3)
83#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7)
84
85/* Interrupt and Configuration Register (VIPER_ICR) */
86/* This is a write only register. Only CF_RST is used under Linux */
87
88extern void viper_cf_rst(int state);
89
90#define VIPER_ICR_RETRIG (1 << 0)
91#define VIPER_ICR_AUTO_CLR (1 << 1)
92#define VIPER_ICR_R_DIS (1 << 2)
93#define VIPER_ICR_CF_RST (1 << 3)
94
95#endif
96
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