Merge branch 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel

14 files changed, 320 insertions, 323 deletions

diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
new file mode 100644
index 000000000000..bfec09b1814b
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -0,0 +1,134 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/balloon3.h
+ *
+ *  Authors:    Nick Bane and Wookey
+ *  Created:    Oct, 2005
+ *  Copyright:  Toby Churchill Ltd
+ *  Cribbed from mainstone.c, by Nicholas Pitre
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ASM_ARCH_BALLOON3_H
+#define ASM_ARCH_BALLOON3_H
+
+enum balloon3_features {
+        BALLOON3_FEATURE_OHCI,
+        BALLOON3_FEATURE_MMC,
+        BALLOON3_FEATURE_CF,
+        BALLOON3_FEATURE_AUDIO,
+        BALLOON3_FEATURE_TOPPOLY,
+};
+
+#define BALLOON3_FPGA_PHYS      PXA_CS4_PHYS
+#define BALLOON3_FPGA_VIRT      (0xf1000000)    /* as per balloon2 */
+#define BALLOON3_FPGA_LENGTH    0x01000000
+
+/* FPGA/CPLD registers */
+#define BALLOON3_PCMCIA0_REG            (BALLOON3_FPGA_VIRT + 0x00e00008)
+/* fixme - same for now */
+#define BALLOON3_PCMCIA1_REG            (BALLOON3_FPGA_VIRT + 0x00e00008)
+#define BALLOON3_NANDIO_IO_REG          (BALLOON3_FPGA_VIRT + 0x00e00000)
+/* fpga/cpld interrupt control register */
+#define BALLOON3_INT_CONTROL_REG        (BALLOON3_FPGA_VIRT + 0x00e0000C)
+#define BALLOON3_NANDIO_CTL2_REG        (BALLOON3_FPGA_VIRT + 0x00e00010)
+#define BALLOON3_NANDIO_CTL_REG         (BALLOON3_FPGA_VIRT + 0x00e00014)
+#define BALLOON3_VERSION_REG            (BALLOON3_FPGA_VIRT + 0x00e0001c)
+
+#define BALLOON3_SAMOSA_ADDR_REG        (BALLOON3_FPGA_VIRT + 0x00c00000)
+#define BALLOON3_SAMOSA_DATA_REG        (BALLOON3_FPGA_VIRT + 0x00c00004)
+#define BALLOON3_SAMOSA_STATUS_REG      (BALLOON3_FPGA_VIRT + 0x00c0001c)
+
+/* GPIOs for irqs */
+#define BALLOON3_GPIO_AUX_NIRQ          (94)
+#define BALLOON3_GPIO_CODEC_IRQ         (95)
+
+/* Timer and Idle LED locations */
+#define BALLOON3_GPIO_LED_NAND          (9)
+#define BALLOON3_GPIO_LED_IDLE          (10)
+
+/* backlight control */
+#define BALLOON3_GPIO_RUN_BACKLIGHT     (99)
+
+#define BALLOON3_GPIO_S0_CD             (105)
+
+/* FPGA Interrupt Mask/Acknowledge Register */
+#define BALLOON3_INT_S0_IRQ             (1 << 0)  /* PCMCIA 0 IRQ */
+#define BALLOON3_INT_S0_STSCHG          (1 << 1)  /* PCMCIA 0 status changed */
+
+/* CF Status Register */
+#define BALLOON3_PCMCIA_nIRQ            (1 << 0)  /* IRQ / ready signal */
+#define BALLOON3_PCMCIA_nSTSCHG_BVD1    (1 << 1)
+                                        /* VDD sense / card status changed */
+
+/* CF control register (write) */
+#define BALLOON3_PCMCIA_RESET           (1 << 0)   /* Card reset signal */
+#define BALLOON3_PCMCIA_ENABLE          (1 << 1)
+#define BALLOON3_PCMCIA_ADD_ENABLE      (1 << 2)
+
+/* CPLD (and FPGA) interface definitions */
+#define CPLD_LCD0_DATA_SET             0x00
+#define CPLD_LCD0_DATA_CLR             0x10
+#define CPLD_LCD0_COMMAND_SET          0x01
+#define CPLD_LCD0_COMMAND_CLR          0x11
+#define CPLD_LCD1_DATA_SET             0x02
+#define CPLD_LCD1_DATA_CLR             0x12
+#define CPLD_LCD1_COMMAND_SET          0x03
+#define CPLD_LCD1_COMMAND_CLR          0x13
+
+#define CPLD_MISC_SET                  0x07
+#define CPLD_MISC_CLR                  0x17
+#define CPLD_MISC_LOON_NRESET_BIT      0
+#define CPLD_MISC_LOON_UNSUSP_BIT      1
+#define CPLD_MISC_RUN_5V_BIT           2
+#define CPLD_MISC_CHG_D0_BIT           3
+#define CPLD_MISC_CHG_D1_BIT           4
+#define CPLD_MISC_DAC_NCS_BIT          5
+
+#define CPLD_LCD_SET                   0x08
+#define CPLD_LCD_CLR                   0x18
+#define CPLD_LCD_BACKLIGHT_EN_0_BIT    0
+#define CPLD_LCD_BACKLIGHT_EN_1_BIT    1
+#define CPLD_LCD_LED_RED_BIT           4
+#define CPLD_LCD_LED_GREEN_BIT         5
+#define CPLD_LCD_NRESET_BIT            7
+
+#define CPLD_LCD_RO_SET                0x09
+#define CPLD_LCD_RO_CLR                0x19
+#define CPLD_LCD_RO_LCD0_nWAIT_BIT     0
+#define CPLD_LCD_RO_LCD1_nWAIT_BIT     1
+
+#define CPLD_SERIAL_SET                0x0a
+#define CPLD_SERIAL_CLR                0x1a
+#define CPLD_SERIAL_GSM_RI_BIT         0
+#define CPLD_SERIAL_GSM_CTS_BIT        1
+#define CPLD_SERIAL_GSM_DTR_BIT        2
+#define CPLD_SERIAL_LPR_CTS_BIT        3
+#define CPLD_SERIAL_TC232_CTS_BIT      4
+#define CPLD_SERIAL_TC232_DSR_BIT      5
+
+#define CPLD_SROUTING_SET              0x0b
+#define CPLD_SROUTING_CLR              0x1b
+#define CPLD_SROUTING_MSP430_LPR       0
+#define CPLD_SROUTING_MSP430_TC232     1
+#define CPLD_SROUTING_MSP430_GSM       2
+#define CPLD_SROUTING_LOON_LPR         (0 << 4)
+#define CPLD_SROUTING_LOON_TC232       (1 << 4)
+#define CPLD_SROUTING_LOON_GSM         (2 << 4)
+
+#define CPLD_AROUTING_SET              0x0c
+#define CPLD_AROUTING_CLR              0x1c
+#define CPLD_AROUTING_MIC2PHONE_BIT    0
+#define CPLD_AROUTING_PHONE2INT_BIT    1
+#define CPLD_AROUTING_PHONE2EXT_BIT    2
+#define CPLD_AROUTING_LOONL2INT_BIT    3
+#define CPLD_AROUTING_LOONL2EXT_BIT    4
+#define CPLD_AROUTING_LOONR2PHONE_BIT  5
+#define CPLD_AROUTING_LOONR2INT_BIT    6
+#define CPLD_AROUTING_LOONR2EXT_BIT    7
+
+extern int balloon3_has(enum balloon3_features feature);
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index a88d7caff0d1..811743c56147 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -23,6 +23,12 @@ static inline void colibri_pxa3xx_init_lcd(int bl_pin) {}
 extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data);
 #endif
 
+#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+extern void colibri_pxa3xx_init_nand(void);
+#else
+static inline void colibri_pxa3xx_init_nand(void) {}
+#endif
+
 /* physical memory regions */
 #define COLIBRI_SDRAM_BASE      0xa0000000      /* SDRAM region */
 
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
index f6b4bf3e73d2..241880608ac6 100644
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -24,34 +24,27 @@
                 mov     \tmp, \tmp, lsr #13
                 and     \tmp, \tmp, #0x7                @ Core G
                 cmp     \tmp, #1
-                bhi     1004f
+                bhi     1002f
 
+                @ Core Generation 1 (PXA25x)
                 mov     \base, #io_p2v(0x40000000)      @ IIR Ctl = 0x40d00000
                 add     \base, \base, #0x00d00000
                 ldr     \irqstat, [\base, #0]           @ ICIP
                 ldr     \irqnr, [\base, #4]             @ ICMR
-                b       1002f
 
-1004:
-                mrc     p6, 0, \irqstat, c6, c0, 0      @ ICIP2
-                mrc     p6, 0, \irqnr, c7, c0, 0        @ ICMR2
                 ands    \irqnr, \irqstat, \irqnr
-                beq     1003f
+                beq     1001f
                 rsb     \irqstat, \irqnr, #0
                 and     \irqstat, \irqstat, \irqnr
                 clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #31
-                add     \irqnr, \irqnr, #(32 + PXA_IRQ(0))
+                rsb     \irqnr, \irqnr, #(31 + PXA_IRQ(0))
                 b       1001f
-1003:
-                mrc     p6, 0, \irqstat, c0, c0, 0      @ ICIP
-                mrc     p6, 0, \irqnr, c1, c0, 0        @ ICMR
 1002:
-                ands    \irqnr, \irqstat, \irqnr
+                @ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
+                mrc     p6, 0, \irqstat, c5, c0, 0      @ ICHP
+                tst     \irqstat, #0x80000000
                 beq     1001f
-                rsb     \irqstat, \irqnr, #0
-                and     \irqstat, \irqstat, \irqnr
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #(31 + PXA_IRQ(0))
+                bic     \irqstat, \irqstat, #0x80000000
+                mov     \irqnr, \irqstat, lsr #16
 1001:
                 .endm
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 16ab79547dae..aa3d9f70a08a 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -197,6 +197,16 @@
 #define __cpu_is_pxa935(id)     (0)
 #endif
 
+#ifdef CONFIG_CPU_PXA950
+#define __cpu_is_pxa950(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                id == 0x697;                            \
+         })
+#else
+#define __cpu_is_pxa950(id)     (0)
+#endif
+
 #define cpu_is_pxa210()                                 \
         ({                                              \
                 __cpu_is_pxa210(read_cpuid_id());       \
@@ -249,6 +259,13 @@
                 __cpu_is_pxa935(id);                    \
          })
 
+#define cpu_is_pxa950()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa950(id);                    \
+         })
+
+
 /*
  * CPUID Core Generation Bit
  * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
diff --git a/arch/arm/mach-pxa/include/mach/irda.h b/arch/arm/mach-pxa/include/mach/irda.h
index 0a50c3c763df..3cd41f77dda4 100644
--- a/arch/arm/mach-pxa/include/mach/irda.h
+++ b/arch/arm/mach-pxa/include/mach/irda.h
@@ -12,6 +12,8 @@ struct pxaficp_platform_data {
         void (*transceiver_mode)(struct device *dev, int mode);
         int (*startup)(struct device *dev);
         void (*shutdown)(struct device *dev);
+        int gpio_pwdown;                /* powerdown GPIO for the IrDA chip */
+        bool gpio_pwdown_inverted;      /* gpio_pwdown is inverted */
 };
 
 extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 6a1d95993342..3677a9af9c87 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -68,9 +68,10 @@
 #ifdef CONFIG_PXA3xx
 #define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request */
 #define IRQ_CIR         PXA_IRQ(34)     /* Consumer IR */
+#define IRQ_COMM_WDT    PXA_IRQ(35)     /* Comm WDT interrupt */
 #define IRQ_TSI         PXA_IRQ(36)     /* Touch Screen Interface (PXA320) */
 #define IRQ_USIM2       PXA_IRQ(38)     /* USIM2 Controller */
-#define IRQ_GRPHICS     PXA_IRQ(39)     /* Graphics Controller */
+#define IRQ_GCU         PXA_IRQ(39)     /* Graphics Controller */
 #define IRQ_MMC2        PXA_IRQ(41)     /* MMC2 Controller */
 #define IRQ_1WIRE       PXA_IRQ(44)     /* 1-Wire Controller */
 #define IRQ_NAND        PXA_IRQ(45)     /* NAND Controller */
@@ -81,8 +82,31 @@
 #define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
 #endif
 
-#define PXA_GPIO_IRQ_BASE       PXA_IRQ(64)
-#define PXA_GPIO_IRQ_NUM        (128)
+#ifdef CONFIG_CPU_PXA935
+#define IRQ_U2O         PXA_IRQ(64)     /* USB OTG 2.0 Controller (PXA935) */
+#define IRQ_U2H         PXA_IRQ(65)     /* USB Host 2.0 Controller (PXA935) */
+
+#define IRQ_MMC3_PXA935 PXA_IRQ(72)     /* MMC3 Controller (PXA935) */
+#define IRQ_MMC4_PXA935 PXA_IRQ(73)     /* MMC4 Controller (PXA935) */
+#define IRQ_MMC5_PXA935 PXA_IRQ(74)     /* MMC5 Controller (PXA935) */
+
+#define IRQ_U2P         PXA_IRQ(93)     /* USB PHY D+/D- Lines (PXA935) */
+#endif
+
+#ifdef CONFIG_CPU_PXA930
+#define IRQ_ENHROT      PXA_IRQ(37)     /* Enhanced Rotary (PXA930) */
+#define IRQ_ACIPC0      PXA_IRQ(5)
+#define IRQ_ACIPC1      PXA_IRQ(40)
+#define IRQ_ACIPC2      PXA_IRQ(19)
+#define IRQ_TRKBALL     PXA_IRQ(43)     /* Track Ball */
+#endif
+
+#ifdef CONFIG_CPU_PXA950
+#define IRQ_GC500       PXA_IRQ(70)     /* Graphics Controller (PXA950) */
+#endif
+
+#define PXA_GPIO_IRQ_BASE       PXA_IRQ(96)
+#define PXA_GPIO_IRQ_NUM        (192)
 
 #define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
 #define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
@@ -105,6 +129,8 @@
 #define IRQ_BOARD_END           (IRQ_BOARD_START + 70)
 #elif defined(CONFIG_MACH_ZYLONITE)
 #define IRQ_BOARD_END           (IRQ_BOARD_START + 32)
+#elif defined(CONFIG_PXA_EZX)
+#define IRQ_BOARD_END           (IRQ_BOARD_START + 23)
 #else
 #define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
 #endif
@@ -237,6 +263,16 @@
 #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
 #define MAINSTONE_S1_IRQ        MAINSTONE_IRQ(15)
 
+/* Balloon3 Interrupts */
+#define BALLOON3_IRQ(x)         (IRQ_BOARD_START + (x))
+
+#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
+#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
+
+#define BALLOON3_AUX_NIRQ       IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
+#define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
+#define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
+
 /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
 #define IRQ_LOCOMO_KEY_BASE     (IRQ_BOARD_START + 0)
 #define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h
index 482185053a92..271e249ae34f 100644
--- a/arch/arm/mach-pxa/include/mach/mfp.h
+++ b/arch/arm/mach-pxa/include/mach/mfp.h
@@ -16,305 +16,6 @@
 #ifndef __ASM_ARCH_MFP_H
 #define __ASM_ARCH_MFP_H
 
-#define mfp_to_gpio(m)  ((m) % 128)
-
-/* list of all the configurable MFP pins */
-enum {
-        MFP_PIN_INVALID = -1,
-
-        MFP_PIN_GPIO0 = 0,
-        MFP_PIN_GPIO1,
-        MFP_PIN_GPIO2,
-        MFP_PIN_GPIO3,
-        MFP_PIN_GPIO4,
-        MFP_PIN_GPIO5,
-        MFP_PIN_GPIO6,
-        MFP_PIN_GPIO7,
-        MFP_PIN_GPIO8,
-        MFP_PIN_GPIO9,
-        MFP_PIN_GPIO10,
-        MFP_PIN_GPIO11,
-        MFP_PIN_GPIO12,
-        MFP_PIN_GPIO13,
-        MFP_PIN_GPIO14,
-        MFP_PIN_GPIO15,
-        MFP_PIN_GPIO16,
-        MFP_PIN_GPIO17,
-        MFP_PIN_GPIO18,
-        MFP_PIN_GPIO19,
-        MFP_PIN_GPIO20,
-        MFP_PIN_GPIO21,
-        MFP_PIN_GPIO22,
-        MFP_PIN_GPIO23,
-        MFP_PIN_GPIO24,
-        MFP_PIN_GPIO25,
-        MFP_PIN_GPIO26,
-        MFP_PIN_GPIO27,
-        MFP_PIN_GPIO28,
-        MFP_PIN_GPIO29,
-        MFP_PIN_GPIO30,
-        MFP_PIN_GPIO31,
-        MFP_PIN_GPIO32,
-        MFP_PIN_GPIO33,
-        MFP_PIN_GPIO34,
-        MFP_PIN_GPIO35,
-        MFP_PIN_GPIO36,
-        MFP_PIN_GPIO37,
-        MFP_PIN_GPIO38,
-        MFP_PIN_GPIO39,
-        MFP_PIN_GPIO40,
-        MFP_PIN_GPIO41,
-        MFP_PIN_GPIO42,
-        MFP_PIN_GPIO43,
-        MFP_PIN_GPIO44,
-        MFP_PIN_GPIO45,
-        MFP_PIN_GPIO46,
-        MFP_PIN_GPIO47,
-        MFP_PIN_GPIO48,
-        MFP_PIN_GPIO49,
-        MFP_PIN_GPIO50,
-        MFP_PIN_GPIO51,
-        MFP_PIN_GPIO52,
-        MFP_PIN_GPIO53,
-        MFP_PIN_GPIO54,
-        MFP_PIN_GPIO55,
-        MFP_PIN_GPIO56,
-        MFP_PIN_GPIO57,
-        MFP_PIN_GPIO58,
-        MFP_PIN_GPIO59,
-        MFP_PIN_GPIO60,
-        MFP_PIN_GPIO61,
-        MFP_PIN_GPIO62,
-        MFP_PIN_GPIO63,
-        MFP_PIN_GPIO64,
-        MFP_PIN_GPIO65,
-        MFP_PIN_GPIO66,
-        MFP_PIN_GPIO67,
-        MFP_PIN_GPIO68,
-        MFP_PIN_GPIO69,
-        MFP_PIN_GPIO70,
-        MFP_PIN_GPIO71,
-        MFP_PIN_GPIO72,
-        MFP_PIN_GPIO73,
-        MFP_PIN_GPIO74,
-        MFP_PIN_GPIO75,
-        MFP_PIN_GPIO76,
-        MFP_PIN_GPIO77,
-        MFP_PIN_GPIO78,
-        MFP_PIN_GPIO79,
-        MFP_PIN_GPIO80,
-        MFP_PIN_GPIO81,
-        MFP_PIN_GPIO82,
-        MFP_PIN_GPIO83,
-        MFP_PIN_GPIO84,
-        MFP_PIN_GPIO85,
-        MFP_PIN_GPIO86,
-        MFP_PIN_GPIO87,
-        MFP_PIN_GPIO88,
-        MFP_PIN_GPIO89,
-        MFP_PIN_GPIO90,
-        MFP_PIN_GPIO91,
-        MFP_PIN_GPIO92,
-        MFP_PIN_GPIO93,
-        MFP_PIN_GPIO94,
-        MFP_PIN_GPIO95,
-        MFP_PIN_GPIO96,
-        MFP_PIN_GPIO97,
-        MFP_PIN_GPIO98,
-        MFP_PIN_GPIO99,
-        MFP_PIN_GPIO100,
-        MFP_PIN_GPIO101,
-        MFP_PIN_GPIO102,
-        MFP_PIN_GPIO103,
-        MFP_PIN_GPIO104,
-        MFP_PIN_GPIO105,
-        MFP_PIN_GPIO106,
-        MFP_PIN_GPIO107,
-        MFP_PIN_GPIO108,
-        MFP_PIN_GPIO109,
-        MFP_PIN_GPIO110,
-        MFP_PIN_GPIO111,
-        MFP_PIN_GPIO112,
-        MFP_PIN_GPIO113,
-        MFP_PIN_GPIO114,
-        MFP_PIN_GPIO115,
-        MFP_PIN_GPIO116,
-        MFP_PIN_GPIO117,
-        MFP_PIN_GPIO118,
-        MFP_PIN_GPIO119,
-        MFP_PIN_GPIO120,
-        MFP_PIN_GPIO121,
-        MFP_PIN_GPIO122,
-        MFP_PIN_GPIO123,
-        MFP_PIN_GPIO124,
-        MFP_PIN_GPIO125,
-        MFP_PIN_GPIO126,
-        MFP_PIN_GPIO127,
-        MFP_PIN_GPIO0_2,
-        MFP_PIN_GPIO1_2,
-        MFP_PIN_GPIO2_2,
-        MFP_PIN_GPIO3_2,
-        MFP_PIN_GPIO4_2,
-        MFP_PIN_GPIO5_2,
-        MFP_PIN_GPIO6_2,
-        MFP_PIN_GPIO7_2,
-        MFP_PIN_GPIO8_2,
-        MFP_PIN_GPIO9_2,
-        MFP_PIN_GPIO10_2,
-        MFP_PIN_GPIO11_2,
-        MFP_PIN_GPIO12_2,
-        MFP_PIN_GPIO13_2,
-        MFP_PIN_GPIO14_2,
-        MFP_PIN_GPIO15_2,
-        MFP_PIN_GPIO16_2,
-        MFP_PIN_GPIO17_2,
-
-        MFP_PIN_ULPI_STP,
-        MFP_PIN_ULPI_NXT,
-        MFP_PIN_ULPI_DIR,
-
-        MFP_PIN_nXCVREN,
-        MFP_PIN_DF_CLE_nOE,
-        MFP_PIN_DF_nADV1_ALE,
-        MFP_PIN_DF_SCLK_E,
-        MFP_PIN_DF_SCLK_S,
-        MFP_PIN_nBE0,
-        MFP_PIN_nBE1,
-        MFP_PIN_DF_nADV2_ALE,
-        MFP_PIN_DF_INT_RnB,
-        MFP_PIN_DF_nCS0,
-        MFP_PIN_DF_nCS1,
-        MFP_PIN_nLUA,
-        MFP_PIN_nLLA,
-        MFP_PIN_DF_nWE,
-        MFP_PIN_DF_ALE_nWE,
-        MFP_PIN_DF_nRE_nOE,
-        MFP_PIN_DF_ADDR0,
-        MFP_PIN_DF_ADDR1,
-        MFP_PIN_DF_ADDR2,
-        MFP_PIN_DF_ADDR3,
-        MFP_PIN_DF_IO0,
-        MFP_PIN_DF_IO1,
-        MFP_PIN_DF_IO2,
-        MFP_PIN_DF_IO3,
-        MFP_PIN_DF_IO4,
-        MFP_PIN_DF_IO5,
-        MFP_PIN_DF_IO6,
-        MFP_PIN_DF_IO7,
-        MFP_PIN_DF_IO8,
-        MFP_PIN_DF_IO9,
-        MFP_PIN_DF_IO10,
-        MFP_PIN_DF_IO11,
-        MFP_PIN_DF_IO12,
-        MFP_PIN_DF_IO13,
-        MFP_PIN_DF_IO14,
-        MFP_PIN_DF_IO15,
-
-        /* additional pins on PXA930 */
-        MFP_PIN_GSIM_UIO,
-        MFP_PIN_GSIM_UCLK,
-        MFP_PIN_GSIM_UDET,
-        MFP_PIN_GSIM_nURST,
-        MFP_PIN_PMIC_INT,
-        MFP_PIN_RDY,
-
-        MFP_PIN_MAX,
-};
-
-/*
- * a possible MFP configuration is represented by a 32-bit integer
- *
- * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
- * bit 10..12 - Alternate Function Selection
- * bit 13..15 - Drive Strength
- * bit 16..18 - Low Power Mode State
- * bit 19..20 - Low Power Mode Edge Detection
- * bit 21..22 - Run Mode Pull State
- *
- * to facilitate the definition, the following macros are provided
- *
- * MFP_CFG_DEFAULT - default MFP configuration value, with
- *                alternate function = 0,
- *                drive strength = fast 3mA (MFP_DS03X)
- *                low power mode = default
- *                edge detection = none
- *
- * MFP_CFG      - default MFPR value with alternate function
- * MFP_CFG_DRV  - default MFPR value with alternate function and
- *                pin drive strength
- * MFP_CFG_LPM  - default MFPR value with alternate function and
- *                low power mode
- * MFP_CFG_X    - default MFPR value with alternate function,
- *                pin drive strength and low power mode
- */
-
-typedef unsigned long mfp_cfg_t;
-
-#define MFP_PIN(x)              ((x) & 0x3ff)
-
-#define MFP_AF0                 (0x0 << 10)
-#define MFP_AF1                 (0x1 << 10)
-#define MFP_AF2                 (0x2 << 10)
-#define MFP_AF3                 (0x3 << 10)
-#define MFP_AF4                 (0x4 << 10)
-#define MFP_AF5                 (0x5 << 10)
-#define MFP_AF6                 (0x6 << 10)
-#define MFP_AF7                 (0x7 << 10)
-#define MFP_AF_MASK             (0x7 << 10)
-#define MFP_AF(x)               (((x) >> 10) & 0x7)
-
-#define MFP_DS01X               (0x0 << 13)
-#define MFP_DS02X               (0x1 << 13)
-#define MFP_DS03X               (0x2 << 13)
-#define MFP_DS04X               (0x3 << 13)
-#define MFP_DS06X               (0x4 << 13)
-#define MFP_DS08X               (0x5 << 13)
-#define MFP_DS10X               (0x6 << 13)
-#define MFP_DS13X               (0x7 << 13)
-#define MFP_DS_MASK             (0x7 << 13)
-#define MFP_DS(x)               (((x) >> 13) & 0x7)
-
-#define MFP_LPM_DEFAULT         (0x0 << 16)
-#define MFP_LPM_DRIVE_LOW       (0x1 << 16)
-#define MFP_LPM_DRIVE_HIGH      (0x2 << 16)
-#define MFP_LPM_PULL_LOW        (0x3 << 16)
-#define MFP_LPM_PULL_HIGH       (0x4 << 16)
-#define MFP_LPM_FLOAT           (0x5 << 16)
-#define MFP_LPM_INPUT           (0x6 << 16)
-#define MFP_LPM_STATE_MASK      (0x7 << 16)
-#define MFP_LPM_STATE(x)        (((x) >> 16) & 0x7)
-
-#define MFP_LPM_EDGE_NONE       (0x0 << 19)
-#define MFP_LPM_EDGE_RISE       (0x1 << 19)
-#define MFP_LPM_EDGE_FALL       (0x2 << 19)
-#define MFP_LPM_EDGE_BOTH       (0x3 << 19)
-#define MFP_LPM_EDGE_MASK       (0x3 << 19)
-#define MFP_LPM_EDGE(x)         (((x) >> 19) & 0x3)
-
-#define MFP_PULL_NONE           (0x0 << 21)
-#define MFP_PULL_LOW            (0x1 << 21)
-#define MFP_PULL_HIGH           (0x2 << 21)
-#define MFP_PULL_BOTH           (0x3 << 21)
-#define MFP_PULL_MASK           (0x3 << 21)
-#define MFP_PULL(x)             (((x) >> 21) & 0x3)
-
-#define MFP_CFG_DEFAULT         (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
-                                 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
-
-#define MFP_CFG(pin, af)                \
-        ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
-
-#define MFP_CFG_DRV(pin, af, drv)       \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
-
-#define MFP_CFG_LPM(pin, af, lpm)       \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
-
-#define MFP_CFG_X(pin, af, drv, lpm)    \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
+#include <plat/mfp.h>
 
 #endif /* __ASM_ARCH_MFP_H */
diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h
index 6d1304c9270f..02a69dc2ee63 100644
--- a/arch/arm/mach-pxa/include/mach/mmc.h
+++ b/arch/arm/mach-pxa/include/mach/mmc.h
@@ -14,6 +14,11 @@ struct pxamci_platform_data {
         int (*get_ro)(struct device *);
         void (*setpower)(struct device *, unsigned int);
         void (*exit)(struct device *, void *);
+        int gpio_card_detect;                   /* gpio detecting card insertion */
+        int gpio_card_ro;                       /* gpio detecting read only toggle */
+        bool gpio_card_ro_invert;               /* gpio ro is inverted */
+        int gpio_power;                         /* gpio powering up MMC bus */
+        bool gpio_power_invert;                 /* gpio power is inverted */
 };
 
 extern void pxa_set_mci_info(struct pxamci_platform_data *info);
diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h
new file mode 100644
index 000000000000..3dc9b074ab46
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmtc.h
@@ -0,0 +1,86 @@
+/*
+ * linux/include/asm-arm/arch-pxa/palmtc-gpio.h
+ *
+ * GPIOs and interrupts for Palm Tungsten|C Handheld Computer
+ *
+ * Authors:     Alex Osborne <bobofdoom@gmail.com>
+ *              Marek Vasut <marek.vasut@gmail.com>
+ *              Holger Bocklet <bitz.email@gmx.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _INCLUDE_PALMTC_H_
+#define _INCLUDE_PALMTC_H_
+
+/** HERE ARE GPIOs **/
+
+/* GPIOs */
+#define GPIO_NR_PALMTC_EARPHONE_DETECT  2
+#define GPIO_NR_PALMTC_CRADLE_DETECT    5
+#define GPIO_NR_PALMTC_HOTSYNC_BUTTON   7
+
+/* SD/MMC */
+#define GPIO_NR_PALMTC_SD_DETECT_N      12
+#define GPIO_NR_PALMTC_SD_POWER         32
+#define GPIO_NR_PALMTC_SD_READONLY      54
+
+/* WLAN */
+#define GPIO_NR_PALMTC_PCMCIA_READY     13
+#define GPIO_NR_PALMTC_PCMCIA_PWRREADY  14
+#define GPIO_NR_PALMTC_PCMCIA_POWER1    15
+#define GPIO_NR_PALMTC_PCMCIA_POWER2    33
+#define GPIO_NR_PALMTC_PCMCIA_POWER3    55
+#define GPIO_NR_PALMTC_PCMCIA_RESET     78
+
+/* UDC */
+#define GPIO_NR_PALMTC_USB_DETECT_N     4
+#define GPIO_NR_PALMTC_USB_POWER        36
+
+/* LCD/BACKLIGHT */
+#define GPIO_NR_PALMTC_BL_POWER         16
+#define GPIO_NR_PALMTC_LCD_POWER        44
+#define GPIO_NR_PALMTC_LCD_BLANK        38
+
+/* UART */
+#define GPIO_NR_PALMTC_RS232_POWER      37
+
+/* IRDA */
+#define GPIO_NR_PALMTC_IR_DISABLE       45
+
+/* IRQs */
+#define IRQ_GPIO_PALMTC_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMTC_SD_DETECT_N)
+#define IRQ_GPIO_PALMTC_WLAN_READY      IRQ_GPIO(GPIO_NR_PALMTC_WLAN_READY)
+
+/* UCB1400 GPIOs */
+#define GPIO_NR_PALMTC_POWER_DETECT     (0x80 | 0x00)
+#define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01)
+#define GPIO_NR_PALMTC_SPEAKER_ENABLE   (0x80 | 0x03)
+#define GPIO_NR_PALMTC_VIBRA_POWER      (0x80 | 0x05)
+#define GPIO_NR_PALMTC_LED_POWER        (0x80 | 0x07)
+
+/** HERE ARE INIT VALUES **/
+#define PALMTC_UCB1400_GPIO_OFFSET      0x80
+
+/* BATTERY */
+#define PALMTC_BAT_MAX_VOLTAGE          4000    /* 4.00V maximum voltage */
+#define PALMTC_BAT_MIN_VOLTAGE          3550    /* 3.55V critical voltage */
+#define PALMTC_BAT_MAX_CURRENT          0       /* unknokn */
+#define PALMTC_BAT_MIN_CURRENT          0       /* unknown */
+#define PALMTC_BAT_MAX_CHARGE           1       /* unknown */
+#define PALMTC_BAT_MIN_CHARGE           1       /* unknown */
+#define PALMTC_MAX_LIFE_MINS            240     /* on-life in minutes */
+
+#define PALMTC_BAT_MEASURE_DELAY        (HZ * 1)
+
+/* BACKLIGHT */
+#define PALMTC_MAX_INTENSITY            0xFE
+#define PALMTC_DEFAULT_INTENSITY        0x7E
+#define PALMTC_LIMIT_MASK               0x7F
+#define PALMTC_PRESCALER                0x3F
+#define PALMTC_PERIOD_NS                3500
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
index e74082c872e1..1be0db6ed55e 100644
--- a/arch/arm/mach-pxa/include/mach/palmtx.h
+++ b/arch/arm/mach-pxa/include/mach/palmtx.h
@@ -82,6 +82,11 @@
 #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS    /* ChipSelect 0 */
 #define PALMTX_PHYS_NAND_START  PXA_CS1_PHYS    /* ChipSelect 1 */
 
+#define PALMTX_NAND_ALE_PHYS    (PALMTX_PHYS_NAND_START | (1 << 24))
+#define PALMTX_NAND_CLE_PHYS    (PALMTX_PHYS_NAND_START | (1 << 25))
+#define PALMTX_NAND_ALE_VIRT    0xff100000
+#define PALMTX_NAND_CLE_VIRT    0xff200000
+
 /* TOUCHSCREEN */
 #define AC97_LINK_FRAME                 21
 
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 7d1a059b3d43..e91d63cfe811 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -208,7 +208,7 @@
 #define CKEN_MVED       43      /* < MVED clock enable */
 
 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
-#define PXA300_CKEN_GRAPHICS    42      /* Graphics controller clock enable */
-#define PXA320_CKEN_GRAPHICS    7       /* Graphics controller clock enable */
+#define CKEN_PXA300_GCU         42      /* Graphics controller clock enable */
+#define CKEN_PXA320_GCU         7       /* Graphics controller clock enable */
 
 #endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index 6932720ba04e..f73061c90b5e 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -118,7 +118,8 @@ struct pxafb_mach_info {
         u_int           fixed_modes:1,
                         cmap_inverse:1,
                         cmap_static:1,
-                        unused:29;
+                        acceleration_enabled:1,
+                        unused:28;
 
         /* The following should be defined in LCCR0
          *      LCCR0_Act or LCCR0_Pas          Active or Passive
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
index ad23e74b762f..68464ce1c1ea 100644
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -13,6 +13,7 @@
 #define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
 #define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
 #define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
+#define ICHP            __REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
 
 #define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
 #define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
@@ -20,4 +21,14 @@
 #define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
 #define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
 
+#define ICIP3           __REG(0x40D00130)  /* Interrupt Controller IRQ Pending Register 3 */
+#define ICMR3           __REG(0x40D00134)  /* Interrupt Controller Mask Register 3 */
+#define ICLR3           __REG(0x40D00138)  /* Interrupt Controller Level Register 3 */
+#define ICFP3           __REG(0x40D0013C)  /* Interrupt Controller FIQ Pending Register 3 */
+#define ICPR3           __REG(0x40D00140)  /* Interrupt Controller Pending Register 3 */
+
+#define IPR(x)          __REG(0x40D0001C + (x < 32 ? (x << 2)           \
+                                : (x < 64 ? (0x94 + ((x - 32) << 2))    \
+                                : (0x128 + ((x - 64) << 2)))))
+
 #endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index b54749413e96..237734b5b1be 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -37,7 +37,7 @@ static inline void arch_decomp_setup(void)
 {
         if (machine_is_littleton() || machine_is_intelmote2()
             || machine_is_csb726() || machine_is_stargate2()
-            || machine_is_cm_x300())
+            || machine_is_cm_x300() || machine_is_balloon3())
                 UART = STUART;
 }