diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-03-28 16:29:51 -0400 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-03-28 16:29:51 -0400 |
commit | ed40d0c472b136682b2fcba05f89762859c7374f (patch) | |
tree | 076b83a26bcd63d6158463735dd34c10bbc591dc /arch/arm/mach-pxa/include/mach/regs-ssp.h | |
parent | 9e495834e59ca9b29f1a1f63b9f5533bb022ac49 (diff) | |
parent | 5d80f8e5a9dc9c9a94d4aeaa567e219a808b8a4a (diff) |
Merge branch 'origin' into devel
Conflicts:
sound/soc/pxa/pxa2xx-i2s.c
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/regs-ssp.h')
-rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-ssp.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h index 8152be683881..6a2ed35acd59 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ssp.h +++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h | |||
@@ -49,7 +49,7 @@ | |||
49 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ | 49 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ |
50 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ | 50 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ |
51 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ | 51 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ |
52 | #define SSCR0_ADC (1 << 30) /* Audio clock select */ | 52 | #define SSCR0_ACS (1 << 30) /* Audio clock select */ |
53 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ | 53 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ |
54 | #endif | 54 | #endif |
55 | 55 | ||
@@ -108,6 +108,11 @@ | |||
108 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ | 108 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ |
109 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ | 109 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ |
110 | 110 | ||
111 | #if defined(CONFIG_PXA3xx) | ||
112 | #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ | ||
113 | #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ | ||
114 | #endif | ||
115 | |||
111 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ | 116 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ |
112 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ | 117 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ |
113 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ | 118 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ |