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authorHaojian Zhuang <haojian.zhuang@marvell.com>2009-08-19 07:49:31 -0400
committerEric Miao <eric.y.miao@gmail.com>2009-09-10 06:49:26 -0400
commitd2c37068429b29d6549cf3486fc84b836689e122 (patch)
tree5c5460cd095a1bb01d5a92ecce850a127c38e2ed /arch/arm/mach-pxa/include/mach/entry-macro.S
parent6ba39282bb3ee486a142ee3fd61196d329622ed9 (diff)
[ARM] pxa: initialize default interrupt priority and use ICHP for IRQ handling
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/entry-macro.S')
-rw-r--r--arch/arm/mach-pxa/include/mach/entry-macro.S25
1 files changed, 9 insertions, 16 deletions
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
index f6b4bf3e73d2..241880608ac6 100644
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -24,34 +24,27 @@
24 mov \tmp, \tmp, lsr #13 24 mov \tmp, \tmp, lsr #13
25 and \tmp, \tmp, #0x7 @ Core G 25 and \tmp, \tmp, #0x7 @ Core G
26 cmp \tmp, #1 26 cmp \tmp, #1
27 bhi 1004f 27 bhi 1002f
28 28
29 @ Core Generation 1 (PXA25x)
29 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 30 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
30 add \base, \base, #0x00d00000 31 add \base, \base, #0x00d00000
31 ldr \irqstat, [\base, #0] @ ICIP 32 ldr \irqstat, [\base, #0] @ ICIP
32 ldr \irqnr, [\base, #4] @ ICMR 33 ldr \irqnr, [\base, #4] @ ICMR
33 b 1002f
34 34
351004:
36 mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
37 mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
38 ands \irqnr, \irqstat, \irqnr 35 ands \irqnr, \irqstat, \irqnr
39 beq 1003f 36 beq 1001f
40 rsb \irqstat, \irqnr, #0 37 rsb \irqstat, \irqnr, #0
41 and \irqstat, \irqstat, \irqnr 38 and \irqstat, \irqstat, \irqnr
42 clz \irqnr, \irqstat 39 clz \irqnr, \irqstat
43 rsb \irqnr, \irqnr, #31 40 rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0))
44 add \irqnr, \irqnr, #(32 + PXA_IRQ(0))
45 b 1001f 41 b 1001f
461003:
47 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
48 mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
491002: 421002:
50 ands \irqnr, \irqstat, \irqnr 43 @ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
44 mrc p6, 0, \irqstat, c5, c0, 0 @ ICHP
45 tst \irqstat, #0x80000000
51 beq 1001f 46 beq 1001f
52 rsb \irqstat, \irqnr, #0 47 bic \irqstat, \irqstat, #0x80000000
53 and \irqstat, \irqstat, \irqnr 48 mov \irqnr, \irqstat, lsr #16
54 clz \irqnr, \irqstat
55 rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0))
561001: 491001:
57 .endm 50 .endm