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authoreric miao <eric.miao@marvell.com>2007-12-19 04:14:02 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 10:07:52 -0500
commit8f58de7c3932f659fff3b4e5fc14ca8ccf8ec873 (patch)
tree0e8988ff90d6377d124865c94076ca2702585ef8 /arch/arm/mach-pxa/generic.c
parenta333aeb73b45d2b6bbaaebd56f9e7e3a674ac039 (diff)
[ARM] pxa: create arch/arm/mach-pxa/device.c for all on-chip devices
Considering that generic.c is getting more and more bloated by device information, moving that part out side will be much cleaner. Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/generic.c')
-rw-r--r--arch/arm/mach-pxa/generic.c548
1 files changed, 0 insertions, 548 deletions
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index a8d88704c8d4..e4dbdbc2fb15 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -20,11 +20,9 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/ioport.h> 23#include <linux/ioport.h>
25#include <linux/pm.h> 24#include <linux/pm.h>
26#include <linux/string.h> 25#include <linux/string.h>
27#include <linux/dma-mapping.h>
28 26
29#include <asm/hardware.h> 27#include <asm/hardware.h>
30#include <asm/irq.h> 28#include <asm/irq.h>
@@ -34,13 +32,7 @@
34 32
35#include <asm/arch/pxa-regs.h> 33#include <asm/arch/pxa-regs.h>
36#include <asm/arch/gpio.h> 34#include <asm/arch/gpio.h>
37#include <asm/arch/udc.h>
38#include <asm/arch/pxafb.h>
39#include <asm/arch/mmc.h>
40#include <asm/arch/irda.h>
41#include <asm/arch/i2c.h>
42 35
43#include "devices.h"
44#include "generic.h" 36#include "generic.h"
45 37
46/* 38/*
@@ -234,543 +226,3 @@ void __init pxa_map_io(void)
234 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 226 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
235 get_clk_frequency_khz(1); 227 get_clk_frequency_khz(1);
236} 228}
237
238
239void __init pxa_register_device(struct platform_device *dev, void *data)
240{
241 int ret;
242
243 dev->dev.platform_data = data;
244
245 ret = platform_device_register(dev);
246 if (ret)
247 dev_err(&dev->dev, "unable to register device: %d\n", ret);
248}
249
250
251static struct resource pxamci_resources[] = {
252 [0] = {
253 .start = 0x41100000,
254 .end = 0x41100fff,
255 .flags = IORESOURCE_MEM,
256 },
257 [1] = {
258 .start = IRQ_MMC,
259 .end = IRQ_MMC,
260 .flags = IORESOURCE_IRQ,
261 },
262 [2] = {
263 .start = 21,
264 .end = 21,
265 .flags = IORESOURCE_DMA,
266 },
267 [3] = {
268 .start = 22,
269 .end = 22,
270 .flags = IORESOURCE_DMA,
271 },
272};
273
274static u64 pxamci_dmamask = 0xffffffffUL;
275
276struct platform_device pxa_device_mci = {
277 .name = "pxa2xx-mci",
278 .id = -1,
279 .dev = {
280 .dma_mask = &pxamci_dmamask,
281 .coherent_dma_mask = 0xffffffff,
282 },
283 .num_resources = ARRAY_SIZE(pxamci_resources),
284 .resource = pxamci_resources,
285};
286
287void __init pxa_set_mci_info(struct pxamci_platform_data *info)
288{
289 pxa_register_device(&pxa_device_mci, info);
290}
291
292
293static struct pxa2xx_udc_mach_info pxa_udc_info;
294
295void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
296{
297 memcpy(&pxa_udc_info, info, sizeof *info);
298}
299
300static struct resource pxa2xx_udc_resources[] = {
301 [0] = {
302 .start = 0x40600000,
303 .end = 0x4060ffff,
304 .flags = IORESOURCE_MEM,
305 },
306 [1] = {
307 .start = IRQ_USB,
308 .end = IRQ_USB,
309 .flags = IORESOURCE_IRQ,
310 },
311};
312
313static u64 udc_dma_mask = ~(u32)0;
314
315struct platform_device pxa_device_udc = {
316 .name = "pxa2xx-udc",
317 .id = -1,
318 .resource = pxa2xx_udc_resources,
319 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
320 .dev = {
321 .platform_data = &pxa_udc_info,
322 .dma_mask = &udc_dma_mask,
323 }
324};
325
326static struct resource pxafb_resources[] = {
327 [0] = {
328 .start = 0x44000000,
329 .end = 0x4400ffff,
330 .flags = IORESOURCE_MEM,
331 },
332 [1] = {
333 .start = IRQ_LCD,
334 .end = IRQ_LCD,
335 .flags = IORESOURCE_IRQ,
336 },
337};
338
339static u64 fb_dma_mask = ~(u64)0;
340
341struct platform_device pxa_device_fb = {
342 .name = "pxa2xx-fb",
343 .id = -1,
344 .dev = {
345 .dma_mask = &fb_dma_mask,
346 .coherent_dma_mask = 0xffffffff,
347 },
348 .num_resources = ARRAY_SIZE(pxafb_resources),
349 .resource = pxafb_resources,
350};
351
352void __init set_pxa_fb_info(struct pxafb_mach_info *info)
353{
354 pxa_register_device(&pxa_device_fb, info);
355}
356
357void __init set_pxa_fb_parent(struct device *parent_dev)
358{
359 pxa_device_fb.dev.parent = parent_dev;
360}
361
362static struct resource pxa_resource_ffuart[] = {
363 {
364 .start = __PREG(FFUART),
365 .end = __PREG(FFUART) + 35,
366 .flags = IORESOURCE_MEM,
367 }, {
368 .start = IRQ_FFUART,
369 .end = IRQ_FFUART,
370 .flags = IORESOURCE_IRQ,
371 }
372};
373
374struct platform_device pxa_device_ffuart= {
375 .name = "pxa2xx-uart",
376 .id = 0,
377 .resource = pxa_resource_ffuart,
378 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
379};
380
381static struct resource pxa_resource_btuart[] = {
382 {
383 .start = __PREG(BTUART),
384 .end = __PREG(BTUART) + 35,
385 .flags = IORESOURCE_MEM,
386 }, {
387 .start = IRQ_BTUART,
388 .end = IRQ_BTUART,
389 .flags = IORESOURCE_IRQ,
390 }
391};
392
393struct platform_device pxa_device_btuart = {
394 .name = "pxa2xx-uart",
395 .id = 1,
396 .resource = pxa_resource_btuart,
397 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
398};
399
400static struct resource pxa_resource_stuart[] = {
401 {
402 .start = __PREG(STUART),
403 .end = __PREG(STUART) + 35,
404 .flags = IORESOURCE_MEM,
405 }, {
406 .start = IRQ_STUART,
407 .end = IRQ_STUART,
408 .flags = IORESOURCE_IRQ,
409 }
410};
411
412struct platform_device pxa_device_stuart = {
413 .name = "pxa2xx-uart",
414 .id = 2,
415 .resource = pxa_resource_stuart,
416 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
417};
418
419static struct resource pxa_resource_hwuart[] = {
420 {
421 .start = __PREG(HWUART),
422 .end = __PREG(HWUART) + 47,
423 .flags = IORESOURCE_MEM,
424 }, {
425 .start = IRQ_HWUART,
426 .end = IRQ_HWUART,
427 .flags = IORESOURCE_IRQ,
428 }
429};
430
431struct platform_device pxa_device_hwuart = {
432 .name = "pxa2xx-uart",
433 .id = 3,
434 .resource = pxa_resource_hwuart,
435 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
436};
437
438static struct resource pxai2c_resources[] = {
439 {
440 .start = 0x40301680,
441 .end = 0x403016a3,
442 .flags = IORESOURCE_MEM,
443 }, {
444 .start = IRQ_I2C,
445 .end = IRQ_I2C,
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450struct platform_device pxa_device_i2c = {
451 .name = "pxa2xx-i2c",
452 .id = 0,
453 .resource = pxai2c_resources,
454 .num_resources = ARRAY_SIZE(pxai2c_resources),
455};
456
457void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
458{
459 pxa_register_device(&pxa_device_i2c, info);
460}
461
462static struct resource pxai2s_resources[] = {
463 {
464 .start = 0x40400000,
465 .end = 0x40400083,
466 .flags = IORESOURCE_MEM,
467 }, {
468 .start = IRQ_I2S,
469 .end = IRQ_I2S,
470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474struct platform_device pxa_device_i2s = {
475 .name = "pxa2xx-i2s",
476 .id = -1,
477 .resource = pxai2s_resources,
478 .num_resources = ARRAY_SIZE(pxai2s_resources),
479};
480
481static u64 pxaficp_dmamask = ~(u32)0;
482
483struct platform_device pxa_device_ficp = {
484 .name = "pxa2xx-ir",
485 .id = -1,
486 .dev = {
487 .dma_mask = &pxaficp_dmamask,
488 .coherent_dma_mask = 0xffffffff,
489 },
490};
491
492void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
493{
494 pxa_register_device(&pxa_device_ficp, info);
495}
496
497struct platform_device pxa_device_rtc = {
498 .name = "sa1100-rtc",
499 .id = -1,
500};
501
502#ifdef CONFIG_PXA25x
503
504static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
505
506static struct resource pxa25x_resource_ssp[] = {
507 [0] = {
508 .start = 0x41000000,
509 .end = 0x4100001f,
510 .flags = IORESOURCE_MEM,
511 },
512 [1] = {
513 .start = IRQ_SSP,
514 .end = IRQ_SSP,
515 .flags = IORESOURCE_IRQ,
516 },
517 [2] = {
518 /* DRCMR for RX */
519 .start = 13,
520 .end = 13,
521 .flags = IORESOURCE_DMA,
522 },
523 [3] = {
524 /* DRCMR for TX */
525 .start = 14,
526 .end = 14,
527 .flags = IORESOURCE_DMA,
528 },
529};
530
531struct platform_device pxa25x_device_ssp = {
532 .name = "pxa25x-ssp",
533 .id = 0,
534 .dev = {
535 .dma_mask = &pxa25x_ssp_dma_mask,
536 .coherent_dma_mask = DMA_BIT_MASK(32),
537 },
538 .resource = pxa25x_resource_ssp,
539 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
540};
541
542static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
543
544static struct resource pxa25x_resource_nssp[] = {
545 [0] = {
546 .start = 0x41400000,
547 .end = 0x4140002f,
548 .flags = IORESOURCE_MEM,
549 },
550 [1] = {
551 .start = IRQ_NSSP,
552 .end = IRQ_NSSP,
553 .flags = IORESOURCE_IRQ,
554 },
555 [2] = {
556 /* DRCMR for RX */
557 .start = 15,
558 .end = 15,
559 .flags = IORESOURCE_DMA,
560 },
561 [3] = {
562 /* DRCMR for TX */
563 .start = 16,
564 .end = 16,
565 .flags = IORESOURCE_DMA,
566 },
567};
568
569struct platform_device pxa25x_device_nssp = {
570 .name = "pxa25x-nssp",
571 .id = 1,
572 .dev = {
573 .dma_mask = &pxa25x_nssp_dma_mask,
574 .coherent_dma_mask = DMA_BIT_MASK(32),
575 },
576 .resource = pxa25x_resource_nssp,
577 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
578};
579
580static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
581
582static struct resource pxa25x_resource_assp[] = {
583 [0] = {
584 .start = 0x41500000,
585 .end = 0x4150002f,
586 .flags = IORESOURCE_MEM,
587 },
588 [1] = {
589 .start = IRQ_ASSP,
590 .end = IRQ_ASSP,
591 .flags = IORESOURCE_IRQ,
592 },
593 [2] = {
594 /* DRCMR for RX */
595 .start = 23,
596 .end = 23,
597 .flags = IORESOURCE_DMA,
598 },
599 [3] = {
600 /* DRCMR for TX */
601 .start = 24,
602 .end = 24,
603 .flags = IORESOURCE_DMA,
604 },
605};
606
607struct platform_device pxa25x_device_assp = {
608 /* ASSP is basically equivalent to NSSP */
609 .name = "pxa25x-nssp",
610 .id = 2,
611 .dev = {
612 .dma_mask = &pxa25x_assp_dma_mask,
613 .coherent_dma_mask = DMA_BIT_MASK(32),
614 },
615 .resource = pxa25x_resource_assp,
616 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
617};
618#endif /* CONFIG_PXA25x */
619
620#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
621
622static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
623
624static struct resource pxa27x_resource_ssp1[] = {
625 [0] = {
626 .start = 0x41000000,
627 .end = 0x4100003f,
628 .flags = IORESOURCE_MEM,
629 },
630 [1] = {
631 .start = IRQ_SSP,
632 .end = IRQ_SSP,
633 .flags = IORESOURCE_IRQ,
634 },
635 [2] = {
636 /* DRCMR for RX */
637 .start = 13,
638 .end = 13,
639 .flags = IORESOURCE_DMA,
640 },
641 [3] = {
642 /* DRCMR for TX */
643 .start = 14,
644 .end = 14,
645 .flags = IORESOURCE_DMA,
646 },
647};
648
649struct platform_device pxa27x_device_ssp1 = {
650 .name = "pxa27x-ssp",
651 .id = 0,
652 .dev = {
653 .dma_mask = &pxa27x_ssp1_dma_mask,
654 .coherent_dma_mask = DMA_BIT_MASK(32),
655 },
656 .resource = pxa27x_resource_ssp1,
657 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
658};
659
660static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
661
662static struct resource pxa27x_resource_ssp2[] = {
663 [0] = {
664 .start = 0x41700000,
665 .end = 0x4170003f,
666 .flags = IORESOURCE_MEM,
667 },
668 [1] = {
669 .start = IRQ_SSP2,
670 .end = IRQ_SSP2,
671 .flags = IORESOURCE_IRQ,
672 },
673 [2] = {
674 /* DRCMR for RX */
675 .start = 15,
676 .end = 15,
677 .flags = IORESOURCE_DMA,
678 },
679 [3] = {
680 /* DRCMR for TX */
681 .start = 16,
682 .end = 16,
683 .flags = IORESOURCE_DMA,
684 },
685};
686
687struct platform_device pxa27x_device_ssp2 = {
688 .name = "pxa27x-ssp",
689 .id = 1,
690 .dev = {
691 .dma_mask = &pxa27x_ssp2_dma_mask,
692 .coherent_dma_mask = DMA_BIT_MASK(32),
693 },
694 .resource = pxa27x_resource_ssp2,
695 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
696};
697
698static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
699
700static struct resource pxa27x_resource_ssp3[] = {
701 [0] = {
702 .start = 0x41900000,
703 .end = 0x4190003f,
704 .flags = IORESOURCE_MEM,
705 },
706 [1] = {
707 .start = IRQ_SSP3,
708 .end = IRQ_SSP3,
709 .flags = IORESOURCE_IRQ,
710 },
711 [2] = {
712 /* DRCMR for RX */
713 .start = 66,
714 .end = 66,
715 .flags = IORESOURCE_DMA,
716 },
717 [3] = {
718 /* DRCMR for TX */
719 .start = 67,
720 .end = 67,
721 .flags = IORESOURCE_DMA,
722 },
723};
724
725struct platform_device pxa27x_device_ssp3 = {
726 .name = "pxa27x-ssp",
727 .id = 2,
728 .dev = {
729 .dma_mask = &pxa27x_ssp3_dma_mask,
730 .coherent_dma_mask = DMA_BIT_MASK(32),
731 },
732 .resource = pxa27x_resource_ssp3,
733 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
734};
735#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
736
737#ifdef CONFIG_PXA3xx
738static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
739
740static struct resource pxa3xx_resource_ssp4[] = {
741 [0] = {
742 .start = 0x41a00000,
743 .end = 0x41a0003f,
744 .flags = IORESOURCE_MEM,
745 },
746 [1] = {
747 .start = IRQ_SSP4,
748 .end = IRQ_SSP4,
749 .flags = IORESOURCE_IRQ,
750 },
751 [2] = {
752 /* DRCMR for RX */
753 .start = 2,
754 .end = 2,
755 .flags = IORESOURCE_DMA,
756 },
757 [3] = {
758 /* DRCMR for TX */
759 .start = 3,
760 .end = 3,
761 .flags = IORESOURCE_DMA,
762 },
763};
764
765struct platform_device pxa3xx_device_ssp4 = {
766 /* PXA3xx SSP is basically equivalent to PXA27x */
767 .name = "pxa27x-ssp",
768 .id = 3,
769 .dev = {
770 .dma_mask = &pxa3xx_ssp4_dma_mask,
771 .coherent_dma_mask = DMA_BIT_MASK(32),
772 },
773 .resource = pxa3xx_resource_ssp4,
774 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
775};
776#endif /* CONFIG_PXA3xx */
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