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authorRongjun Ying <rongjun.ying@csr.com>2011-07-08 05:40:14 -0400
committerBarry Song <21cnbao@gmail.com>2011-07-08 19:21:53 -0400
commit89e162afd37caa6acab4e05b6e9e9fad6235381e (patch)
treeac5dafe6664ab1e5fab867fcef7d8a7c685d8f78 /arch/arm/mach-prima2/l2x0.c
parent31adb06f9d68f9d033284c9ab0e264b2d581bceb (diff)
ARM: CSR: initializing L2 cache
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-prima2/l2x0.c')
-rw-r--r--arch/arm/mach-prima2/l2x0.c59
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
new file mode 100644
index 000000000000..9cda2057bcfb
--- /dev/null
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -0,0 +1,59 @@
1/*
2 * l2 cache initialization for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/io.h>
12#include <linux/errno.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <asm/hardware/cache-l2x0.h>
16#include <mach/memory.h>
17
18#define L2X0_ADDR_FILTERING_START 0xC00
19#define L2X0_ADDR_FILTERING_END 0xC04
20
21static struct of_device_id l2x_ids[] = {
22 { .compatible = "arm,pl310-cache" },
23};
24
25static int __init sirfsoc_of_l2x_init(void)
26{
27 struct device_node *np;
28 void __iomem *sirfsoc_l2x_base;
29
30 np = of_find_matching_node(NULL, l2x_ids);
31 if (!np)
32 panic("unable to find compatible l2x node in dtb\n");
33
34 sirfsoc_l2x_base = of_iomap(np, 0);
35 if (!sirfsoc_l2x_base)
36 panic("unable to map l2x cpu registers\n");
37
38 of_node_put(np);
39
40 if (!(readl_relaxed(sirfsoc_l2x_base + L2X0_CTRL) & 1)) {
41 /*
42 * set the physical memory windows L2 cache will cover
43 */
44 writel_relaxed(PLAT_PHYS_OFFSET + 1024 * 1024 * 1024,
45 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END);
46 writel_relaxed(PLAT_PHYS_OFFSET | 0x1,
47 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START);
48
49 writel_relaxed(0,
50 sirfsoc_l2x_base + L2X0_TAG_LATENCY_CTRL);
51 writel_relaxed(0,
52 sirfsoc_l2x_base + L2X0_DATA_LATENCY_CTRL);
53 }
54 l2x0_init((void __iomem *)sirfsoc_l2x_base, 0x00040000,
55 0x00000000);
56
57 return 0;
58}
59early_initcall(sirfsoc_of_l2x_init);