diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2010-11-29 04:40:16 -0500 |
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committer | Lennert Buytenhek <buytenh@wantstofly.org> | 2011-01-13 11:18:54 -0500 |
commit | 406b005045ad18ffa08c439545801e1c8cec4b5e (patch) | |
tree | 91272d83fb598542e11d00e0966a569c60786e5b /arch/arm/mach-pnx4008 | |
parent | df303477bd06d5453a4d8a69fb1ecf24c5ca5e48 (diff) |
ARM: pnx4008: irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Diffstat (limited to 'arch/arm/mach-pnx4008')
-rw-r--r-- | arch/arm/mach-pnx4008/irq.c | 62 |
1 files changed, 33 insertions, 29 deletions
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index a9ce02b4bf17..c69c180aec76 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c | |||
@@ -36,44 +36,44 @@ | |||
36 | 36 | ||
37 | static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES; | 37 | static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES; |
38 | 38 | ||
39 | static void pnx4008_mask_irq(unsigned int irq) | 39 | static void pnx4008_mask_irq(struct irq_data *d) |
40 | { | 40 | { |
41 | __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */ | 41 | __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ |
42 | } | 42 | } |
43 | 43 | ||
44 | static void pnx4008_unmask_irq(unsigned int irq) | 44 | static void pnx4008_unmask_irq(struct irq_data *d) |
45 | { | 45 | { |
46 | __raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq)); /* unmask interrupt */ | 46 | __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */ |
47 | } | 47 | } |
48 | 48 | ||
49 | static void pnx4008_mask_ack_irq(unsigned int irq) | 49 | static void pnx4008_mask_ack_irq(struct irq_data *d) |
50 | { | 50 | { |
51 | __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */ | 51 | __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ |
52 | __raw_writel(INTC_BIT(irq), INTC_SR(irq)); /* clear interrupt status */ | 52 | __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */ |
53 | } | 53 | } |
54 | 54 | ||
55 | static int pnx4008_set_irq_type(unsigned int irq, unsigned int type) | 55 | static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) |
56 | { | 56 | { |
57 | switch (type) { | 57 | switch (type) { |
58 | case IRQ_TYPE_EDGE_RISING: | 58 | case IRQ_TYPE_EDGE_RISING: |
59 | __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ | 59 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
60 | __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ | 60 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ |
61 | set_irq_handler(irq, handle_edge_irq); | 61 | set_irq_handler(d->irq, handle_edge_irq); |
62 | break; | 62 | break; |
63 | case IRQ_TYPE_EDGE_FALLING: | 63 | case IRQ_TYPE_EDGE_FALLING: |
64 | __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ | 64 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
65 | __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ | 65 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ |
66 | set_irq_handler(irq, handle_edge_irq); | 66 | set_irq_handler(d->irq, handle_edge_irq); |
67 | break; | 67 | break; |
68 | case IRQ_TYPE_LEVEL_LOW: | 68 | case IRQ_TYPE_LEVEL_LOW: |
69 | __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ | 69 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
70 | __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ | 70 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ |
71 | set_irq_handler(irq, handle_level_irq); | 71 | set_irq_handler(d->irq, handle_level_irq); |
72 | break; | 72 | break; |
73 | case IRQ_TYPE_LEVEL_HIGH: | 73 | case IRQ_TYPE_LEVEL_HIGH: |
74 | __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ | 74 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
75 | __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ | 75 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ |
76 | set_irq_handler(irq, handle_level_irq); | 76 | set_irq_handler(d->irq, handle_level_irq); |
77 | break; | 77 | break; |
78 | 78 | ||
79 | /* IRQ_TYPE_EDGE_BOTH is not supported */ | 79 | /* IRQ_TYPE_EDGE_BOTH is not supported */ |
@@ -85,10 +85,10 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type) | |||
85 | } | 85 | } |
86 | 86 | ||
87 | static struct irq_chip pnx4008_irq_chip = { | 87 | static struct irq_chip pnx4008_irq_chip = { |
88 | .ack = pnx4008_mask_ack_irq, | 88 | .irq_ack = pnx4008_mask_ack_irq, |
89 | .mask = pnx4008_mask_irq, | 89 | .irq_mask = pnx4008_mask_irq, |
90 | .unmask = pnx4008_unmask_irq, | 90 | .irq_unmask = pnx4008_unmask_irq, |
91 | .set_type = pnx4008_set_irq_type, | 91 | .irq_set_type = pnx4008_set_irq_type, |
92 | }; | 92 | }; |
93 | 93 | ||
94 | void __init pnx4008_init_irq(void) | 94 | void __init pnx4008_init_irq(void) |
@@ -99,14 +99,18 @@ void __init pnx4008_init_irq(void) | |||
99 | for (i = 0; i < NR_IRQS; i++) { | 99 | for (i = 0; i < NR_IRQS; i++) { |
100 | set_irq_flags(i, IRQF_VALID); | 100 | set_irq_flags(i, IRQF_VALID); |
101 | set_irq_chip(i, &pnx4008_irq_chip); | 101 | set_irq_chip(i, &pnx4008_irq_chip); |
102 | pnx4008_set_irq_type(i, pnx4008_irq_type[i]); | 102 | pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); |
103 | } | 103 | } |
104 | 104 | ||
105 | /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */ | 105 | /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */ |
106 | pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]); | 106 | pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N), |
107 | pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]); | 107 | pnx4008_irq_type[SUB1_IRQ_N]); |
108 | pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]); | 108 | pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N), |
109 | pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]); | 109 | pnx4008_irq_type[SUB2_IRQ_N]); |
110 | pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N), | ||
111 | pnx4008_irq_type[SUB1_FIQ_N]); | ||
112 | pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N), | ||
113 | pnx4008_irq_type[SUB2_FIQ_N]); | ||
110 | 114 | ||
111 | /* mask all others */ | 115 | /* mask all others */ |
112 | __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | | 116 | __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | |