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authorOlof Johansson <olof@lixom.net>2012-10-04 23:17:25 -0400
committerOlof Johansson <olof@lixom.net>2012-10-04 23:17:25 -0400
commit54d69df5849ec2e660aa12ac75562618c10fb499 (patch)
treeadbfb8bcc7cc73b83bf2b784fa331911ba03573a /arch/arm/mach-pnx4008
parentad932bb6b549722a561fb31ac2fa50dcbcb3e36b (diff)
parent46f2007c1efadfa4071c17e75f140c47f09293de (diff)
Merge branch 'late/kirkwood' into late/soc
Merge in the late Kirkwood branch with the OMAP late branch for upstream submission. Final contents described in shared tag. Fixup remove/change conflicts in arch/arm/mach-omap2/devices.c and drivers/spi/spi-omap2-mcspi.c. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-pnx4008')
-rw-r--r--arch/arm/mach-pnx4008/Makefile12
-rw-r--r--arch/arm/mach-pnx4008/Makefile.boot4
-rw-r--r--arch/arm/mach-pnx4008/clock.c1001
-rw-r--r--arch/arm/mach-pnx4008/clock.h43
-rw-r--r--arch/arm/mach-pnx4008/core.c290
-rw-r--r--arch/arm/mach-pnx4008/dma.c1105
-rw-r--r--arch/arm/mach-pnx4008/gpio.c328
-rw-r--r--arch/arm/mach-pnx4008/i2c.c86
-rw-r--r--arch/arm/mach-pnx4008/include/mach/clock.h62
-rw-r--r--arch/arm/mach-pnx4008/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-pnx4008/include/mach/dma.h160
-rw-r--r--arch/arm/mach-pnx4008/include/mach/entry-macro.S116
-rw-r--r--arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h241
-rw-r--r--arch/arm/mach-pnx4008/include/mach/hardware.h32
-rw-r--r--arch/arm/mach-pnx4008/include/mach/irq.h42
-rw-r--r--arch/arm/mach-pnx4008/include/mach/irqs.h215
-rw-r--r--arch/arm/mach-pnx4008/include/mach/param.h21
-rw-r--r--arch/arm/mach-pnx4008/include/mach/platform.h69
-rw-r--r--arch/arm/mach-pnx4008/include/mach/pm.h33
-rw-r--r--arch/arm/mach-pnx4008/include/mach/timex.h19
-rw-r--r--arch/arm/mach-pnx4008/include/mach/uncompress.h46
-rw-r--r--arch/arm/mach-pnx4008/irq.c121
-rw-r--r--arch/arm/mach-pnx4008/pm.c153
-rw-r--r--arch/arm/mach-pnx4008/serial.c67
-rw-r--r--arch/arm/mach-pnx4008/sleep.S195
-rw-r--r--arch/arm/mach-pnx4008/time.c134
-rw-r--r--arch/arm/mach-pnx4008/time.h70
27 files changed, 0 insertions, 4686 deletions
diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile
deleted file mode 100644
index 777564c90a12..000000000000
--- a/arch/arm/mach-pnx4008/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
6obj-m :=
7obj-n :=
8obj- :=
9
10# Power Management
11obj-$(CONFIG_PM) += pm.o sleep.o
12
diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot
deleted file mode 100644
index 9fa19baa7f2e..000000000000
--- a/arch/arm/mach-pnx4008/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1 zreladdr-y += 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
4
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
deleted file mode 100644
index a4a3819c96cb..000000000000
--- a/arch/arm/mach-pnx4008/clock.c
+++ /dev/null
@@ -1,1001 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/clock.c
3 *
4 * Clock control driver for PNX4008
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 * Generic clock management functions are partially based on:
8 * linux/arch/arm/mach-omap/clock.c
9 *
10 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/device.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/clkdev.h>
25
26#include <mach/hardware.h>
27#include <mach/clock.h>
28#include "clock.h"
29
30/*forward declaration*/
31static struct clk per_ck;
32static struct clk hclk_ck;
33static struct clk ck_1MHz;
34static struct clk ck_13MHz;
35static struct clk ck_pll1;
36static int local_set_rate(struct clk *clk, u32 rate);
37
38static inline void clock_lock(void)
39{
40 local_irq_disable();
41}
42
43static inline void clock_unlock(void)
44{
45 local_irq_enable();
46}
47
48static void propagate_rate(struct clk *clk)
49{
50 struct clk *tmp_clk;
51
52 tmp_clk = clk;
53 while (tmp_clk->propagate_next) {
54 tmp_clk = tmp_clk->propagate_next;
55 local_set_rate(tmp_clk, tmp_clk->user_rate);
56 }
57}
58
59static void clk_reg_disable(struct clk *clk)
60{
61 if (clk->enable_reg)
62 __raw_writel(__raw_readl(clk->enable_reg) &
63 ~(1 << clk->enable_shift), clk->enable_reg);
64}
65
66static int clk_reg_enable(struct clk *clk)
67{
68 if (clk->enable_reg)
69 __raw_writel(__raw_readl(clk->enable_reg) |
70 (1 << clk->enable_shift), clk->enable_reg);
71 return 0;
72}
73
74static inline void clk_reg_disable1(struct clk *clk)
75{
76 if (clk->enable_reg1)
77 __raw_writel(__raw_readl(clk->enable_reg1) &
78 ~(1 << clk->enable_shift1), clk->enable_reg1);
79}
80
81static inline void clk_reg_enable1(struct clk *clk)
82{
83 if (clk->enable_reg1)
84 __raw_writel(__raw_readl(clk->enable_reg1) |
85 (1 << clk->enable_shift1), clk->enable_reg1);
86}
87
88static int clk_wait_for_pll_lock(struct clk *clk)
89{
90 int i;
91 i = 0;
92 while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ; /*wait for PLL to lock */
93
94 if (!(__raw_readl(clk->scale_reg) & 1)) {
95 printk(KERN_ERR
96 "%s ERROR: failed to lock, scale reg data: %x\n",
97 clk->name, __raw_readl(clk->scale_reg));
98 return -1;
99 }
100 return 0;
101}
102
103static int switch_to_dirty_13mhz(struct clk *clk)
104{
105 int i;
106 int ret;
107 u32 tmp_reg;
108
109 ret = 0;
110
111 if (!clk->rate)
112 clk_reg_enable1(clk);
113
114 tmp_reg = __raw_readl(clk->parent_switch_reg);
115 /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
116 if (!(tmp_reg & 1)) {
117 tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
118 __raw_writel(tmp_reg, clk->parent_switch_reg);
119 i = 0;
120 while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13'MHz selection status */
121
122 if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
123 printk(KERN_ERR
124 "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
125 clk->name, __raw_readl(clk->parent_switch_reg));
126 ret = -1;
127 }
128 }
129
130 if (!clk->rate)
131 clk_reg_disable1(clk);
132
133 return ret;
134}
135
136static int switch_to_clean_13mhz(struct clk *clk)
137{
138 int i;
139 int ret;
140 u32 tmp_reg;
141
142 ret = 0;
143
144 if (!clk->rate)
145 clk_reg_enable1(clk);
146
147 tmp_reg = __raw_readl(clk->parent_switch_reg);
148 /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
149 if (tmp_reg & 1) {
150 tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
151 __raw_writel(tmp_reg, clk->parent_switch_reg);
152 i = 0;
153 while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13MHz selection status */
154
155 if (__raw_readl(clk->parent_switch_reg) & 1) {
156 printk(KERN_ERR
157 "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
158 clk->name, __raw_readl(clk->parent_switch_reg));
159 ret = -1;
160 }
161 }
162
163 if (!clk->rate)
164 clk_reg_disable1(clk);
165
166 return ret;
167}
168
169static int set_13MHz_parent(struct clk *clk, struct clk *parent)
170{
171 int ret = -EINVAL;
172
173 if (parent == &ck_13MHz)
174 ret = switch_to_clean_13mhz(clk);
175 else if (parent == &ck_pll1)
176 ret = switch_to_dirty_13mhz(clk);
177
178 return ret;
179}
180
181#define PLL160_MIN_FCCO 156000
182#define PLL160_MAX_FCCO 320000
183
184/*
185 * Calculate pll160 settings.
186 * Possible input: up to 320MHz with step of clk->parent->rate.
187 * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
188 * Ignored paths: "feedback" (bit 13 set), "div-by-N".
189 * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
190 * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
191 * Please refer to PNX4008 IC manual for details.
192 */
193
194static int pll160_set_rate(struct clk *clk, u32 rate)
195{
196 u32 tmp_reg, tmp_m, tmp_2p, i;
197 u32 parent_rate;
198 int ret = -EINVAL;
199
200 parent_rate = clk->parent->rate;
201
202 if (!parent_rate)
203 goto out;
204
205 /* set direct run for ARM or disable output for others */
206 clk_reg_disable(clk);
207
208 /* disable source input as well (ignored for ARM) */
209 clk_reg_disable1(clk);
210
211 tmp_reg = __raw_readl(clk->scale_reg);
212 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
213 __raw_writel(tmp_reg, clk->scale_reg);
214
215 rate -= rate % parent_rate; /*round down the input */
216
217 if (rate > PLL160_MAX_FCCO)
218 rate = PLL160_MAX_FCCO;
219
220 if (!rate) {
221 clk->rate = 0;
222 ret = 0;
223 goto out;
224 }
225
226 clk_reg_enable1(clk);
227 tmp_reg = __raw_readl(clk->scale_reg);
228
229 if (rate == parent_rate) {
230 /*enter direct bypass mode */
231 tmp_reg |= ((1 << 14) | (1 << 15));
232 __raw_writel(tmp_reg, clk->scale_reg);
233 clk->rate = parent_rate;
234 clk_reg_enable(clk);
235 ret = 0;
236 goto out;
237 }
238
239 i = 0;
240 for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
241 if (rate * tmp_2p >= PLL160_MIN_FCCO)
242 break;
243 i++;
244 }
245
246 if (tmp_2p > 1)
247 tmp_reg |= ((i - 1) << 11);
248 else
249 tmp_reg |= (1 << 14); /*direct mode, no divide */
250
251 tmp_m = rate * tmp_2p;
252 tmp_m /= parent_rate;
253
254 tmp_reg |= (tmp_m - 1) << 1; /*calculate M */
255 tmp_reg |= (1 << 16); /*power up PLL */
256 __raw_writel(tmp_reg, clk->scale_reg);
257
258 if (clk_wait_for_pll_lock(clk) < 0) {
259 clk_reg_disable(clk);
260 clk_reg_disable1(clk);
261
262 tmp_reg = __raw_readl(clk->scale_reg);
263 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
264 __raw_writel(tmp_reg, clk->scale_reg);
265 clk->rate = 0;
266 ret = -EFAULT;
267 goto out;
268 }
269
270 clk->rate = (tmp_m * parent_rate) / tmp_2p;
271
272 if (clk->flags & RATE_PROPAGATES)
273 propagate_rate(clk);
274
275 clk_reg_enable(clk);
276 ret = 0;
277
278out:
279 return ret;
280}
281
282/*configure PER_CLK*/
283static int per_clk_set_rate(struct clk *clk, u32 rate)
284{
285 u32 tmp;
286
287 tmp = __raw_readl(clk->scale_reg);
288 tmp &= ~(0x1f << 2);
289 tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
290 __raw_writel(tmp, clk->scale_reg);
291 clk->rate = rate;
292 return 0;
293}
294
295/*configure HCLK*/
296static int hclk_set_rate(struct clk *clk, u32 rate)
297{
298 u32 tmp;
299 tmp = __raw_readl(clk->scale_reg);
300 tmp = tmp & ~0x3;
301 switch (rate) {
302 case 1:
303 break;
304 case 2:
305 tmp |= 1;
306 break;
307 case 4:
308 tmp |= 2;
309 break;
310 }
311
312 __raw_writel(tmp, clk->scale_reg);
313 clk->rate = rate;
314 return 0;
315}
316
317static u32 hclk_round_rate(struct clk *clk, u32 rate)
318{
319 switch (rate) {
320 case 1:
321 case 4:
322 return rate;
323 }
324 return 2;
325}
326
327static u32 per_clk_round_rate(struct clk *clk, u32 rate)
328{
329 return CLK_RATE_13MHZ;
330}
331
332static int on_off_set_rate(struct clk *clk, u32 rate)
333{
334 if (rate) {
335 clk_reg_enable(clk);
336 clk->rate = 1;
337 } else {
338 clk_reg_disable(clk);
339 clk->rate = 0;
340 }
341 return 0;
342}
343
344static int on_off_inv_set_rate(struct clk *clk, u32 rate)
345{
346 if (rate) {
347 clk_reg_disable(clk); /*enable bit is inverted */
348 clk->rate = 1;
349 } else {
350 clk_reg_enable(clk);
351 clk->rate = 0;
352 }
353 return 0;
354}
355
356static u32 on_off_round_rate(struct clk *clk, u32 rate)
357{
358 return (rate ? 1 : 0);
359}
360
361static u32 pll4_round_rate(struct clk *clk, u32 rate)
362{
363 if (rate > CLK_RATE_208MHZ)
364 rate = CLK_RATE_208MHZ;
365 if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
366 rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
367 return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
368}
369
370static u32 pll3_round_rate(struct clk *clk, u32 rate)
371{
372 if (rate > CLK_RATE_208MHZ)
373 rate = CLK_RATE_208MHZ;
374 return (rate - rate % CLK_RATE_13MHZ);
375}
376
377static u32 pll5_round_rate(struct clk *clk, u32 rate)
378{
379 return (rate ? CLK_RATE_48MHZ : 0);
380}
381
382static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
383{
384 return (rate ? CLK_RATE_13MHZ : 0);
385}
386
387static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
388{
389 if (rate) {
390 clk_reg_disable(clk); /*enable bit is inverted */
391 udelay(500);
392 clk->rate = CLK_RATE_13MHZ;
393 ck_1MHz.rate = CLK_RATE_1MHZ;
394 } else {
395 clk_reg_enable(clk);
396 clk->rate = 0;
397 ck_1MHz.rate = 0;
398 }
399 return 0;
400}
401
402static int pll1_set_rate(struct clk *clk, u32 rate)
403{
404#if 0 /* doesn't work on some boards, probably a HW BUG */
405 if (rate) {
406 clk_reg_disable(clk); /*enable bit is inverted */
407 if (!clk_wait_for_pll_lock(clk)) {
408 clk->rate = CLK_RATE_13MHZ;
409 } else {
410 clk_reg_enable(clk);
411 clk->rate = 0;
412 }
413
414 } else {
415 clk_reg_enable(clk);
416 clk->rate = 0;
417 }
418#endif
419 return 0;
420}
421
422/* Clock sources */
423
424static struct clk osc_13MHz = {
425 .name = "osc_13MHz",
426 .flags = FIXED_RATE,
427 .rate = CLK_RATE_13MHZ,
428};
429
430static struct clk ck_13MHz = {
431 .name = "ck_13MHz",
432 .parent = &osc_13MHz,
433 .flags = NEEDS_INITIALIZATION,
434 .round_rate = &ck_13MHz_round_rate,
435 .set_rate = &ck_13MHz_set_rate,
436 .enable_reg = OSC13CTRL_REG,
437 .enable_shift = 0,
438 .rate = CLK_RATE_13MHZ,
439};
440
441static struct clk osc_32KHz = {
442 .name = "osc_32KHz",
443 .flags = FIXED_RATE,
444 .rate = CLK_RATE_32KHZ,
445};
446
447/*attached to PLL5*/
448static struct clk ck_1MHz = {
449 .name = "ck_1MHz",
450 .flags = FIXED_RATE | PARENT_SET_RATE,
451 .parent = &ck_13MHz,
452};
453
454/* PLL1 (397) - provides 13' MHz clock */
455static struct clk ck_pll1 = {
456 .name = "ck_pll1",
457 .parent = &osc_32KHz,
458 .flags = NEEDS_INITIALIZATION,
459 .round_rate = &ck_13MHz_round_rate,
460 .set_rate = &pll1_set_rate,
461 .enable_reg = PLLCTRL_REG,
462 .enable_shift = 1,
463 .scale_reg = PLLCTRL_REG,
464 .rate = CLK_RATE_13MHZ,
465};
466
467/* CPU/Bus PLL */
468static struct clk ck_pll4 = {
469 .name = "ck_pll4",
470 .parent = &ck_pll1,
471 .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
472 .propagate_next = &per_ck,
473 .round_rate = &pll4_round_rate,
474 .set_rate = &pll160_set_rate,
475 .rate = CLK_RATE_208MHZ,
476 .scale_reg = HCLKPLLCTRL_REG,
477 .enable_reg = PWRCTRL_REG,
478 .enable_shift = 2,
479 .parent_switch_reg = SYSCLKCTRL_REG,
480 .set_parent = &set_13MHz_parent,
481};
482
483/* USB PLL */
484static struct clk ck_pll5 = {
485 .name = "ck_pll5",
486 .parent = &ck_1MHz,
487 .flags = NEEDS_INITIALIZATION,
488 .round_rate = &pll5_round_rate,
489 .set_rate = &pll160_set_rate,
490 .scale_reg = USBCTRL_REG,
491 .enable_reg = USBCTRL_REG,
492 .enable_shift = 18,
493 .enable_reg1 = USBCTRL_REG,
494 .enable_shift1 = 17,
495};
496
497/* XPERTTeak DSP PLL */
498static struct clk ck_pll3 = {
499 .name = "ck_pll3",
500 .parent = &ck_pll1,
501 .flags = NEEDS_INITIALIZATION,
502 .round_rate = &pll3_round_rate,
503 .set_rate = &pll160_set_rate,
504 .scale_reg = DSPPLLCTRL_REG,
505 .enable_reg = DSPCLKCTRL_REG,
506 .enable_shift = 3,
507 .enable_reg1 = DSPCLKCTRL_REG,
508 .enable_shift1 = 2,
509 .parent_switch_reg = DSPCLKCTRL_REG,
510 .set_parent = &set_13MHz_parent,
511};
512
513static struct clk hclk_ck = {
514 .name = "hclk_ck",
515 .parent = &ck_pll4,
516 .flags = PARENT_SET_RATE,
517 .set_rate = &hclk_set_rate,
518 .round_rate = &hclk_round_rate,
519 .scale_reg = HCLKDIVCTRL_REG,
520 .rate = 2,
521 .user_rate = 2,
522};
523
524static struct clk per_ck = {
525 .name = "per_ck",
526 .parent = &ck_pll4,
527 .flags = FIXED_RATE,
528 .propagate_next = &hclk_ck,
529 .set_rate = &per_clk_set_rate,
530 .round_rate = &per_clk_round_rate,
531 .scale_reg = HCLKDIVCTRL_REG,
532 .rate = CLK_RATE_13MHZ,
533 .user_rate = CLK_RATE_13MHZ,
534};
535
536static struct clk m2hclk_ck = {
537 .name = "m2hclk_ck",
538 .parent = &hclk_ck,
539 .flags = NEEDS_INITIALIZATION,
540 .round_rate = &on_off_round_rate,
541 .set_rate = &on_off_inv_set_rate,
542 .rate = 1,
543 .enable_shift = 6,
544 .enable_reg = PWRCTRL_REG,
545};
546
547static struct clk vfp9_ck = {
548 .name = "vfp9_ck",
549 .parent = &ck_pll4,
550 .flags = NEEDS_INITIALIZATION,
551 .round_rate = &on_off_round_rate,
552 .set_rate = &on_off_set_rate,
553 .rate = 1,
554 .enable_shift = 4,
555 .enable_reg = VFP9CLKCTRL_REG,
556};
557
558static struct clk keyscan_ck = {
559 .name = "keyscan_ck",
560 .parent = &osc_32KHz,
561 .flags = NEEDS_INITIALIZATION,
562 .round_rate = &on_off_round_rate,
563 .set_rate = &on_off_set_rate,
564 .enable_shift = 0,
565 .enable_reg = KEYCLKCTRL_REG,
566};
567
568static struct clk touch_ck = {
569 .name = "touch_ck",
570 .parent = &osc_32KHz,
571 .flags = NEEDS_INITIALIZATION,
572 .round_rate = &on_off_round_rate,
573 .set_rate = &on_off_set_rate,
574 .enable_shift = 0,
575 .enable_reg = TSCLKCTRL_REG,
576};
577
578static struct clk pwm1_ck = {
579 .name = "pwm1_ck",
580 .parent = &osc_32KHz,
581 .flags = NEEDS_INITIALIZATION,
582 .round_rate = &on_off_round_rate,
583 .set_rate = &on_off_set_rate,
584 .enable_shift = 0,
585 .enable_reg = PWMCLKCTRL_REG,
586};
587
588static struct clk pwm2_ck = {
589 .name = "pwm2_ck",
590 .parent = &osc_32KHz,
591 .flags = NEEDS_INITIALIZATION,
592 .round_rate = &on_off_round_rate,
593 .set_rate = &on_off_set_rate,
594 .enable_shift = 2,
595 .enable_reg = PWMCLKCTRL_REG,
596};
597
598static struct clk jpeg_ck = {
599 .name = "jpeg_ck",
600 .parent = &hclk_ck,
601 .flags = NEEDS_INITIALIZATION,
602 .round_rate = &on_off_round_rate,
603 .set_rate = &on_off_set_rate,
604 .enable_shift = 0,
605 .enable_reg = JPEGCLKCTRL_REG,
606};
607
608static struct clk ms_ck = {
609 .name = "ms_ck",
610 .parent = &ck_pll4,
611 .flags = NEEDS_INITIALIZATION,
612 .round_rate = &on_off_round_rate,
613 .set_rate = &on_off_set_rate,
614 .enable_shift = 5,
615 .enable_reg = MSCTRL_REG,
616};
617
618static struct clk dum_ck = {
619 .name = "dum_ck",
620 .parent = &hclk_ck,
621 .flags = NEEDS_INITIALIZATION,
622 .round_rate = &on_off_round_rate,
623 .set_rate = &on_off_set_rate,
624 .enable_shift = 0,
625 .enable_reg = DUMCLKCTRL_REG,
626};
627
628static struct clk flash_ck = {
629 .name = "flash_ck",
630 .parent = &hclk_ck,
631 .round_rate = &on_off_round_rate,
632 .set_rate = &on_off_set_rate,
633 .enable_shift = 1, /* Only MLC clock supported */
634 .enable_reg = FLASHCLKCTRL_REG,
635};
636
637static struct clk i2c0_ck = {
638 .name = "i2c0_ck",
639 .parent = &per_ck,
640 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
641 .enable_shift = 0,
642 .enable_reg = I2CCLKCTRL_REG,
643 .rate = 13000000,
644 .enable = clk_reg_enable,
645 .disable = clk_reg_disable,
646};
647
648static struct clk i2c1_ck = {
649 .name = "i2c1_ck",
650 .parent = &per_ck,
651 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
652 .enable_shift = 1,
653 .enable_reg = I2CCLKCTRL_REG,
654 .rate = 13000000,
655 .enable = clk_reg_enable,
656 .disable = clk_reg_disable,
657};
658
659static struct clk i2c2_ck = {
660 .name = "i2c2_ck",
661 .parent = &per_ck,
662 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
663 .enable_shift = 2,
664 .enable_reg = USB_OTG_CLKCTRL_REG,
665 .rate = 13000000,
666 .enable = clk_reg_enable,
667 .disable = clk_reg_disable,
668};
669
670static struct clk spi0_ck = {
671 .name = "spi0_ck",
672 .parent = &hclk_ck,
673 .flags = NEEDS_INITIALIZATION,
674 .round_rate = &on_off_round_rate,
675 .set_rate = &on_off_set_rate,
676 .enable_shift = 0,
677 .enable_reg = SPICTRL_REG,
678};
679
680static struct clk spi1_ck = {
681 .name = "spi1_ck",
682 .parent = &hclk_ck,
683 .flags = NEEDS_INITIALIZATION,
684 .round_rate = &on_off_round_rate,
685 .set_rate = &on_off_set_rate,
686 .enable_shift = 4,
687 .enable_reg = SPICTRL_REG,
688};
689
690static struct clk dma_ck = {
691 .name = "dma_ck",
692 .parent = &hclk_ck,
693 .round_rate = &on_off_round_rate,
694 .set_rate = &on_off_set_rate,
695 .enable_shift = 0,
696 .enable_reg = DMACLKCTRL_REG,
697};
698
699static struct clk uart3_ck = {
700 .name = "uart3_ck",
701 .parent = &per_ck,
702 .flags = NEEDS_INITIALIZATION,
703 .round_rate = &on_off_round_rate,
704 .set_rate = &on_off_set_rate,
705 .rate = 1,
706 .enable_shift = 0,
707 .enable_reg = UARTCLKCTRL_REG,
708};
709
710static struct clk uart4_ck = {
711 .name = "uart4_ck",
712 .parent = &per_ck,
713 .flags = NEEDS_INITIALIZATION,
714 .round_rate = &on_off_round_rate,
715 .set_rate = &on_off_set_rate,
716 .enable_shift = 1,
717 .enable_reg = UARTCLKCTRL_REG,
718};
719
720static struct clk uart5_ck = {
721 .name = "uart5_ck",
722 .parent = &per_ck,
723 .flags = NEEDS_INITIALIZATION,
724 .round_rate = &on_off_round_rate,
725 .set_rate = &on_off_set_rate,
726 .rate = 1,
727 .enable_shift = 2,
728 .enable_reg = UARTCLKCTRL_REG,
729};
730
731static struct clk uart6_ck = {
732 .name = "uart6_ck",
733 .parent = &per_ck,
734 .flags = NEEDS_INITIALIZATION,
735 .round_rate = &on_off_round_rate,
736 .set_rate = &on_off_set_rate,
737 .enable_shift = 3,
738 .enable_reg = UARTCLKCTRL_REG,
739};
740
741static struct clk wdt_ck = {
742 .name = "wdt_ck",
743 .parent = &per_ck,
744 .flags = NEEDS_INITIALIZATION,
745 .enable_shift = 0,
746 .enable_reg = TIMCLKCTRL_REG,
747 .enable = clk_reg_enable,
748 .disable = clk_reg_disable,
749};
750
751/* These clocks are visible outside this module
752 * and can be initialized
753 */
754static struct clk *onchip_clks[] __initdata = {
755 &ck_13MHz,
756 &ck_pll1,
757 &ck_pll4,
758 &ck_pll5,
759 &ck_pll3,
760 &vfp9_ck,
761 &m2hclk_ck,
762 &hclk_ck,
763 &dma_ck,
764 &flash_ck,
765 &dum_ck,
766 &keyscan_ck,
767 &pwm1_ck,
768 &pwm2_ck,
769 &jpeg_ck,
770 &ms_ck,
771 &touch_ck,
772 &i2c0_ck,
773 &i2c1_ck,
774 &i2c2_ck,
775 &spi0_ck,
776 &spi1_ck,
777 &uart3_ck,
778 &uart4_ck,
779 &uart5_ck,
780 &uart6_ck,
781 &wdt_ck,
782};
783
784static struct clk_lookup onchip_clkreg[] = {
785 { .clk = &ck_13MHz, .con_id = "ck_13MHz" },
786 { .clk = &ck_pll1, .con_id = "ck_pll1" },
787 { .clk = &ck_pll4, .con_id = "ck_pll4" },
788 { .clk = &ck_pll5, .con_id = "ck_pll5" },
789 { .clk = &ck_pll3, .con_id = "ck_pll3" },
790 { .clk = &vfp9_ck, .con_id = "vfp9_ck" },
791 { .clk = &m2hclk_ck, .con_id = "m2hclk_ck" },
792 { .clk = &hclk_ck, .con_id = "hclk_ck" },
793 { .clk = &dma_ck, .con_id = "dma_ck" },
794 { .clk = &flash_ck, .con_id = "flash_ck" },
795 { .clk = &dum_ck, .con_id = "dum_ck" },
796 { .clk = &keyscan_ck, .con_id = "keyscan_ck" },
797 { .clk = &pwm1_ck, .con_id = "pwm1_ck" },
798 { .clk = &pwm2_ck, .con_id = "pwm2_ck" },
799 { .clk = &jpeg_ck, .con_id = "jpeg_ck" },
800 { .clk = &ms_ck, .con_id = "ms_ck" },
801 { .clk = &touch_ck, .con_id = "touch_ck" },
802 { .clk = &i2c0_ck, .dev_id = "pnx-i2c.0" },
803 { .clk = &i2c1_ck, .dev_id = "pnx-i2c.1" },
804 { .clk = &i2c2_ck, .dev_id = "pnx-i2c.2" },
805 { .clk = &spi0_ck, .con_id = "spi0_ck" },
806 { .clk = &spi1_ck, .con_id = "spi1_ck" },
807 { .clk = &uart3_ck, .con_id = "uart3_ck" },
808 { .clk = &uart4_ck, .con_id = "uart4_ck" },
809 { .clk = &uart5_ck, .con_id = "uart5_ck" },
810 { .clk = &uart6_ck, .con_id = "uart6_ck" },
811 { .clk = &wdt_ck, .dev_id = "pnx4008-watchdog" },
812};
813
814static void local_clk_disable(struct clk *clk)
815{
816 if (WARN_ON(clk->usecount == 0))
817 return;
818
819 if (!(--clk->usecount)) {
820 if (clk->disable)
821 clk->disable(clk);
822 else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
823 clk->set_rate(clk, 0);
824 if (clk->parent)
825 local_clk_disable(clk->parent);
826 }
827}
828
829static int local_clk_enable(struct clk *clk)
830{
831 int ret = 0;
832
833 if (clk->usecount == 0) {
834 if (clk->parent) {
835 ret = local_clk_enable(clk->parent);
836 if (ret != 0)
837 goto out;
838 }
839
840 if (clk->enable)
841 ret = clk->enable(clk);
842 else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
843 && clk->user_rate)
844 ret = clk->set_rate(clk, clk->user_rate);
845
846 if (ret != 0 && clk->parent) {
847 local_clk_disable(clk->parent);
848 goto out;
849 }
850
851 clk->usecount++;
852 }
853out:
854 return ret;
855}
856
857static int local_set_rate(struct clk *clk, u32 rate)
858{
859 int ret = -EINVAL;
860 if (clk->set_rate) {
861
862 if (clk->user_rate == clk->rate && clk->parent->rate) {
863 /* if clock enabled or rate not set */
864 clk->user_rate = clk->round_rate(clk, rate);
865 ret = clk->set_rate(clk, clk->user_rate);
866 } else
867 clk->user_rate = clk->round_rate(clk, rate);
868 ret = 0;
869 }
870 return ret;
871}
872
873int clk_set_rate(struct clk *clk, unsigned long rate)
874{
875 int ret = -EINVAL;
876
877 if (clk->flags & FIXED_RATE)
878 goto out;
879
880 clock_lock();
881 if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
882
883 clk->user_rate = clk->round_rate(clk, rate);
884 /* parent clock needs to be refreshed
885 for the setting to take effect */
886 } else {
887 ret = local_set_rate(clk, rate);
888 }
889 ret = 0;
890 clock_unlock();
891
892out:
893 return ret;
894}
895
896EXPORT_SYMBOL(clk_set_rate);
897
898unsigned long clk_get_rate(struct clk *clk)
899{
900 unsigned long ret;
901 clock_lock();
902 ret = clk->rate;
903 clock_unlock();
904 return ret;
905}
906EXPORT_SYMBOL(clk_get_rate);
907
908int clk_enable(struct clk *clk)
909{
910 int ret;
911
912 clock_lock();
913 ret = local_clk_enable(clk);
914 clock_unlock();
915 return ret;
916}
917
918EXPORT_SYMBOL(clk_enable);
919
920void clk_disable(struct clk *clk)
921{
922 clock_lock();
923 local_clk_disable(clk);
924 clock_unlock();
925}
926
927EXPORT_SYMBOL(clk_disable);
928
929long clk_round_rate(struct clk *clk, unsigned long rate)
930{
931 long ret;
932 clock_lock();
933 if (clk->round_rate)
934 ret = clk->round_rate(clk, rate);
935 else
936 ret = clk->rate;
937 clock_unlock();
938 return ret;
939}
940
941EXPORT_SYMBOL(clk_round_rate);
942
943int clk_set_parent(struct clk *clk, struct clk *parent)
944{
945 int ret = -ENODEV;
946 if (!clk->set_parent)
947 goto out;
948
949 clock_lock();
950 ret = clk->set_parent(clk, parent);
951 if (!ret)
952 clk->parent = parent;
953 clock_unlock();
954
955out:
956 return ret;
957}
958
959EXPORT_SYMBOL(clk_set_parent);
960
961static int __init clk_init(void)
962{
963 struct clk **clkp;
964
965 /* Disable autoclocking, as it doesn't seem to work */
966 __raw_writel(0xff, AUTOCLK_CTRL);
967
968 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
969 clkp++) {
970 struct clk *clk = *clkp;
971 if (clk->flags & NEEDS_INITIALIZATION) {
972 if (clk->set_rate) {
973 clk->user_rate = clk->rate;
974 local_set_rate(clk, clk->user_rate);
975 if (clk->set_parent)
976 clk->set_parent(clk, clk->parent);
977 }
978 if (clk->enable && clk->usecount)
979 clk->enable(clk);
980 if (clk->disable && !clk->usecount)
981 clk->disable(clk);
982 }
983 pr_debug("%s: clock %s, rate %ld\n",
984 __func__, clk->name, clk->rate);
985 }
986
987 local_clk_enable(&ck_pll4);
988
989 /* if ck_13MHz is not used, disable it. */
990 if (ck_13MHz.usecount == 0)
991 local_clk_disable(&ck_13MHz);
992
993 /* Disable autoclocking */
994 __raw_writeb(0xff, AUTOCLK_CTRL);
995
996 clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
997
998 return 0;
999}
1000
1001arch_initcall(clk_init);
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
deleted file mode 100644
index 39720d6c0d01..000000000000
--- a/arch/arm/mach-pnx4008/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/clock.h
3 *
4 * Clock control driver for PNX4008 - internal header file
5 *
6 * Author: Vitaly Wool <source@mvista.com>
7 *
8 * 2006 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
14#define __ARCH_ARM_PNX4008_CLOCK_H__
15
16struct clk {
17 const char *name;
18 struct clk *parent;
19 struct clk *propagate_next;
20 u32 rate;
21 u32 user_rate;
22 s8 usecount;
23 u32 flags;
24 u32 scale_reg;
25 u8 enable_shift;
26 u32 enable_reg;
27 u8 enable_shift1;
28 u32 enable_reg1;
29 u32 parent_switch_reg;
30 u32(*round_rate) (struct clk *, u32);
31 int (*set_rate) (struct clk *, u32);
32 int (*set_parent) (struct clk * clk, struct clk * parent);
33 int (*enable)(struct clk *);
34 void (*disable)(struct clk *);
35};
36
37/* Flags */
38#define RATE_PROPAGATES (1<<0)
39#define NEEDS_INITIALIZATION (1<<1)
40#define PARENT_SET_RATE (1<<2)
41#define FIXED_RATE (1<<3)
42
43#endif
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
deleted file mode 100644
index a00d2f1254ed..000000000000
--- a/arch/arm/mach-pnx4008/core.c
+++ /dev/null
@@ -1,290 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/core.c
3 *
4 * PNX4008 core startup code
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev,
7 * Grigory Tolstolytkin, Dmitry Pervushin <source@mvista.com>
8 *
9 * Based on reference code received from Philips:
10 * Copyright (C) 2003 Philips Semiconductors
11 *
12 * 2005 (c) MontaVista Software, Inc. This file is licensed under
13 * the terms of the GNU General Public License version 2. This program
14 * is licensed "as is" without any warranty of any kind, whether express
15 * or implied.
16 */
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/list.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/serial_8250.h>
26#include <linux/device.h>
27#include <linux/spi/spi.h>
28#include <linux/io.h>
29
30#include <mach/hardware.h>
31#include <asm/setup.h>
32#include <asm/mach-types.h>
33#include <asm/pgtable.h>
34#include <asm/page.h>
35#include <asm/system_misc.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/time.h>
40
41#include <mach/irq.h>
42#include <mach/clock.h>
43#include <mach/dma.h>
44
45struct resource spipnx_0_resources[] = {
46 {
47 .start = PNX4008_SPI1_BASE,
48 .end = PNX4008_SPI1_BASE + SZ_4K,
49 .flags = IORESOURCE_MEM,
50 }, {
51 .start = PER_SPI1_REC_XMIT,
52 .flags = IORESOURCE_DMA,
53 }, {
54 .start = SPI1_INT,
55 .flags = IORESOURCE_IRQ,
56 }, {
57 .flags = 0,
58 },
59};
60
61struct resource spipnx_1_resources[] = {
62 {
63 .start = PNX4008_SPI2_BASE,
64 .end = PNX4008_SPI2_BASE + SZ_4K,
65 .flags = IORESOURCE_MEM,
66 }, {
67 .start = PER_SPI2_REC_XMIT,
68 .flags = IORESOURCE_DMA,
69 }, {
70 .start = SPI2_INT,
71 .flags = IORESOURCE_IRQ,
72 }, {
73 .flags = 0,
74 }
75};
76
77static struct spi_board_info spi_board_info[] __initdata = {
78 {
79 .modalias = "m25p80",
80 .max_speed_hz = 1000000,
81 .bus_num = 1,
82 .chip_select = 0,
83 },
84};
85
86static struct platform_device spipnx_1 = {
87 .name = "spipnx",
88 .id = 1,
89 .num_resources = ARRAY_SIZE(spipnx_0_resources),
90 .resource = spipnx_0_resources,
91 .dev = {
92 .coherent_dma_mask = 0xFFFFFFFF,
93 },
94};
95
96static struct platform_device spipnx_2 = {
97 .name = "spipnx",
98 .id = 2,
99 .num_resources = ARRAY_SIZE(spipnx_1_resources),
100 .resource = spipnx_1_resources,
101 .dev = {
102 .coherent_dma_mask = 0xFFFFFFFF,
103 },
104};
105
106static struct plat_serial8250_port platform_serial_ports[] = {
107 {
108 .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
109 .mapbase = (unsigned long)PNX4008_UART5_BASE,
110 .irq = IIR5_INT,
111 .uartclk = PNX4008_UART_CLK,
112 .regshift = 2,
113 .iotype = UPIO_MEM,
114 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
115 },
116 {
117 .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
118 .mapbase = (unsigned long)PNX4008_UART3_BASE,
119 .irq = IIR3_INT,
120 .uartclk = PNX4008_UART_CLK,
121 .regshift = 2,
122 .iotype = UPIO_MEM,
123 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
124 },
125 {}
126};
127
128static struct platform_device serial_device = {
129 .name = "serial8250",
130 .id = PLAT8250_DEV_PLATFORM,
131 .dev = {
132 .platform_data = &platform_serial_ports,
133 },
134};
135
136static struct platform_device nand_flash_device = {
137 .name = "pnx4008-flash",
138 .id = -1,
139 .dev = {
140 .coherent_dma_mask = 0xFFFFFFFF,
141 },
142};
143
144/* The dmamask must be set for OHCI to work */
145static u64 ohci_dmamask = ~(u32) 0;
146
147static struct resource ohci_resources[] = {
148 {
149 .start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
150 .end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
151 .flags = IORESOURCE_MEM,
152 }, {
153 .start = USB_HOST_INT,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device ohci_device = {
159 .name = "pnx4008-usb-ohci",
160 .id = -1,
161 .dev = {
162 .dma_mask = &ohci_dmamask,
163 .coherent_dma_mask = 0xffffffff,
164 },
165 .num_resources = ARRAY_SIZE(ohci_resources),
166 .resource = ohci_resources,
167};
168
169static struct platform_device sdum_device = {
170 .name = "pnx4008-sdum",
171 .id = 0,
172 .dev = {
173 .coherent_dma_mask = 0xffffffff,
174 },
175};
176
177static struct platform_device rgbfb_device = {
178 .name = "pnx4008-rgbfb",
179 .id = 0,
180 .dev = {
181 .coherent_dma_mask = 0xffffffff,
182 }
183};
184
185struct resource watchdog_resources[] = {
186 {
187 .start = PNX4008_WDOG_BASE,
188 .end = PNX4008_WDOG_BASE + SZ_4K - 1,
189 .flags = IORESOURCE_MEM,
190 },
191};
192
193static struct platform_device watchdog_device = {
194 .name = "pnx4008-watchdog",
195 .id = -1,
196 .num_resources = ARRAY_SIZE(watchdog_resources),
197 .resource = watchdog_resources,
198};
199
200static struct platform_device *devices[] __initdata = {
201 &spipnx_1,
202 &spipnx_2,
203 &serial_device,
204 &ohci_device,
205 &nand_flash_device,
206 &sdum_device,
207 &rgbfb_device,
208 &watchdog_device,
209};
210
211
212extern void pnx4008_uart_init(void);
213
214static void __init pnx4008_init(void)
215{
216 /*disable all START interrupt sources,
217 and clear all START interrupt flags */
218 __raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
219 __raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
220 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
221 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
222
223 platform_add_devices(devices, ARRAY_SIZE(devices));
224 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
225 /* Switch on the UART clocks */
226 pnx4008_uart_init();
227}
228
229static struct map_desc pnx4008_io_desc[] __initdata = {
230 {
231 .virtual = IO_ADDRESS(PNX4008_IRAM_BASE),
232 .pfn = __phys_to_pfn(PNX4008_IRAM_BASE),
233 .length = SZ_64K,
234 .type = MT_DEVICE,
235 }, {
236 .virtual = IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
237 .pfn = __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
238 .length = SZ_1M - SZ_128K,
239 .type = MT_DEVICE,
240 }, {
241 .virtual = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
242 .pfn = __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
243 .length = SZ_128K * 3,
244 .type = MT_DEVICE,
245 }, {
246 .virtual = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
247 .pfn = __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
248 .length = SZ_1M,
249 .type = MT_DEVICE,
250 }, {
251 .virtual = IO_ADDRESS(PNX4008_AHB2FAB_BASE),
252 .pfn = __phys_to_pfn(PNX4008_AHB2FAB_BASE),
253 .length = SZ_1M,
254 .type = MT_DEVICE,
255 },
256};
257
258void __init pnx4008_map_io(void)
259{
260 iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
261}
262
263static void pnx4008_restart(char mode, const char *cmd)
264{
265 soft_restart(0);
266}
267
268#ifdef CONFIG_PM
269extern int pnx4008_pm_init(void);
270#else
271static inline int pnx4008_pm_init(void) { return 0; }
272#endif
273
274void __init pnx4008_init_late(void)
275{
276 pnx4008_pm_init();
277}
278
279extern struct sys_timer pnx4008_timer;
280
281MACHINE_START(PNX4008, "Philips PNX4008")
282 /* Maintainer: MontaVista Software Inc. */
283 .atag_offset = 0x100,
284 .map_io = pnx4008_map_io,
285 .init_irq = pnx4008_init_irq,
286 .init_machine = pnx4008_init,
287 .init_late = pnx4008_init_late,
288 .timer = &pnx4008_timer,
289 .restart = pnx4008_restart,
290MACHINE_END
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
deleted file mode 100644
index a4739e9fb2fb..000000000000
--- a/arch/arm/mach-pnx4008/dma.c
+++ /dev/null
@@ -1,1105 +0,0 @@
1/*
2 * linux/arch/arm/mach-pnx4008/dma.c
3 *
4 * PNX4008 DMA registration and IRQ dispatching
5 *
6 * Author: Vitaly Wool
7 * Copyright: MontaVista Software Inc. (c) 2005
8 *
9 * Based on the code from Nicolas Pitre
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/interrupt.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/dma-mapping.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/gfp.h>
26
27#include <mach/hardware.h>
28#include <mach/dma.h>
29#include <asm/dma-mapping.h>
30#include <mach/clock.h>
31
32static struct dma_channel {
33 char *name;
34 void (*irq_handler) (int, int, void *);
35 void *data;
36 struct pnx4008_dma_ll *ll;
37 u32 ll_dma;
38 void *target_addr;
39 int target_id;
40} dma_channels[MAX_DMA_CHANNELS];
41
42static struct ll_pool {
43 void *vaddr;
44 void *cur;
45 dma_addr_t dma_addr;
46 int count;
47} ll_pool;
48
49static DEFINE_SPINLOCK(ll_lock);
50
51struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
52{
53 struct pnx4008_dma_ll *ll = NULL;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ll_lock, flags);
57 if (ll_pool.count > 4) { /* can give one more */
58 ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
59 *ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
60 *(void **)ll_pool.cur = **(void ***)ll_pool.cur;
61 memset(ll, 0, sizeof(*ll));
62 ll_pool.count--;
63 }
64 spin_unlock_irqrestore(&ll_lock, flags);
65
66 return ll;
67}
68
69EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
70
71void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
72{
73 unsigned long flags;
74
75 if (ll) {
76 if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
77 printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
78 BUG();
79 }
80
81 if (ll->flags & DMA_BUFFER_ALLOCATED)
82 ll->free(ll->alloc_data);
83
84 spin_lock_irqsave(&ll_lock, flags);
85 *(long *)ll = *(long *)ll_pool.cur;
86 *(long *)ll_pool.cur = (long)ll;
87 ll_pool.count++;
88 spin_unlock_irqrestore(&ll_lock, flags);
89 }
90}
91
92EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
93
94void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
95{
96 struct pnx4008_dma_ll *ptr;
97 u32 dma;
98
99 while (ll) {
100 dma = ll->next_dma;
101 ptr = ll->next;
102 pnx4008_free_ll_entry(ll, ll_dma);
103
104 ll_dma = dma;
105 ll = ptr;
106 }
107}
108
109EXPORT_SYMBOL_GPL(pnx4008_free_ll);
110
111static int dma_channels_requested = 0;
112
113static inline void dma_increment_usage(void)
114{
115 if (!dma_channels_requested++) {
116 struct clk *clk = clk_get(0, "dma_ck");
117 if (!IS_ERR(clk)) {
118 clk_set_rate(clk, 1);
119 clk_put(clk);
120 }
121 pnx4008_config_dma(-1, -1, 1);
122 }
123}
124static inline void dma_decrement_usage(void)
125{
126 if (!--dma_channels_requested) {
127 struct clk *clk = clk_get(0, "dma_ck");
128 if (!IS_ERR(clk)) {
129 clk_set_rate(clk, 0);
130 clk_put(clk);
131 }
132 pnx4008_config_dma(-1, -1, 0);
133
134 }
135}
136
137static DEFINE_SPINLOCK(dma_lock);
138
139static inline void pnx4008_dma_lock(void)
140{
141 spin_lock_irq(&dma_lock);
142}
143
144static inline void pnx4008_dma_unlock(void)
145{
146 spin_unlock_irq(&dma_lock);
147}
148
149#define VALID_CHANNEL(c) (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
150
151int pnx4008_request_channel(char *name, int ch,
152 void (*irq_handler) (int, int, void *), void *data)
153{
154 int i, found = 0;
155
156 /* basic sanity checks */
157 if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
158 return -EINVAL;
159
160 pnx4008_dma_lock();
161
162 /* try grabbing a DMA channel with the requested priority */
163 for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
164 if (!dma_channels[i].name && (ch == -1 || ch == i)) {
165 found = 1;
166 break;
167 }
168 }
169
170 if (found) {
171 dma_increment_usage();
172 dma_channels[i].name = name;
173 dma_channels[i].irq_handler = irq_handler;
174 dma_channels[i].data = data;
175 dma_channels[i].ll = NULL;
176 dma_channels[i].ll_dma = 0;
177 } else {
178 printk(KERN_WARNING "No more available DMA channels for %s\n",
179 name);
180 i = -ENODEV;
181 }
182
183 pnx4008_dma_unlock();
184 return i;
185}
186
187EXPORT_SYMBOL_GPL(pnx4008_request_channel);
188
189void pnx4008_free_channel(int ch)
190{
191 if (!dma_channels[ch].name) {
192 printk(KERN_CRIT
193 "%s: trying to free channel %d which is already freed\n",
194 __func__, ch);
195 return;
196 }
197
198 pnx4008_dma_lock();
199 pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
200 dma_channels[ch].ll = NULL;
201 dma_decrement_usage();
202
203 dma_channels[ch].name = NULL;
204 pnx4008_dma_unlock();
205}
206
207EXPORT_SYMBOL_GPL(pnx4008_free_channel);
208
209int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
210{
211 unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
212
213 switch (ahb_m1_be) {
214 case 0:
215 dma_cfg &= ~(1 << 1);
216 break;
217 case 1:
218 dma_cfg |= (1 << 1);
219 break;
220 default:
221 break;
222 }
223
224 switch (ahb_m2_be) {
225 case 0:
226 dma_cfg &= ~(1 << 2);
227 break;
228 case 1:
229 dma_cfg |= (1 << 2);
230 break;
231 default:
232 break;
233 }
234
235 switch (enable) {
236 case 0:
237 dma_cfg &= ~(1 << 0);
238 break;
239 case 1:
240 dma_cfg |= (1 << 0);
241 break;
242 default:
243 break;
244 }
245
246 pnx4008_dma_lock();
247 __raw_writel(dma_cfg, DMAC_CONFIG);
248 pnx4008_dma_unlock();
249
250 return 0;
251}
252
253EXPORT_SYMBOL_GPL(pnx4008_config_dma);
254
255int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
256 unsigned long *ctrl)
257{
258 int i = 0, dbsize, sbsize, err = 0;
259
260 if (!ctrl || !ch_ctrl) {
261 err = -EINVAL;
262 goto out;
263 }
264
265 *ctrl = 0;
266
267 switch (ch_ctrl->tc_mask) {
268 case 0:
269 break;
270 case 1:
271 *ctrl |= (1 << 31);
272 break;
273
274 default:
275 err = -EINVAL;
276 goto out;
277 }
278
279 switch (ch_ctrl->cacheable) {
280 case 0:
281 break;
282 case 1:
283 *ctrl |= (1 << 30);
284 break;
285
286 default:
287 err = -EINVAL;
288 goto out;
289 }
290 switch (ch_ctrl->bufferable) {
291 case 0:
292 break;
293 case 1:
294 *ctrl |= (1 << 29);
295 break;
296
297 default:
298 err = -EINVAL;
299 goto out;
300 }
301 switch (ch_ctrl->priv_mode) {
302 case 0:
303 break;
304 case 1:
305 *ctrl |= (1 << 28);
306 break;
307
308 default:
309 err = -EINVAL;
310 goto out;
311 }
312 switch (ch_ctrl->di) {
313 case 0:
314 break;
315 case 1:
316 *ctrl |= (1 << 27);
317 break;
318
319 default:
320 err = -EINVAL;
321 goto out;
322 }
323 switch (ch_ctrl->si) {
324 case 0:
325 break;
326 case 1:
327 *ctrl |= (1 << 26);
328 break;
329
330 default:
331 err = -EINVAL;
332 goto out;
333 }
334 switch (ch_ctrl->dest_ahb1) {
335 case 0:
336 break;
337 case 1:
338 *ctrl |= (1 << 25);
339 break;
340
341 default:
342 err = -EINVAL;
343 goto out;
344 }
345 switch (ch_ctrl->src_ahb1) {
346 case 0:
347 break;
348 case 1:
349 *ctrl |= (1 << 24);
350 break;
351
352 default:
353 err = -EINVAL;
354 goto out;
355 }
356 switch (ch_ctrl->dwidth) {
357 case WIDTH_BYTE:
358 *ctrl &= ~(7 << 21);
359 break;
360 case WIDTH_HWORD:
361 *ctrl &= ~(7 << 21);
362 *ctrl |= (1 << 21);
363 break;
364 case WIDTH_WORD:
365 *ctrl &= ~(7 << 21);
366 *ctrl |= (2 << 21);
367 break;
368
369 default:
370 err = -EINVAL;
371 goto out;
372 }
373 switch (ch_ctrl->swidth) {
374 case WIDTH_BYTE:
375 *ctrl &= ~(7 << 18);
376 break;
377 case WIDTH_HWORD:
378 *ctrl &= ~(7 << 18);
379 *ctrl |= (1 << 18);
380 break;
381 case WIDTH_WORD:
382 *ctrl &= ~(7 << 18);
383 *ctrl |= (2 << 18);
384 break;
385
386 default:
387 err = -EINVAL;
388 goto out;
389 }
390 dbsize = ch_ctrl->dbsize;
391 while (!(dbsize & 1)) {
392 i++;
393 dbsize >>= 1;
394 }
395 if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
396 err = -EINVAL;
397 goto out;
398 } else if (i > 1)
399 i--;
400 *ctrl &= ~(7 << 15);
401 *ctrl |= (i << 15);
402
403 sbsize = ch_ctrl->sbsize;
404 while (!(sbsize & 1)) {
405 i++;
406 sbsize >>= 1;
407 }
408 if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
409 err = -EINVAL;
410 goto out;
411 } else if (i > 1)
412 i--;
413 *ctrl &= ~(7 << 12);
414 *ctrl |= (i << 12);
415
416 if (ch_ctrl->tr_size > 0x7ff) {
417 err = -E2BIG;
418 goto out;
419 }
420 *ctrl &= ~0x7ff;
421 *ctrl |= ch_ctrl->tr_size & 0x7ff;
422
423out:
424 return err;
425}
426
427EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
428
429int pnx4008_dma_parse_control(unsigned long ctrl,
430 struct pnx4008_dma_ch_ctrl * ch_ctrl)
431{
432 int err = 0;
433
434 if (!ch_ctrl) {
435 err = -EINVAL;
436 goto out;
437 }
438
439 ch_ctrl->tr_size = ctrl & 0x7ff;
440 ctrl >>= 12;
441
442 ch_ctrl->sbsize = 1 << (ctrl & 7);
443 if (ch_ctrl->sbsize > 1)
444 ch_ctrl->sbsize <<= 1;
445 ctrl >>= 3;
446
447 ch_ctrl->dbsize = 1 << (ctrl & 7);
448 if (ch_ctrl->dbsize > 1)
449 ch_ctrl->dbsize <<= 1;
450 ctrl >>= 3;
451
452 switch (ctrl & 7) {
453 case 0:
454 ch_ctrl->swidth = WIDTH_BYTE;
455 break;
456 case 1:
457 ch_ctrl->swidth = WIDTH_HWORD;
458 break;
459 case 2:
460 ch_ctrl->swidth = WIDTH_WORD;
461 break;
462 default:
463 err = -EINVAL;
464 goto out;
465 }
466 ctrl >>= 3;
467
468 switch (ctrl & 7) {
469 case 0:
470 ch_ctrl->dwidth = WIDTH_BYTE;
471 break;
472 case 1:
473 ch_ctrl->dwidth = WIDTH_HWORD;
474 break;
475 case 2:
476 ch_ctrl->dwidth = WIDTH_WORD;
477 break;
478 default:
479 err = -EINVAL;
480 goto out;
481 }
482 ctrl >>= 3;
483
484 ch_ctrl->src_ahb1 = ctrl & 1;
485 ctrl >>= 1;
486
487 ch_ctrl->dest_ahb1 = ctrl & 1;
488 ctrl >>= 1;
489
490 ch_ctrl->si = ctrl & 1;
491 ctrl >>= 1;
492
493 ch_ctrl->di = ctrl & 1;
494 ctrl >>= 1;
495
496 ch_ctrl->priv_mode = ctrl & 1;
497 ctrl >>= 1;
498
499 ch_ctrl->bufferable = ctrl & 1;
500 ctrl >>= 1;
501
502 ch_ctrl->cacheable = ctrl & 1;
503 ctrl >>= 1;
504
505 ch_ctrl->tc_mask = ctrl & 1;
506
507out:
508 return err;
509}
510
511EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
512
513int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
514 unsigned long *cfg)
515{
516 int err = 0;
517
518 if (!cfg || !ch_cfg) {
519 err = -EINVAL;
520 goto out;
521 }
522
523 *cfg = 0;
524
525 switch (ch_cfg->halt) {
526 case 0:
527 break;
528 case 1:
529 *cfg |= (1 << 18);
530 break;
531
532 default:
533 err = -EINVAL;
534 goto out;
535 }
536 switch (ch_cfg->active) {
537 case 0:
538 break;
539 case 1:
540 *cfg |= (1 << 17);
541 break;
542
543 default:
544 err = -EINVAL;
545 goto out;
546 }
547 switch (ch_cfg->lock) {
548 case 0:
549 break;
550 case 1:
551 *cfg |= (1 << 16);
552 break;
553
554 default:
555 err = -EINVAL;
556 goto out;
557 }
558 switch (ch_cfg->itc) {
559 case 0:
560 break;
561 case 1:
562 *cfg |= (1 << 15);
563 break;
564
565 default:
566 err = -EINVAL;
567 goto out;
568 }
569 switch (ch_cfg->ie) {
570 case 0:
571 break;
572 case 1:
573 *cfg |= (1 << 14);
574 break;
575
576 default:
577 err = -EINVAL;
578 goto out;
579 }
580 switch (ch_cfg->flow_cntrl) {
581 case FC_MEM2MEM_DMA:
582 *cfg &= ~(7 << 11);
583 break;
584 case FC_MEM2PER_DMA:
585 *cfg &= ~(7 << 11);
586 *cfg |= (1 << 11);
587 break;
588 case FC_PER2MEM_DMA:
589 *cfg &= ~(7 << 11);
590 *cfg |= (2 << 11);
591 break;
592 case FC_PER2PER_DMA:
593 *cfg &= ~(7 << 11);
594 *cfg |= (3 << 11);
595 break;
596 case FC_PER2PER_DPER:
597 *cfg &= ~(7 << 11);
598 *cfg |= (4 << 11);
599 break;
600 case FC_MEM2PER_PER:
601 *cfg &= ~(7 << 11);
602 *cfg |= (5 << 11);
603 break;
604 case FC_PER2MEM_PER:
605 *cfg &= ~(7 << 11);
606 *cfg |= (6 << 11);
607 break;
608 case FC_PER2PER_SPER:
609 *cfg |= (7 << 11);
610 break;
611
612 default:
613 err = -EINVAL;
614 goto out;
615 }
616 *cfg &= ~(0x1f << 6);
617 *cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
618
619 *cfg &= ~(0x1f << 1);
620 *cfg |= ((ch_cfg->src_per & 0x1f) << 1);
621
622out:
623 return err;
624}
625
626EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
627
628int pnx4008_dma_parse_config(unsigned long cfg,
629 struct pnx4008_dma_ch_config * ch_cfg)
630{
631 int err = 0;
632
633 if (!ch_cfg) {
634 err = -EINVAL;
635 goto out;
636 }
637
638 cfg >>= 1;
639
640 ch_cfg->src_per = cfg & 0x1f;
641 cfg >>= 5;
642
643 ch_cfg->dest_per = cfg & 0x1f;
644 cfg >>= 5;
645
646 switch (cfg & 7) {
647 case 0:
648 ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
649 break;
650 case 1:
651 ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
652 break;
653 case 2:
654 ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
655 break;
656 case 3:
657 ch_cfg->flow_cntrl = FC_PER2PER_DMA;
658 break;
659 case 4:
660 ch_cfg->flow_cntrl = FC_PER2PER_DPER;
661 break;
662 case 5:
663 ch_cfg->flow_cntrl = FC_MEM2PER_PER;
664 break;
665 case 6:
666 ch_cfg->flow_cntrl = FC_PER2MEM_PER;
667 break;
668 case 7:
669 ch_cfg->flow_cntrl = FC_PER2PER_SPER;
670 }
671 cfg >>= 3;
672
673 ch_cfg->ie = cfg & 1;
674 cfg >>= 1;
675
676 ch_cfg->itc = cfg & 1;
677 cfg >>= 1;
678
679 ch_cfg->lock = cfg & 1;
680 cfg >>= 1;
681
682 ch_cfg->active = cfg & 1;
683 cfg >>= 1;
684
685 ch_cfg->halt = cfg & 1;
686
687out:
688 return err;
689}
690
691EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
692
693void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
694 struct pnx4008_dma_ch_ctrl * ctrl)
695{
696 int new_len = ctrl->tr_size, num_entries = 0;
697 int old_len = new_len;
698 int src_width, dest_width, count = 1;
699
700 switch (ctrl->swidth) {
701 case WIDTH_BYTE:
702 src_width = 1;
703 break;
704 case WIDTH_HWORD:
705 src_width = 2;
706 break;
707 case WIDTH_WORD:
708 src_width = 4;
709 break;
710 default:
711 return;
712 }
713
714 switch (ctrl->dwidth) {
715 case WIDTH_BYTE:
716 dest_width = 1;
717 break;
718 case WIDTH_HWORD:
719 dest_width = 2;
720 break;
721 case WIDTH_WORD:
722 dest_width = 4;
723 break;
724 default:
725 return;
726 }
727
728 while (new_len > 0x7FF) {
729 num_entries++;
730 new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
731 }
732 if (num_entries != 0) {
733 struct pnx4008_dma_ll *ll = NULL;
734 config->ch_ctrl &= ~0x7ff;
735 config->ch_ctrl |= new_len;
736 if (!config->is_ll) {
737 config->is_ll = 1;
738 while (num_entries) {
739 if (!ll) {
740 config->ll =
741 pnx4008_alloc_ll_entry(&config->
742 ll_dma);
743 ll = config->ll;
744 } else {
745 ll->next =
746 pnx4008_alloc_ll_entry(&ll->
747 next_dma);
748 ll = ll->next;
749 }
750
751 if (ctrl->si)
752 ll->src_addr =
753 config->src_addr +
754 src_width * new_len * count;
755 else
756 ll->src_addr = config->src_addr;
757 if (ctrl->di)
758 ll->dest_addr =
759 config->dest_addr +
760 dest_width * new_len * count;
761 else
762 ll->dest_addr = config->dest_addr;
763 ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
764 ll->next_dma = 0;
765 ll->next = NULL;
766 num_entries--;
767 count++;
768 }
769 } else {
770 struct pnx4008_dma_ll *ll_old = config->ll;
771 unsigned long ll_dma_old = config->ll_dma;
772 while (num_entries) {
773 if (!ll) {
774 config->ll =
775 pnx4008_alloc_ll_entry(&config->
776 ll_dma);
777 ll = config->ll;
778 } else {
779 ll->next =
780 pnx4008_alloc_ll_entry(&ll->
781 next_dma);
782 ll = ll->next;
783 }
784
785 if (ctrl->si)
786 ll->src_addr =
787 config->src_addr +
788 src_width * new_len * count;
789 else
790 ll->src_addr = config->src_addr;
791 if (ctrl->di)
792 ll->dest_addr =
793 config->dest_addr +
794 dest_width * new_len * count;
795 else
796 ll->dest_addr = config->dest_addr;
797 ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
798 ll->next_dma = 0;
799 ll->next = NULL;
800 num_entries--;
801 count++;
802 }
803 ll->next_dma = ll_dma_old;
804 ll->next = ll_old;
805 }
806 /* adjust last length/tc */
807 ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
808 ll->ch_ctrl |= old_len - new_len * (count - 1);
809 config->ch_ctrl &= 0x7fffffff;
810 }
811}
812
813EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
814
815void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
816 struct pnx4008_dma_ch_ctrl * ctrl)
817{
818 int new_len = ctrl->tr_size, num_entries = 0;
819 int old_len = new_len;
820 int src_width, dest_width, count = 1;
821
822 switch (ctrl->swidth) {
823 case WIDTH_BYTE:
824 src_width = 1;
825 break;
826 case WIDTH_HWORD:
827 src_width = 2;
828 break;
829 case WIDTH_WORD:
830 src_width = 4;
831 break;
832 default:
833 return;
834 }
835
836 switch (ctrl->dwidth) {
837 case WIDTH_BYTE:
838 dest_width = 1;
839 break;
840 case WIDTH_HWORD:
841 dest_width = 2;
842 break;
843 case WIDTH_WORD:
844 dest_width = 4;
845 break;
846 default:
847 return;
848 }
849
850 while (new_len > 0x7FF) {
851 num_entries++;
852 new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
853 }
854 if (num_entries != 0) {
855 struct pnx4008_dma_ll *ll = NULL;
856 cur_ll->ch_ctrl &= ~0x7ff;
857 cur_ll->ch_ctrl |= new_len;
858 if (!cur_ll->next) {
859 while (num_entries) {
860 if (!ll) {
861 cur_ll->next =
862 pnx4008_alloc_ll_entry(&cur_ll->
863 next_dma);
864 ll = cur_ll->next;
865 } else {
866 ll->next =
867 pnx4008_alloc_ll_entry(&ll->
868 next_dma);
869 ll = ll->next;
870 }
871
872 if (ctrl->si)
873 ll->src_addr =
874 cur_ll->src_addr +
875 src_width * new_len * count;
876 else
877 ll->src_addr = cur_ll->src_addr;
878 if (ctrl->di)
879 ll->dest_addr =
880 cur_ll->dest_addr +
881 dest_width * new_len * count;
882 else
883 ll->dest_addr = cur_ll->dest_addr;
884 ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
885 ll->next_dma = 0;
886 ll->next = NULL;
887 num_entries--;
888 count++;
889 }
890 } else {
891 struct pnx4008_dma_ll *ll_old = cur_ll->next;
892 unsigned long ll_dma_old = cur_ll->next_dma;
893 while (num_entries) {
894 if (!ll) {
895 cur_ll->next =
896 pnx4008_alloc_ll_entry(&cur_ll->
897 next_dma);
898 ll = cur_ll->next;
899 } else {
900 ll->next =
901 pnx4008_alloc_ll_entry(&ll->
902 next_dma);
903 ll = ll->next;
904 }
905
906 if (ctrl->si)
907 ll->src_addr =
908 cur_ll->src_addr +
909 src_width * new_len * count;
910 else
911 ll->src_addr = cur_ll->src_addr;
912 if (ctrl->di)
913 ll->dest_addr =
914 cur_ll->dest_addr +
915 dest_width * new_len * count;
916 else
917 ll->dest_addr = cur_ll->dest_addr;
918 ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
919 ll->next_dma = 0;
920 ll->next = NULL;
921 num_entries--;
922 count++;
923 }
924
925 ll->next_dma = ll_dma_old;
926 ll->next = ll_old;
927 }
928 /* adjust last length/tc */
929 ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
930 ll->ch_ctrl |= old_len - new_len * (count - 1);
931 cur_ll->ch_ctrl &= 0x7fffffff;
932 }
933}
934
935EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
936
937int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
938{
939 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
940 return -EINVAL;
941
942 pnx4008_dma_lock();
943 __raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
944 __raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
945
946 if (config->is_ll)
947 __raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
948 else
949 __raw_writel(0, DMAC_Cx_LLI(ch));
950
951 __raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
952 __raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
953 pnx4008_dma_unlock();
954
955 return 0;
956
957}
958
959EXPORT_SYMBOL_GPL(pnx4008_config_channel);
960
961int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
962{
963 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
964 return -EINVAL;
965
966 pnx4008_dma_lock();
967 config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
968 config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
969
970 config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
971 config->is_ll = config->ll_dma ? 1 : 0;
972
973 config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
974 config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
975 pnx4008_dma_unlock();
976
977 return 0;
978}
979
980EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
981
982int pnx4008_dma_ch_enable(int ch)
983{
984 unsigned long ch_cfg;
985
986 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
987 return -EINVAL;
988
989 pnx4008_dma_lock();
990 ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
991 ch_cfg |= 1;
992 __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
993 pnx4008_dma_unlock();
994
995 return 0;
996}
997
998EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
999
1000int pnx4008_dma_ch_disable(int ch)
1001{
1002 unsigned long ch_cfg;
1003
1004 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
1005 return -EINVAL;
1006
1007 pnx4008_dma_lock();
1008 ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
1009 ch_cfg &= ~1;
1010 __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
1011 pnx4008_dma_unlock();
1012
1013 return 0;
1014}
1015
1016EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
1017
1018int pnx4008_dma_ch_enabled(int ch)
1019{
1020 unsigned long ch_cfg;
1021
1022 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
1023 return -EINVAL;
1024
1025 pnx4008_dma_lock();
1026 ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
1027 pnx4008_dma_unlock();
1028
1029 return ch_cfg & 1;
1030}
1031
1032EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
1033
1034static irqreturn_t dma_irq_handler(int irq, void *dev_id)
1035{
1036 int i;
1037 unsigned long dint = __raw_readl(DMAC_INT_STAT);
1038 unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
1039 unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
1040 unsigned long i_bit;
1041
1042 for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
1043 i_bit = 1 << i;
1044 if (dint & i_bit) {
1045 struct dma_channel *channel = &dma_channels[i];
1046
1047 if (channel->name && channel->irq_handler) {
1048 int cause = 0;
1049
1050 if (eint & i_bit)
1051 cause |= DMA_ERR_INT;
1052 if (tcint & i_bit)
1053 cause |= DMA_TC_INT;
1054 channel->irq_handler(i, cause, channel->data);
1055 } else {
1056 /*
1057 * IRQ for an unregistered DMA channel
1058 */
1059 printk(KERN_WARNING
1060 "spurious IRQ for DMA channel %d\n", i);
1061 }
1062 if (tcint & i_bit)
1063 __raw_writel(i_bit, DMAC_INT_TC_CLEAR);
1064 if (eint & i_bit)
1065 __raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
1066 }
1067 }
1068 return IRQ_HANDLED;
1069}
1070
1071static int __init pnx4008_dma_init(void)
1072{
1073 int ret, i;
1074
1075 ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
1076 if (ret) {
1077 printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
1078 goto out;
1079 }
1080
1081 ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
1082 ll_pool.cur = ll_pool.vaddr =
1083 dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
1084 &ll_pool.dma_addr, GFP_KERNEL);
1085
1086 if (!ll_pool.vaddr) {
1087 ret = -ENOMEM;
1088 free_irq(DMA_INT, NULL);
1089 goto out;
1090 }
1091
1092 for (i = 0; i < ll_pool.count - 1; i++) {
1093 void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
1094 *addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
1095 }
1096 *(long *)(ll_pool.vaddr +
1097 (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
1098 (long)ll_pool.vaddr;
1099
1100 __raw_writel(1, DMAC_CONFIG);
1101
1102out:
1103 return ret;
1104}
1105arch_initcall(pnx4008_dma_init);
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
deleted file mode 100644
index d3e71d3847b4..000000000000
--- a/arch/arm/mach-pnx4008/gpio.c
+++ /dev/null
@@ -1,328 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/gpio.c
3 *
4 * PNX4008 GPIO driver
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
9 * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/io.h>
20#include <mach/hardware.h>
21#include <mach/platform.h>
22#include <mach/gpio-pnx4008.h>
23
24/* register definitions */
25#define PIO_VA_BASE IO_ADDRESS(PNX4008_PIO_BASE)
26
27#define PIO_INP_STATE (0x00U)
28#define PIO_OUTP_SET (0x04U)
29#define PIO_OUTP_CLR (0x08U)
30#define PIO_OUTP_STATE (0x0CU)
31#define PIO_DRV_SET (0x10U)
32#define PIO_DRV_CLR (0x14U)
33#define PIO_DRV_STATE (0x18U)
34#define PIO_SDINP_STATE (0x1CU)
35#define PIO_SDOUTP_SET (0x20U)
36#define PIO_SDOUTP_CLR (0x24U)
37#define PIO_MUX_SET (0x28U)
38#define PIO_MUX_CLR (0x2CU)
39#define PIO_MUX_STATE (0x30U)
40
41static inline void gpio_lock(void)
42{
43 local_irq_disable();
44}
45
46static inline void gpio_unlock(void)
47{
48 local_irq_enable();
49}
50
51/* Inline functions */
52static inline int gpio_read_bit(u32 reg, int gpio)
53{
54 u32 bit, val;
55 int ret = -EFAULT;
56
57 if (gpio < 0)
58 goto out;
59
60 bit = GPIO_BIT(gpio);
61 if (bit) {
62 val = __raw_readl(PIO_VA_BASE + reg);
63 ret = (val & bit) ? 1 : 0;
64 }
65out:
66 return ret;
67}
68
69static inline int gpio_set_bit(u32 reg, int gpio)
70{
71 u32 bit, val;
72 int ret = -EFAULT;
73
74 if (gpio < 0)
75 goto out;
76
77 bit = GPIO_BIT(gpio);
78 if (bit) {
79 val = __raw_readl(PIO_VA_BASE + reg);
80 val |= bit;
81 __raw_writel(val, PIO_VA_BASE + reg);
82 ret = 0;
83 }
84out:
85 return ret;
86}
87
88/* Very simple access control, bitmap for allocated/free */
89static unsigned long access_map[4];
90#define INP_INDEX 0
91#define OUTP_INDEX 1
92#define GPIO_INDEX 2
93#define MUX_INDEX 3
94
95/*GPIO to Input Mapping */
96static short gpio_to_inp_map[32] = {
97 -1, -1, -1, -1, -1, -1, -1, -1,
98 -1, -1, -1, -1, -1, -1, -1, -1,
99 -1, -1, -1, -1, -1, -1, -1, -1,
100 -1, 10, 11, 12, 13, 14, 24, -1
101};
102
103/*GPIO to Mux Mapping */
104static short gpio_to_mux_map[32] = {
105 -1, -1, -1, -1, -1, -1, -1, -1,
106 -1, -1, -1, -1, -1, -1, -1, -1,
107 -1, -1, -1, -1, -1, -1, -1, -1,
108 -1, -1, -1, 0, 1, 4, 5, -1
109};
110
111/*Output to Mux Mapping */
112static short outp_to_mux_map[32] = {
113 -1, -1, -1, 6, -1, -1, -1, -1,
114 -1, -1, -1, -1, -1, -1, -1, -1,
115 -1, -1, -1, -1, -1, 2, -1, -1,
116 -1, -1, -1, -1, -1, -1, -1, -1
117};
118
119int pnx4008_gpio_register_pin(unsigned short pin)
120{
121 unsigned long bit = GPIO_BIT(pin);
122 int ret = -EBUSY; /* Already in use */
123
124 gpio_lock();
125
126 if (GPIO_ISBID(pin)) {
127 if (access_map[GPIO_INDEX] & bit)
128 goto out;
129 access_map[GPIO_INDEX] |= bit;
130
131 } else if (GPIO_ISRAM(pin)) {
132 if (access_map[GPIO_INDEX] & bit)
133 goto out;
134 access_map[GPIO_INDEX] |= bit;
135
136 } else if (GPIO_ISMUX(pin)) {
137 if (access_map[MUX_INDEX] & bit)
138 goto out;
139 access_map[MUX_INDEX] |= bit;
140
141 } else if (GPIO_ISOUT(pin)) {
142 if (access_map[OUTP_INDEX] & bit)
143 goto out;
144 access_map[OUTP_INDEX] |= bit;
145
146 } else if (GPIO_ISIN(pin)) {
147 if (access_map[INP_INDEX] & bit)
148 goto out;
149 access_map[INP_INDEX] |= bit;
150 } else
151 goto out;
152 ret = 0;
153
154out:
155 gpio_unlock();
156 return ret;
157}
158
159EXPORT_SYMBOL(pnx4008_gpio_register_pin);
160
161int pnx4008_gpio_unregister_pin(unsigned short pin)
162{
163 unsigned long bit = GPIO_BIT(pin);
164 int ret = -EFAULT; /* Not registered */
165
166 gpio_lock();
167
168 if (GPIO_ISBID(pin)) {
169 if (~access_map[GPIO_INDEX] & bit)
170 goto out;
171 access_map[GPIO_INDEX] &= ~bit;
172 } else if (GPIO_ISRAM(pin)) {
173 if (~access_map[GPIO_INDEX] & bit)
174 goto out;
175 access_map[GPIO_INDEX] &= ~bit;
176 } else if (GPIO_ISMUX(pin)) {
177 if (~access_map[MUX_INDEX] & bit)
178 goto out;
179 access_map[MUX_INDEX] &= ~bit;
180 } else if (GPIO_ISOUT(pin)) {
181 if (~access_map[OUTP_INDEX] & bit)
182 goto out;
183 access_map[OUTP_INDEX] &= ~bit;
184 } else if (GPIO_ISIN(pin)) {
185 if (~access_map[INP_INDEX] & bit)
186 goto out;
187 access_map[INP_INDEX] &= ~bit;
188 } else
189 goto out;
190 ret = 0;
191
192out:
193 gpio_unlock();
194 return ret;
195}
196
197EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
198
199unsigned long pnx4008_gpio_read_pin(unsigned short pin)
200{
201 unsigned long ret = -EFAULT;
202 int gpio = GPIO_BIT_MASK(pin);
203 gpio_lock();
204 if (GPIO_ISOUT(pin)) {
205 ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
206 } else if (GPIO_ISRAM(pin)) {
207 if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
208 ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
209 }
210 } else if (GPIO_ISBID(pin)) {
211 ret = gpio_read_bit(PIO_DRV_STATE, gpio);
212 if (ret > 0)
213 ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
214 else if (ret == 0)
215 ret =
216 gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
217 } else if (GPIO_ISIN(pin)) {
218 ret = gpio_read_bit(PIO_INP_STATE, gpio);
219 }
220 gpio_unlock();
221 return ret;
222}
223
224EXPORT_SYMBOL(pnx4008_gpio_read_pin);
225
226/* Write Value to output */
227int pnx4008_gpio_write_pin(unsigned short pin, int output)
228{
229 int gpio = GPIO_BIT_MASK(pin);
230 int ret = -EFAULT;
231
232 gpio_lock();
233 if (GPIO_ISOUT(pin)) {
234 printk( "writing '%x' to '%x'\n",
235 gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
236 ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
237 } else if (GPIO_ISRAM(pin)) {
238 if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
239 ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
240 PIO_SDOUTP_CLR, gpio);
241 } else if (GPIO_ISBID(pin)) {
242 if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
243 ret = gpio_set_bit(output ? PIO_OUTP_SET :
244 PIO_OUTP_CLR, gpio);
245 }
246 gpio_unlock();
247 return ret;
248}
249
250EXPORT_SYMBOL(pnx4008_gpio_write_pin);
251
252/* Value = 1 : Set GPIO pin as output */
253/* Value = 0 : Set GPIO pin as input */
254int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
255{
256 int gpio = GPIO_BIT_MASK(pin);
257 int ret = -EFAULT;
258
259 gpio_lock();
260 if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
261 ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
262 }
263 gpio_unlock();
264 return ret;
265}
266
267EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
268
269/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
270int pnx4008_gpio_read_pin_direction(unsigned short pin)
271{
272 int gpio = GPIO_BIT_MASK(pin);
273 int ret = -EFAULT;
274
275 gpio_lock();
276 if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
277 ret = gpio_read_bit(PIO_DRV_STATE, gpio);
278 }
279 gpio_unlock();
280 return ret;
281}
282
283EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
284
285/* Value = 1 : Set pin to muxed function */
286/* Value = 0 : Set pin as GPIO */
287int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
288{
289 int gpio = GPIO_BIT_MASK(pin);
290 int ret = -EFAULT;
291
292 gpio_lock();
293 if (GPIO_ISBID(pin)) {
294 ret =
295 gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
296 gpio_to_mux_map[gpio]);
297 } else if (GPIO_ISOUT(pin)) {
298 ret =
299 gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
300 outp_to_mux_map[gpio]);
301 } else if (GPIO_ISMUX(pin)) {
302 ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
303 }
304 gpio_unlock();
305 return ret;
306}
307
308EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
309
310/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
311int pnx4008_gpio_read_pin_mux(unsigned short pin)
312{
313 int gpio = GPIO_BIT_MASK(pin);
314 int ret = -EFAULT;
315
316 gpio_lock();
317 if (GPIO_ISBID(pin)) {
318 ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
319 } else if (GPIO_ISOUT(pin)) {
320 ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
321 } else if (GPIO_ISMUX(pin)) {
322 ret = gpio_read_bit(PIO_MUX_STATE, gpio);
323 }
324 gpio_unlock();
325 return ret;
326}
327
328EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
deleted file mode 100644
index 550cfc2a1f2e..000000000000
--- a/arch/arm/mach-pnx4008/i2c.c
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * I2C initialization for PNX4008.
3 *
4 * Author: Vitaly Wool <vitalywool@gmail.com>
5 *
6 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/i2c.h>
14#include <linux/i2c-pnx.h>
15#include <linux/platform_device.h>
16#include <linux/err.h>
17#include <mach/platform.h>
18#include <mach/irqs.h>
19
20static struct resource i2c0_resources[] = {
21 {
22 .start = PNX4008_I2C1_BASE,
23 .end = PNX4008_I2C1_BASE + SZ_4K - 1,
24 .flags = IORESOURCE_MEM,
25 }, {
26 .start = I2C_1_INT,
27 .end = I2C_1_INT,
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32static struct resource i2c1_resources[] = {
33 {
34 .start = PNX4008_I2C2_BASE,
35 .end = PNX4008_I2C2_BASE + SZ_4K - 1,
36 .flags = IORESOURCE_MEM,
37 }, {
38 .start = I2C_2_INT,
39 .end = I2C_2_INT,
40 .flags = IORESOURCE_IRQ,
41 },
42};
43
44static struct resource i2c2_resources[] = {
45 {
46 .start = PNX4008_USB_CONFIG_BASE + 0x300,
47 .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
48 .flags = IORESOURCE_MEM,
49 }, {
50 .start = USB_I2C_INT,
51 .end = USB_I2C_INT,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
56static struct platform_device i2c0_device = {
57 .name = "pnx-i2c.0",
58 .id = 0,
59 .resource = i2c0_resources,
60 .num_resources = ARRAY_SIZE(i2c0_resources),
61};
62
63static struct platform_device i2c1_device = {
64 .name = "pnx-i2c.1",
65 .id = 1,
66 .resource = i2c1_resources,
67 .num_resources = ARRAY_SIZE(i2c1_resources),
68};
69
70static struct platform_device i2c2_device = {
71 .name = "pnx-i2c.2",
72 .id = 2,
73 .resource = i2c2_resources,
74 .num_resources = ARRAY_SIZE(i2c2_resources),
75};
76
77static struct platform_device *devices[] __initdata = {
78 &i2c0_device,
79 &i2c1_device,
80 &i2c2_device,
81};
82
83void __init pnx4008_register_i2c_devices(void)
84{
85 platform_add_devices(devices, ARRAY_SIZE(devices));
86}
diff --git a/arch/arm/mach-pnx4008/include/mach/clock.h b/arch/arm/mach-pnx4008/include/mach/clock.h
deleted file mode 100644
index 8d2a5ef52c90..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/clock.h
3 *
4 * Clock control driver for PNX4008 - header file
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __PNX4008_CLOCK_H__
14#define __PNX4008_CLOCK_H__
15
16struct module;
17struct clk;
18
19#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
20#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40)
21#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44)
22#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48)
23#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c)
24#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50)
25#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58)
26#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64)
27#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68)
28#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80)
29#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84)
30#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90)
31#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac)
32#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0)
33#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4)
34#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8)
35#define TIMCLKCTRL_REG (PWRMAN_VA_BASE + 0xbc)
36#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4)
37#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8)
38#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0)
39#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4)
40#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8)
41#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec)
42#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc)
43
44#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
45#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60)
46#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64)
47#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68)
48#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C)
49
50#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
51
52#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
53
54#define CLK_RATE_13MHZ 13000
55#define CLK_RATE_1MHZ 1000
56#define CLK_RATE_208MHZ 208000
57#define CLK_RATE_48MHZ 48000
58#define CLK_RATE_32KHZ 32
59
60#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
61
62#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
deleted file mode 100644
index 469d60d97f5c..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
1/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00090000
16 add \rv, \rp, #0xf4000000 @ virtual
17 add \rp, \rp, #0x40000000 @ physical
18 .endm
19
20#define UART_SHIFT 2
21#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h
deleted file mode 100644
index f094bf8bfb18..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/dma.h
+++ /dev/null
@@ -1,160 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/dma.h
3 *
4 * PNX4008 DMA header file
5 *
6 * Author: Vitaly Wool
7 * Copyright: MontaVista Software Inc. (c) 2005
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_DMA_H
15#define __ASM_ARCH_DMA_H
16
17#include "platform.h"
18
19#define MAX_DMA_CHANNELS 8
20
21#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
22#define DMAC_INT_STAT (DMAC_BASE + 0x0000)
23#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004)
24#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008)
25#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c)
26#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010)
27#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024)
28#define DMAC_CONFIG (DMAC_BASE + 0x0030)
29#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20)
30#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20)
31#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20)
32#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20)
33#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20)
34
35enum {
36 WIDTH_BYTE = 0,
37 WIDTH_HWORD,
38 WIDTH_WORD
39};
40
41enum {
42 FC_MEM2MEM_DMA,
43 FC_MEM2PER_DMA,
44 FC_PER2MEM_DMA,
45 FC_PER2PER_DMA,
46 FC_PER2PER_DPER,
47 FC_MEM2PER_PER,
48 FC_PER2MEM_PER,
49 FC_PER2PER_SPER
50};
51
52enum {
53 DMA_INT_UNKNOWN = 0,
54 DMA_ERR_INT = 1,
55 DMA_TC_INT = 2,
56};
57
58enum {
59 DMA_BUFFER_ALLOCATED = 1,
60 DMA_HAS_LL = 2,
61};
62
63enum {
64 PER_CAM_DMA_1 = 0,
65 PER_NDF_FLASH = 1,
66 PER_MBX_SLAVE_FIFO = 2,
67 PER_SPI2_REC_XMIT = 3,
68 PER_MS_SD_RX_XMIT = 4,
69 PER_HS_UART_1_XMIT = 5,
70 PER_HS_UART_1_RX = 6,
71 PER_HS_UART_2_XMIT = 7,
72 PER_HS_UART_2_RX = 8,
73 PER_HS_UART_7_XMIT = 9,
74 PER_HS_UART_7_RX = 10,
75 PER_SPI1_REC_XMIT = 11,
76 PER_MLC_NDF_SREC = 12,
77 PER_CAM_DMA_2 = 13,
78 PER_PRNG_INFIFO = 14,
79 PER_PRNG_OUTFIFO = 15,
80};
81
82struct pnx4008_dma_ch_ctrl {
83 int tc_mask;
84 int cacheable;
85 int bufferable;
86 int priv_mode;
87 int di;
88 int si;
89 int dest_ahb1;
90 int src_ahb1;
91 int dwidth;
92 int swidth;
93 int dbsize;
94 int sbsize;
95 int tr_size;
96};
97
98struct pnx4008_dma_ch_config {
99 int halt;
100 int active;
101 int lock;
102 int itc;
103 int ie;
104 int flow_cntrl;
105 int dest_per;
106 int src_per;
107};
108
109struct pnx4008_dma_ll {
110 unsigned long src_addr;
111 unsigned long dest_addr;
112 u32 next_dma;
113 unsigned long ch_ctrl;
114 struct pnx4008_dma_ll *next;
115 int flags;
116 void *alloc_data;
117 int (*free) (void *);
118};
119
120struct pnx4008_dma_config {
121 int is_ll;
122 unsigned long src_addr;
123 unsigned long dest_addr;
124 unsigned long ch_ctrl;
125 unsigned long ch_cfg;
126 struct pnx4008_dma_ll *ll;
127 u32 ll_dma;
128 int flags;
129 void *alloc_data;
130 int (*free) (void *);
131};
132
133extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
134extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
135extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
136
137extern int pnx4008_request_channel(char *, int,
138 void (*)(int, int, void *),
139 void *);
140extern void pnx4008_free_channel(int);
141extern int pnx4008_config_dma(int, int, int);
142extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
143 unsigned long *);
144extern int pnx4008_dma_parse_control(unsigned long,
145 struct pnx4008_dma_ch_ctrl *);
146extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
147 unsigned long *);
148extern int pnx4008_dma_parse_config(unsigned long,
149 struct pnx4008_dma_ch_config *);
150extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
151extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
152extern int pnx4008_dma_ch_enable(int);
153extern int pnx4008_dma_ch_disable(int);
154extern int pnx4008_dma_ch_enabled(int);
155extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
156 struct pnx4008_dma_ch_ctrl *);
157extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
158 struct pnx4008_dma_ch_ctrl *);
159
160#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
deleted file mode 100644
index 77a555846719..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for PNX4008-based platforms
5 *
6 * 2005-2006 (c) MontaVista Software, Inc.
7 * Author: Vitaly Wool <vwool@ru.mvista.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include "platform.h"
14
15#define IO_BASE 0xF0000000
16#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
17
18#define INTRC_MASK 0x00
19#define INTRC_RAW_STAT 0x04
20#define INTRC_STAT 0x08
21#define INTRC_POLAR 0x0C
22#define INTRC_ACT_TYPE 0x10
23#define INTRC_TYPE 0x14
24
25#define SIC1_BASE_INT 32
26#define SIC2_BASE_INT 64
27
28 .macro get_irqnr_preamble, base, tmp
29 .endm
30
31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
32/* decode the MIC interrupt numbers */
33 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
34 ldr \irqstat, [\base, #INTRC_STAT]
35
36 cmp \irqstat,#1<<16
37 movhs \irqnr,#16
38 movlo \irqnr,#0
39 movhs \irqstat,\irqstat,lsr#16
40 cmp \irqstat,#1<<8
41 addhs \irqnr,\irqnr,#8
42 movhs \irqstat,\irqstat,lsr#8
43 cmp \irqstat,#1<<4
44 addhs \irqnr,\irqnr,#4
45 movhs \irqstat,\irqstat,lsr#4
46 cmp \irqstat,#1<<2
47 addhs \irqnr,\irqnr,#2
48 movhs \irqstat,\irqstat,lsr#2
49 cmp \irqstat,#1<<1
50 addhs \irqnr,\irqnr,#1
51
52/* was there an interrupt ? if not then drop out with EQ status */
53 teq \irqstat,#0
54 beq 1003f
55
56/* and now check for extended IRQ reasons */
57 cmp \irqnr,#1
58 bls 1003f
59 cmp \irqnr,#30
60 blo 1002f
61
62/* IRQ 31,30 : High priority cascade IRQ handle */
63/* read the correct SIC */
64/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
65/* set the base IRQ number */
66 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
67 moveq \irqnr,#SIC1_BASE_INT
68 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
69 movne \irqnr,#SIC2_BASE_INT
70 ldr \irqstat, [\base, #INTRC_STAT]
71 ldr \tmp, [\base, #INTRC_TYPE]
72/* and with inverted mask : low priority interrupts */
73 and \irqstat,\irqstat,\tmp
74 b 1004f
75
761003:
77/* IRQ 1,0 : Low priority cascade IRQ handle */
78/* read the correct SIC */
79/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
80/* read the correct SIC */
81/* set the base IRQ number */
82 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
83 movne \irqnr,#SIC1_BASE_INT
84 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
85 moveq \irqnr,#SIC2_BASE_INT
86 ldr \irqstat, [\base, #INTRC_STAT]
87 ldr \tmp, [\base, #INTRC_TYPE]
88/* and with inverted mask : low priority interrupts */
89 bic \irqstat,\irqstat,\tmp
90
911004:
92
93 cmp \irqstat,#1<<16
94 addhs \irqnr,\irqnr,#16
95 movhs \irqstat,\irqstat,lsr#16
96 cmp \irqstat,#1<<8
97 addhs \irqnr,\irqnr,#8
98 movhs \irqstat,\irqstat,lsr#8
99 cmp \irqstat,#1<<4
100 addhs \irqnr,\irqnr,#4
101 movhs \irqstat,\irqstat,lsr#4
102 cmp \irqstat,#1<<2
103 addhs \irqnr,\irqnr,#2
104 movhs \irqstat,\irqstat,lsr#2
105 cmp \irqstat,#1<<1
106 addhs \irqnr,\irqnr,#1
107
108
109/* is irqstat not zero */
110
1111002:
112/* we assert that irqstat is not equal to zero and return ne status if true*/
113 teq \irqstat,#0
1141003:
115 .endm
116
diff --git a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h b/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
deleted file mode 100644
index 41027dd7cf74..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
+++ /dev/null
@@ -1,241 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
3 *
4 * PNX4008 GPIO driver - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
9 * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#ifndef _PNX4008_GPIO_H_
18#define _PNX4008_GPIO_H_
19
20
21/* Block numbers */
22#define GPIO_IN (0)
23#define GPIO_OUT (0x100)
24#define GPIO_BID (0x200)
25#define GPIO_RAM (0x300)
26#define GPIO_MUX (0x400)
27
28#define GPIO_TYPE_MASK(K) ((K) & 0x700)
29
30/* INPUT GPIOs */
31/* GPI */
32#define GPI_00 (GPIO_IN | 0)
33#define GPI_01 (GPIO_IN | 1)
34#define GPI_02 (GPIO_IN | 2)
35#define GPI_03 (GPIO_IN | 3)
36#define GPI_04 (GPIO_IN | 4)
37#define GPI_05 (GPIO_IN | 5)
38#define GPI_06 (GPIO_IN | 6)
39#define GPI_07 (GPIO_IN | 7)
40#define GPI_08 (GPIO_IN | 8)
41#define GPI_09 (GPIO_IN | 9)
42#define U1_RX (GPIO_IN | 15)
43#define U2_HTCS (GPIO_IN | 16)
44#define U2_RX (GPIO_IN | 17)
45#define U3_RX (GPIO_IN | 18)
46#define U4_RX (GPIO_IN | 19)
47#define U5_RX (GPIO_IN | 20)
48#define U6_IRRX (GPIO_IN | 21)
49#define U7_HCTS (GPIO_IN | 22)
50#define U7_RX (GPIO_IN | 23)
51/* MISC IN */
52#define SPI1_DATIN (GPIO_IN | 25)
53#define DISP_SYNC (GPIO_IN | 26)
54#define SPI2_DATIN (GPIO_IN | 27)
55#define GPI_11 (GPIO_IN | 28)
56
57#define GPIO_IN_MASK 0x1eff83ff
58
59/* OUTPUT GPIOs */
60/* GPO */
61#define GPO_00 (GPIO_OUT | 0)
62#define GPO_01 (GPIO_OUT | 1)
63#define GPO_02 (GPIO_OUT | 2)
64#define GPO_03 (GPIO_OUT | 3)
65#define GPO_04 (GPIO_OUT | 4)
66#define GPO_05 (GPIO_OUT | 5)
67#define GPO_06 (GPIO_OUT | 6)
68#define GPO_07 (GPIO_OUT | 7)
69#define GPO_08 (GPIO_OUT | 8)
70#define GPO_09 (GPIO_OUT | 9)
71#define GPO_10 (GPIO_OUT | 10)
72#define GPO_11 (GPIO_OUT | 11)
73#define GPO_12 (GPIO_OUT | 12)
74#define GPO_13 (GPIO_OUT | 13)
75#define GPO_14 (GPIO_OUT | 14)
76#define GPO_15 (GPIO_OUT | 15)
77#define GPO_16 (GPIO_OUT | 16)
78#define GPO_17 (GPIO_OUT | 17)
79#define GPO_18 (GPIO_OUT | 18)
80#define GPO_19 (GPIO_OUT | 19)
81#define GPO_20 (GPIO_OUT | 20)
82#define GPO_21 (GPIO_OUT | 21)
83#define GPO_22 (GPIO_OUT | 22)
84#define GPO_23 (GPIO_OUT | 23)
85
86#define GPIO_OUT_MASK 0xffffff
87
88/* BIDIRECTIONAL GPIOs */
89/* RAM pins */
90#define RAM_D19 (GPIO_RAM | 0)
91#define RAM_D20 (GPIO_RAM | 1)
92#define RAM_D21 (GPIO_RAM | 2)
93#define RAM_D22 (GPIO_RAM | 3)
94#define RAM_D23 (GPIO_RAM | 4)
95#define RAM_D24 (GPIO_RAM | 5)
96#define RAM_D25 (GPIO_RAM | 6)
97#define RAM_D26 (GPIO_RAM | 7)
98#define RAM_D27 (GPIO_RAM | 8)
99#define RAM_D28 (GPIO_RAM | 9)
100#define RAM_D29 (GPIO_RAM | 10)
101#define RAM_D30 (GPIO_RAM | 11)
102#define RAM_D31 (GPIO_RAM | 12)
103
104#define GPIO_RAM_MASK 0x1fff
105
106/* I/O pins */
107#define GPIO_00 (GPIO_BID | 25)
108#define GPIO_01 (GPIO_BID | 26)
109#define GPIO_02 (GPIO_BID | 27)
110#define GPIO_03 (GPIO_BID | 28)
111#define GPIO_04 (GPIO_BID | 29)
112#define GPIO_05 (GPIO_BID | 30)
113
114#define GPIO_BID_MASK 0x7e000000
115
116/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
117#define GPIO_SDRAM_SEL (GPIO_MUX | 3)
118
119#define GPIO_MUX_MASK 0x8
120
121/* Extraction/assembly macros */
122#define GPIO_BIT_MASK(K) ((K) & 0x1F)
123#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
124#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
125#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
126#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
127#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
128#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
129
130/* Start Enable Pin Interrupts - table 58 page 66 */
131
132#define SE_PIN_BASE_INT 32
133
134#define SE_U7_RX_INT 63
135#define SE_U7_HCTS_INT 62
136#define SE_BT_CLKREQ_INT 61
137#define SE_U6_IRRX_INT 60
138/*59 unused*/
139#define SE_U5_RX_INT 58
140#define SE_GPI_11_INT 57
141#define SE_U3_RX_INT 56
142#define SE_U2_HCTS_INT 55
143#define SE_U2_RX_INT 54
144#define SE_U1_RX_INT 53
145#define SE_DISP_SYNC_INT 52
146/*51 unused*/
147#define SE_SDIO_INT_N 50
148#define SE_MSDIO_START_INT 49
149#define SE_GPI_06_INT 48
150#define SE_GPI_05_INT 47
151#define SE_GPI_04_INT 46
152#define SE_GPI_03_INT 45
153#define SE_GPI_02_INT 44
154#define SE_GPI_01_INT 43
155#define SE_GPI_00_INT 42
156#define SE_SYSCLKEN_PIN_INT 41
157#define SE_SPI1_DATAIN_INT 40
158#define SE_GPI_07_INT 39
159#define SE_SPI2_DATAIN_INT 38
160#define SE_GPI_10_INT 37
161#define SE_GPI_09_INT 36
162#define SE_GPI_08_INT 35
163/*34-32 unused*/
164
165/* Start Enable Internal Interrupts - table 57 page 65 */
166
167#define SE_INT_BASE_INT 0
168
169#define SE_TS_IRQ 31
170#define SE_TS_P_INT 30
171#define SE_TS_AUX_INT 29
172/*27-28 unused*/
173#define SE_USB_AHB_NEED_CLK_INT 26
174#define SE_MSTIMER_INT 25
175#define SE_RTC_INT 24
176#define SE_USB_NEED_CLK_INT 23
177#define SE_USB_INT 22
178#define SE_USB_I2C_INT 21
179#define SE_USB_OTG_TIMER_INT 20
180#define SE_USB_OTG_ATX_INT_N 19
181/*18 unused*/
182#define SE_DSP_GPIO4_INT 17
183#define SE_KEY_IRQ 16
184#define SE_DSP_SLAVEPORT_INT 15
185#define SE_DSP_GPIO1_INT 14
186#define SE_DSP_GPIO0_INT 13
187#define SE_DSP_AHB_INT 12
188/*11-6 unused*/
189#define SE_GPIO_05_INT 5
190#define SE_GPIO_04_INT 4
191#define SE_GPIO_03_INT 3
192#define SE_GPIO_02_INT 2
193#define SE_GPIO_01_INT 1
194#define SE_GPIO_00_INT 0
195
196#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
197
198#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
199#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
200#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
201#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
202
203extern int pnx4008_gpio_register_pin(unsigned short pin);
204extern int pnx4008_gpio_unregister_pin(unsigned short pin);
205extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
206extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
207extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
208extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
209extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
210extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
211
212static inline void start_int_umask(u8 irq)
213{
214 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
215 START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
216}
217
218static inline void start_int_mask(u8 irq)
219{
220 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
221 ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
222}
223
224static inline void start_int_ack(u8 irq)
225{
226 __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
227}
228
229static inline void start_int_set_falling_edge(u8 irq)
230{
231 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
232 ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
233}
234
235static inline void start_int_set_rising_edge(u8 irq)
236{
237 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
238 START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
239}
240
241#endif /* _PNX4008_GPIO_H_ */
diff --git a/arch/arm/mach-pnx4008/include/mach/hardware.h b/arch/arm/mach-pnx4008/include/mach/hardware.h
deleted file mode 100644
index 7b98b828d368..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/hardware.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_HARDWARE_H
21#define __ASM_ARCH_HARDWARE_H
22
23#include <asm/sizes.h>
24#include <mach/platform.h>
25
26/* Start of virtual addresses for IO devices */
27#define IO_BASE 0xF0000000
28
29/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
30#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
31
32#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/irq.h b/arch/arm/mach-pnx4008/include/mach/irq.h
deleted file mode 100644
index 2a690ca33870..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/irq.h
3 *
4 * PNX4008 IRQ controller driver - header file
5 * this one is used in entry-arnv.S as well so it cannot contain C code
6 *
7 * Copyright (c) 2005 Philips Semiconductors
8 * Copyright (c) 2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __PNX4008_IRQ_H__
16#define __PNX4008_IRQ_H__
17
18#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
19#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
20#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
21
22/* Manual: Chapter 20, page 195 */
23
24#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
25
26#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
27#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
28#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
29#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
30#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
31#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
32
33#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
34
35#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
36#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
37#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
38#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
39
40extern void __init pnx4008_init_irq(void);
41
42#endif /* __PNX4008_IRQ_H__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/irqs.h b/arch/arm/mach-pnx4008/include/mach/irqs.h
deleted file mode 100644
index f6b33cf23ae2..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/irqs.h
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/irqs.h
3 *
4 * PNX4008 IRQ controller driver - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __PNX4008_IRQS_h__
14#define __PNX4008_IRQS_h__
15
16#define NR_IRQS 96
17
18/*Manual: table 259, page 199*/
19
20/*SUB2 Interrupt Routing (SIC2)*/
21
22#define SIC2_BASE_INT 64
23
24#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */
25#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */
26#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */
27#define GPI_06_INT 92
28#define GPI_05_INT 91
29#define GPI_04_INT 90
30#define GPI_03_INT 89
31#define GPI_02_INT 88
32#define GPI_01_INT 87
33#define GPI_00_INT 86
34#define BT_CLKREQ_INT 85
35#define SPI1_DATIN_INT 84
36#define U5_RX_INT 83
37#define SDIO_INT_N 82
38#define CAM_HS_INT 81
39#define CAM_VS_INT 80
40#define GPI_07_INT 79
41#define DISP_SYNC_INT 78
42#define DSP_INT8 77
43#define U7_HCTS_INT 76
44#define GPI_10_INT 75
45#define GPI_09_INT 74
46#define GPI_08_INT 73
47#define DSP_INT7 72
48#define U2_HCTS_INT 71
49#define SPI2_DATIN_INT 70
50#define GPIO_05_INT 69
51#define GPIO_04_INT 68
52#define GPIO_03_INT 67
53#define GPIO_02_INT 66
54#define GPIO_01_INT 65
55#define GPIO_00_INT 64
56
57/*Manual: table 258, page 198*/
58
59/*SUB1 Interrupt Routing (SIC1)*/
60
61#define SIC1_BASE_INT 32
62
63#define USB_I2C_INT 63
64#define USB_DEV_HP_INT 62
65#define USB_DEV_LP_INT 61
66#define USB_DEV_DMA_INT 60
67#define USB_HOST_INT 59
68#define USB_OTG_ATX_INT_N 58
69#define USB_OTG_TIMER_INT 57
70#define SW_INT 56
71#define SPI1_INT 55
72#define KEY_IRQ 54
73#define DSP_M_INT 53
74#define RTC_INT 52
75#define I2C_1_INT 51
76#define I2C_2_INT 50
77#define PLL1_LOCK_INT 49
78#define PLL2_LOCK_INT 48
79#define PLL3_LOCK_INT 47
80#define PLL4_LOCK_INT 46
81#define PLL5_LOCK_INT 45
82#define SPI2_INT 44
83#define DSP_INT1 43
84#define DSP_INT2 42
85#define DSP_TDM_INT2 41
86#define TS_AUX_INT 40
87#define TS_IRQ 39
88#define TS_P_INT 38
89#define UOUT1_TO_PAD_INT 37
90#define GPI_11_INT 36
91#define DSP_INT4 35
92#define JTAG_COMM_RX_INT 34
93#define JTAG_COMM_TX_INT 33
94#define DSP_INT3 32
95
96/*Manual: table 257, page 197*/
97
98/*MAIN Interrupt Routing*/
99
100#define MAIN_BASE_INT 0
101
102#define SUB2_FIQ_N 31 /*active low */
103#define SUB1_FIQ_N 30 /*active low */
104#define JPEG_INT 29
105#define DMA_INT 28
106#define MSTIMER_INT 27
107#define IIR1_INT 26
108#define IIR2_INT 25
109#define IIR7_INT 24
110#define DSP_TDM_INT0 23
111#define DSP_TDM_INT1 22
112#define DSP_P_INT 21
113#define DSP_INT0 20
114#define DUM_INT 19
115#define UOUT0_TO_PAD_INT 18
116#define MP4_ENC_INT 17
117#define MP4_DEC_INT 16
118#define SD0_INT 15
119#define MBX_INT 14
120#define SD1_INT 13
121#define MS_INT_N 12
122#define FLASH_INT 11 /*NAND*/
123#define IIR6_INT 10
124#define IIR5_INT 9
125#define IIR4_INT 8
126#define IIR3_INT 7
127#define WATCH_INT 6
128#define HSTIMER_INT 5
129#define ARCH_TIMER_IRQ HSTIMER_INT
130#define CAM_INT 4
131#define PRNG_INT 3
132#define CRYPTO_INT 2
133#define SUB2_IRQ_N 1 /*active low */
134#define SUB1_IRQ_N 0 /*active low */
135
136#define PNX4008_IRQ_TYPES \
137{ /*IRQ #'s: */ \
138IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \
139IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \
140IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \
141IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \
142IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \
143IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \
144IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \
145IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \
146IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \
147IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \
148IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \
149IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \
150IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \
151IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \
152IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \
153IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \
154IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \
155IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \
156IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \
157IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \
158IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \
159IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \
160IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \
161IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \
162}
163
164/* Start Enable Pin Interrupts - table 58 page 66 */
165
166#define SE_PIN_BASE_INT 32
167
168#define SE_U7_RX_INT 63
169#define SE_U7_HCTS_INT 62
170#define SE_BT_CLKREQ_INT 61
171#define SE_U6_IRRX_INT 60
172/*59 unused*/
173#define SE_U5_RX_INT 58
174#define SE_GPI_11_INT 57
175#define SE_U3_RX_INT 56
176#define SE_U2_HCTS_INT 55
177#define SE_U2_RX_INT 54
178#define SE_U1_RX_INT 53
179#define SE_DISP_SYNC_INT 52
180/*51 unused*/
181#define SE_SDIO_INT_N 50
182#define SE_MSDIO_START_INT 49
183#define SE_GPI_06_INT 48
184#define SE_GPI_05_INT 47
185#define SE_GPI_04_INT 46
186#define SE_GPI_03_INT 45
187#define SE_GPI_02_INT 44
188#define SE_GPI_01_INT 43
189#define SE_GPI_00_INT 42
190#define SE_SYSCLKEN_PIN_INT 41
191#define SE_SPI1_DATAIN_INT 40
192#define SE_GPI_07_INT 39
193#define SE_SPI2_DATAIN_INT 38
194#define SE_GPI_10_INT 37
195#define SE_GPI_09_INT 36
196#define SE_GPI_08_INT 35
197/*34-32 unused*/
198
199/* Start Enable Internal Interrupts - table 57 page 65 */
200
201#define SE_INT_BASE_INT 0
202
203#define SE_TS_IRQ 31
204#define SE_TS_P_INT 30
205#define SE_TS_AUX_INT 29
206/*27-28 unused*/
207#define SE_USB_AHB_NEED_CLK_INT 26
208#define SE_MSTIMER_INT 25
209#define SE_RTC_INT 24
210#define SE_USB_NEED_CLK_INT 23
211#define SE_USB_INT 22
212#define SE_USB_I2C_INT 21
213#define SE_USB_OTG_TIMER_INT 20
214
215#endif /* __PNX4008_IRQS_h__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/param.h b/arch/arm/mach-pnx4008/include/mach/param.h
deleted file mode 100644
index 6ea02f2176b7..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/param.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/param.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#define HZ 100
diff --git a/arch/arm/mach-pnx4008/include/mach/platform.h b/arch/arm/mach-pnx4008/include/mach/platform.h
deleted file mode 100644
index 368c2c10a308..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/platform.h
3 *
4 * PNX4008 Base addresses - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code received from Philips:
9 * Copyright (C) 2003 Philips Semiconductors
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17
18#ifndef __ASM_ARCH_PLATFORM_H__
19#define __ASM_ARCH_PLATFORM_H__
20
21#define PNX4008_IRAM_BASE 0x08000000
22#define PNX4008_IRAM_SIZE 0x00010000
23#define PNX4008_YUV_SLAVE_BASE 0x10000000
24#define PNX4008_DUM_SLAVE_BASE 0x18000000
25#define PNX4008_NDF_FLASH_BASE 0x20020000
26#define PNX4008_SPI1_BASE 0x20088000
27#define PNX4008_SPI2_BASE 0x20090000
28#define PNX4008_SD_CONFIG_BASE 0x20098000
29#define PNX4008_FLASH_DATA 0x200B0000
30#define PNX4008_MLC_FLASH_BASE 0x200B8000
31#define PNX4008_JPEG_CONFIG_BASE 0x300A0000
32#define PNX4008_DMA_CONFIG_BASE 0x31000000
33#define PNX4008_USB_CONFIG_BASE 0x31020000
34#define PNX4008_SDRAM_CFG_BASE 0x31080000
35#define PNX4008_AHB2FAB_BASE 0x40000000
36#define PNX4008_PWRMAN_BASE 0x40004000
37#define PNX4008_INTCTRLMIC_BASE 0x40008000
38#define PNX4008_INTCTRLSIC1_BASE 0x4000C000
39#define PNX4008_INTCTRLSIC2_BASE 0x40010000
40#define PNX4008_HSUART1_BASE 0x40014000
41#define PNX4008_HSUART2_BASE 0x40018000
42#define PNX4008_HSUART7_BASE 0x4001C000
43#define PNX4008_RTC_BASE 0x40024000
44#define PNX4008_PIO_BASE 0x40028000
45#define PNX4008_MSTIMER_BASE 0x40034000
46#define PNX4008_HSTIMER_BASE 0x40038000
47#define PNX4008_WDOG_BASE 0x4003C000
48#define PNX4008_DEBUG_BASE 0x40040000
49#define PNX4008_TOUCH1_BASE 0x40048000
50#define PNX4008_KEYSCAN_BASE 0x40050000
51#define PNX4008_UARTCTRL_BASE 0x40054000
52#define PNX4008_PWM_BASE 0x4005C000
53#define PNX4008_UART3_BASE 0x40080000
54#define PNX4008_UART4_BASE 0x40088000
55#define PNX4008_UART5_BASE 0x40090000
56#define PNX4008_UART6_BASE 0x40098000
57#define PNX4008_I2C1_BASE 0x400A0000
58#define PNX4008_I2C2_BASE 0x400A8000
59#define PNX4008_MAGICGATE_BASE 0x400B0000
60#define PNX4008_DUMCONF_BASE 0x400B8000
61#define PNX4008_DUM_MAINCFG_BASE 0x400BC000
62#define PNX4008_DSP_BASE 0x400C0000
63#define PNX4008_PROFCOUNTER_BASE 0x400C8000
64#define PNX4008_CRYPTO_BASE 0x400D0000
65#define PNX4008_CAMIFCONF_BASE 0x400D8000
66#define PNX4008_YUV2RGB_BASE 0x400E0000
67#define PNX4008_AUDIOCONFIG_BASE 0x400E8000
68
69#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/pm.h b/arch/arm/mach-pnx4008/include/mach/pm.h
deleted file mode 100644
index 2fa685bff858..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/pm.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/pm.h
3 *
4 * PNX4008 Power Management Routiness - header file
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __ASM_ARCH_PNX4008_PM_H
15#define __ASM_ARCH_PNX4008_PM_H
16
17#ifndef __ASSEMBLER__
18#include "irq.h"
19#include "irqs.h"
20#include "clock.h"
21
22extern void pnx4008_pm_idle(void);
23extern void pnx4008_pm_suspend(void);
24extern unsigned int pnx4008_cpu_suspend_sz;
25extern void pnx4008_cpu_suspend(void);
26extern unsigned int pnx4008_cpu_standby_sz;
27extern void pnx4008_cpu_standby(void);
28
29extern int pnx4008_startup_pll(struct clk *);
30extern int pnx4008_shutdown_pll(struct clk *);
31
32#endif /* ASSEMBLER */
33#endif /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
deleted file mode 100644
index b383c7de7ab4..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/timex.h
3 *
4 * PNX4008 timers header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __PNX4008_TIMEX_H
15#define __PNX4008_TIMEX_H
16
17#define CLOCK_TICK_RATE 1000000
18
19#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/uncompress.h b/arch/arm/mach-pnx4008/include/mach/uncompress.h
deleted file mode 100644
index bb4751ee2539..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/uncompress.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2006 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#define UART5_BASE 0x40090000
23
24#define UART5_DR (*(volatile unsigned char *) (UART5_BASE))
25#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18))
26
27static __inline__ void putc(char c)
28{
29 while (UART5_FR & (1 << 5))
30 barrier();
31
32 UART5_DR = c;
33}
34
35/*
36 * This does not append a newline
37 */
38static inline void flush(void)
39{
40}
41
42/*
43 * nothing to do
44 */
45#define arch_decomp_setup()
46#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
deleted file mode 100644
index 41e4201972d5..000000000000
--- a/arch/arm/mach-pnx4008/irq.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/irq.c
3 *
4 * PNX4008 IRQ controller driver
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code received from Philips:
9 * Copyright (C) 2003 Philips Semiconductors
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/device.h>
25#include <linux/irq.h>
26#include <linux/io.h>
27#include <mach/hardware.h>
28#include <asm/setup.h>
29#include <asm/pgtable.h>
30#include <asm/page.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/irq.h>
33#include <asm/mach/map.h>
34#include <mach/irq.h>
35
36static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
37
38static void pnx4008_mask_irq(struct irq_data *d)
39{
40 __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
41}
42
43static void pnx4008_unmask_irq(struct irq_data *d)
44{
45 __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
46}
47
48static void pnx4008_mask_ack_irq(struct irq_data *d)
49{
50 __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
51 __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */
52}
53
54static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
55{
56 switch (type) {
57 case IRQ_TYPE_EDGE_RISING:
58 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
59 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
60 irq_set_handler(d->irq, handle_edge_irq);
61 break;
62 case IRQ_TYPE_EDGE_FALLING:
63 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
64 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
65 irq_set_handler(d->irq, handle_edge_irq);
66 break;
67 case IRQ_TYPE_LEVEL_LOW:
68 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
69 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
70 irq_set_handler(d->irq, handle_level_irq);
71 break;
72 case IRQ_TYPE_LEVEL_HIGH:
73 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
74 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
75 irq_set_handler(d->irq, handle_level_irq);
76 break;
77
78 /* IRQ_TYPE_EDGE_BOTH is not supported */
79 default:
80 printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
81 return -1;
82 }
83 return 0;
84}
85
86static struct irq_chip pnx4008_irq_chip = {
87 .irq_ack = pnx4008_mask_ack_irq,
88 .irq_mask = pnx4008_mask_irq,
89 .irq_unmask = pnx4008_unmask_irq,
90 .irq_set_type = pnx4008_set_irq_type,
91};
92
93void __init pnx4008_init_irq(void)
94{
95 unsigned int i;
96
97 /* configure IRQ's */
98 for (i = 0; i < NR_IRQS; i++) {
99 set_irq_flags(i, IRQF_VALID);
100 irq_set_chip(i, &pnx4008_irq_chip);
101 pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
102 }
103
104 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
105 pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
106 pnx4008_irq_type[SUB1_IRQ_N]);
107 pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
108 pnx4008_irq_type[SUB2_IRQ_N]);
109 pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
110 pnx4008_irq_type[SUB1_FIQ_N]);
111 pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
112 pnx4008_irq_type[SUB2_FIQ_N]);
113
114 /* mask all others */
115 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
116 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
117 INTC_ER(MAIN_BASE_INT));
118 __raw_writel(0, INTC_ER(SIC1_BASE_INT));
119 __raw_writel(0, INTC_ER(SIC2_BASE_INT));
120}
121
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
deleted file mode 100644
index 26f8d06b142a..000000000000
--- a/arch/arm/mach-pnx4008/pm.c
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/pm.c
3 *
4 * Power Management driver for PNX4008
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/pm.h>
15#include <linux/rtc.h>
16#include <linux/sched.h>
17#include <linux/proc_fs.h>
18#include <linux/suspend.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23
24#include <asm/cacheflush.h>
25
26#include <mach/hardware.h>
27#include <mach/pm.h>
28#include <mach/clock.h>
29
30#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
31
32static void *saved_sram;
33
34static struct clk *pll4_clk;
35
36static inline void pnx4008_standby(void)
37{
38 void (*pnx4008_cpu_standby_ptr) (void);
39
40 local_irq_disable();
41 local_fiq_disable();
42
43 clk_disable(pll4_clk);
44
45 /*saving portion of SRAM to be used by suspend function. */
46 memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
47
48 /*make sure SRAM copy gets physically written into SDRAM.
49 SDRAM will be placed into self-refresh during power down */
50 flush_cache_all();
51
52 /*copy suspend function into SRAM */
53 memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
54
55 /*do suspend */
56 pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
57 pnx4008_cpu_standby_ptr();
58
59 /*restoring portion of SRAM that was used by suspend function */
60 memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
61
62 clk_enable(pll4_clk);
63
64 local_fiq_enable();
65 local_irq_enable();
66}
67
68static inline void pnx4008_suspend(void)
69{
70 void (*pnx4008_cpu_suspend_ptr) (void);
71
72 local_irq_disable();
73 local_fiq_disable();
74
75 clk_disable(pll4_clk);
76
77 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
78 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
79
80 /*saving portion of SRAM to be used by suspend function. */
81 memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
82
83 /*make sure SRAM copy gets physically written into SDRAM.
84 SDRAM will be placed into self-refresh during power down */
85 flush_cache_all();
86
87 /*copy suspend function into SRAM */
88 memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
89
90 /*do suspend */
91 pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
92 pnx4008_cpu_suspend_ptr();
93
94 /*restoring portion of SRAM that was used by suspend function */
95 memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
96
97 clk_enable(pll4_clk);
98
99 local_fiq_enable();
100 local_irq_enable();
101}
102
103static int pnx4008_pm_enter(suspend_state_t state)
104{
105 switch (state) {
106 case PM_SUSPEND_STANDBY:
107 pnx4008_standby();
108 break;
109 case PM_SUSPEND_MEM:
110 pnx4008_suspend();
111 break;
112 }
113 return 0;
114}
115
116static int pnx4008_pm_valid(suspend_state_t state)
117{
118 return (state == PM_SUSPEND_STANDBY) ||
119 (state == PM_SUSPEND_MEM);
120}
121
122static const struct platform_suspend_ops pnx4008_pm_ops = {
123 .enter = pnx4008_pm_enter,
124 .valid = pnx4008_pm_valid,
125};
126
127int __init pnx4008_pm_init(void)
128{
129 u32 sram_size_to_allocate;
130
131 pll4_clk = clk_get(0, "ck_pll4");
132 if (IS_ERR(pll4_clk)) {
133 printk(KERN_ERR
134 "PM Suspend cannot acquire ARM(PLL4) clock control\n");
135 return PTR_ERR(pll4_clk);
136 }
137
138 if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
139 sram_size_to_allocate = pnx4008_cpu_standby_sz;
140 else
141 sram_size_to_allocate = pnx4008_cpu_suspend_sz;
142
143 saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
144 if (!saved_sram) {
145 printk(KERN_ERR
146 "PM Suspend: cannot allocate memory to save portion of SRAM\n");
147 clk_put(pll4_clk);
148 return -ENOMEM;
149 }
150
151 suspend_set_ops(&pnx4008_pm_ops);
152 return 0;
153}
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
deleted file mode 100644
index 374c138ac1ac..000000000000
--- a/arch/arm/mach-pnx4008/serial.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * linux/arch/arm/mach-pnx4008/serial.c
3 *
4 * PNX4008 UART initialization
5 *
6 * Copyright: MontaVista Software Inc. (c) 2005
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/io.h>
15
16#include <mach/platform.h>
17#include <mach/hardware.h>
18
19#include <linux/serial_core.h>
20#include <linux/serial_reg.h>
21
22#include <mach/gpio-pnx4008.h>
23#include <mach/clock.h>
24
25#define UART_3 0
26#define UART_4 1
27#define UART_5 2
28#define UART_6 3
29#define UART_UNKNOWN (-1)
30
31#define UART3_BASE_VA IO_ADDRESS(PNX4008_UART3_BASE)
32#define UART4_BASE_VA IO_ADDRESS(PNX4008_UART4_BASE)
33#define UART5_BASE_VA IO_ADDRESS(PNX4008_UART5_BASE)
34#define UART6_BASE_VA IO_ADDRESS(PNX4008_UART6_BASE)
35
36#define UART_FCR_OFFSET 8
37#define UART_FIFO_SIZE 64
38
39void pnx4008_uart_init(void)
40{
41 u32 tmp;
42 int i = UART_FIFO_SIZE;
43
44 __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
45 __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
46
47 /* Send a NULL to fix the UART HW bug */
48 __raw_writel(0x00, UART5_BASE_VA);
49 __raw_writel(0x00, UART3_BASE_VA);
50
51 while (i--) {
52 tmp = __raw_readl(UART5_BASE_VA);
53 tmp = __raw_readl(UART3_BASE_VA);
54 }
55 __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
56 __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
57
58 /* setup wakeup interrupt */
59 start_int_set_rising_edge(SE_U3_RX_INT);
60 start_int_ack(SE_U3_RX_INT);
61 start_int_umask(SE_U3_RX_INT);
62
63 start_int_set_rising_edge(SE_U5_RX_INT);
64 start_int_ack(SE_U5_RX_INT);
65 start_int_umask(SE_U5_RX_INT);
66}
67
diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S
deleted file mode 100644
index f4eed495d295..000000000000
--- a/arch/arm/mach-pnx4008/sleep.S
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * linux/arch/arm/mach-pnx4008/sleep.S
3 *
4 * PNX4008 support for STOP mode and SDRAM self-refresh
5 *
6 * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/linkage.h>
15#include <asm/assembler.h>
16#include <mach/hardware.h>
17
18#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
19#define PWR_CTRL_REG_OFFS 0x44
20
21#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
22#define MPMC_STATUS_REG_OFFS 0x4
23
24 .text
25
26ENTRY(pnx4008_cpu_suspend)
27 @this function should be entered in Direct run mode.
28
29 @ save registers on stack
30 stmfd sp!, {r0 - r6, lr}
31
32 @ setup Power Manager base address in r4
33 @ and put it's value in r5
34 mov r4, #(PWRMAN_VA_BASE & 0xff000000)
35 orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
36 orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
37 orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
38 ldr r5, [r4, #PWR_CTRL_REG_OFFS]
39
40 @ setup SDRAM controller base address in r2
41 @ and put it's value in r3
42 mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
43 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
44 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
45 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
46 ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
47
48 @ clear SDRAM self-refresh bit latch
49 and r5, r5, #(~(1 << 8))
50 @ clear SDRAM self-refresh bit
51 and r5, r5, #(~(1 << 9))
52 str r5, [r4, #PWR_CTRL_REG_OFFS]
53
54 @ do save current bit settings in r1
55 mov r1, r5
56
57 @ set SDRAM self-refresh bit
58 orr r5, r5, #(1 << 9)
59 str r5, [r4, #PWR_CTRL_REG_OFFS]
60
61 @ set SDRAM self-refresh bit latch
62 orr r5, r5, #(1 << 8)
63 str r5, [r4, #PWR_CTRL_REG_OFFS]
64
65 @ clear SDRAM self-refresh bit latch
66 and r5, r5, #(~(1 << 8))
67 str r5, [r4, #PWR_CTRL_REG_OFFS]
68
69 @ clear SDRAM self-refresh bit
70 and r5, r5, #(~(1 << 9))
71 str r5, [r4, #PWR_CTRL_REG_OFFS]
72
73 @ wait for SDRAM to get into self-refresh mode
742: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
75 tst r3, #(1 << 2)
76 beq 2b
77
78 @ to prepare SDRAM to get out of self-refresh mode after wakeup
79 orr r5, r5, #(1 << 7)
80 str r5, [r4, #PWR_CTRL_REG_OFFS]
81
82 @ do enter stop mode
83 orr r5, r5, #(1 << 0)
84 str r5, [r4, #PWR_CTRL_REG_OFFS]
85 nop
86 nop
87 nop
88 nop
89 nop
90 nop
91 nop
92 nop
93 nop
94
95 @ sleeping now...
96
97 @ coming out of STOP mode into Direct Run mode
98 @ clear STOP mode and SDRAM self-refresh bits
99 str r1, [r4, #PWR_CTRL_REG_OFFS]
100
101 @ wait for SDRAM to get out self-refresh mode
1023: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
103 tst r3, #5
104 bne 3b
105
106 @ restore regs and return
107 ldmfd sp!, {r0 - r6, pc}
108
109ENTRY(pnx4008_cpu_suspend_sz)
110 .word . - pnx4008_cpu_suspend
111
112ENTRY(pnx4008_cpu_standby)
113 @ save registers on stack
114 stmfd sp!, {r0 - r6, lr}
115
116 @ setup Power Manager base address in r4
117 @ and put it's value in r5
118 mov r4, #(PWRMAN_VA_BASE & 0xff000000)
119 orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
120 orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
121 orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
122 ldr r5, [r4, #PWR_CTRL_REG_OFFS]
123
124 @ setup SDRAM controller base address in r2
125 @ and put it's value in r3
126 mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
127 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
128 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
129 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
130 ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
131
132 @ clear SDRAM self-refresh bit latch
133 and r5, r5, #(~(1 << 8))
134 @ clear SDRAM self-refresh bit
135 and r5, r5, #(~(1 << 9))
136 str r5, [r4, #PWR_CTRL_REG_OFFS]
137
138 @ do save current bit settings in r1
139 mov r1, r5
140
141 @ set SDRAM self-refresh bit
142 orr r5, r5, #(1 << 9)
143 str r5, [r4, #PWR_CTRL_REG_OFFS]
144
145 @ set SDRAM self-refresh bit latch
146 orr r5, r5, #(1 << 8)
147 str r5, [r4, #PWR_CTRL_REG_OFFS]
148
149 @ clear SDRAM self-refresh bit latch
150 and r5, r5, #(~(1 << 8))
151 str r5, [r4, #PWR_CTRL_REG_OFFS]
152
153 @ clear SDRAM self-refresh bit
154 and r5, r5, #(~(1 << 9))
155 str r5, [r4, #PWR_CTRL_REG_OFFS]
156
157 @ wait for SDRAM to get into self-refresh mode
1582: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
159 tst r3, #(1 << 2)
160 beq 2b
161
162 @ set 'get out of self-refresh mode after wakeup' bit
163 orr r5, r5, #(1 << 7)
164 str r5, [r4, #PWR_CTRL_REG_OFFS]
165
166 mcr p15, 0, r0, c7, c0, 4 @ kinda sleeping now...
167
168 @ set SDRAM self-refresh bit latch
169 orr r5, r5, #(1 << 8)
170 str r5, [r4, #PWR_CTRL_REG_OFFS]
171
172 @ clear SDRAM self-refresh bit latch
173 and r5, r5, #(~(1 << 8))
174 str r5, [r4, #PWR_CTRL_REG_OFFS]
175
176 @ wait for SDRAM to get out self-refresh mode
1773: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
178 tst r3, #5
179 bne 3b
180
181 @ restore regs and return
182 ldmfd sp!, {r0 - r6, pc}
183
184ENTRY(pnx4008_cpu_standby_sz)
185 .word . - pnx4008_cpu_standby
186
187ENTRY(pnx4008_cache_clean_invalidate)
188 stmfd sp!, {r0 - r6, lr}
189#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
190 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
191#else
1921: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
193 bne 1b
194#endif
195 ldmfd sp!, {r0 - r6, pc}
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
deleted file mode 100644
index 0cfe8af3d3be..000000000000
--- a/arch/arm/mach-pnx4008/time.c
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/time.c
3 *
4 * PNX4008 Timers
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/sched.h>
19#include <linux/spinlock.h>
20#include <linux/module.h>
21#include <linux/kallsyms.h>
22#include <linux/time.h>
23#include <linux/timex.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <asm/leds.h>
29#include <asm/mach/time.h>
30#include <asm/errno.h>
31
32#include "time.h"
33
34/*! Note: all timers are UPCOUNTING */
35
36/*!
37 * Returns number of us since last clock interrupt. Note that interrupts
38 * will have been disabled by do_gettimeoffset()
39 */
40static unsigned long pnx4008_gettimeoffset(void)
41{
42 u32 ticks_to_match =
43 __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
44 u32 elapsed = LATCH - ticks_to_match;
45 return (elapsed * (tick_nsec / 1000)) / LATCH;
46}
47
48/*!
49 * IRQ handler for the timer
50 */
51static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
52{
53 if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
54
55 do {
56 timer_tick();
57
58 /*
59 * this algorithm takes care of possible delay
60 * for this interrupt handling longer than a normal
61 * timer period
62 */
63 __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
64 HSTIM_MATCH0);
65 __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
66
67 /*
68 * The goal is to keep incrementing HSTIM_MATCH0
69 * register until HSTIM_MATCH0 indicates time after
70 * what HSTIM_COUNTER indicates.
71 */
72 } while ((signed)
73 (__raw_readl(HSTIM_MATCH0) -
74 __raw_readl(HSTIM_COUNTER)) < 0);
75 }
76
77 return IRQ_HANDLED;
78}
79
80static struct irqaction pnx4008_timer_irq = {
81 .name = "PNX4008 Tick Timer",
82 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
83 .handler = pnx4008_timer_interrupt
84};
85
86/*!
87 * Set up timer and timer interrupt.
88 */
89static __init void pnx4008_setup_timer(void)
90{
91 __raw_writel(RESET_COUNT, MSTIM_CTRL);
92 while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
93 __raw_writel(0, MSTIM_CTRL); /* stop the timer */
94 __raw_writel(0, MSTIM_MCTRL);
95
96 __raw_writel(RESET_COUNT, HSTIM_CTRL);
97 while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
98 __raw_writel(0, HSTIM_CTRL);
99 __raw_writel(0, HSTIM_MCTRL);
100 __raw_writel(0, HSTIM_CCR);
101 __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
102 __raw_writel(LATCH, HSTIM_MATCH0);
103 __raw_writel(MR0_INT, HSTIM_MCTRL);
104
105 setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
106
107 __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */
108}
109
110/* Timer Clock Control in PM register */
111#define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
112#define WATCHDOG_CLK_EN 1
113#define TIMER_CLK_EN 2 /* HS and MS timers? */
114
115static u32 timclk_ctrl_reg_save;
116
117void pnx4008_timer_suspend(void)
118{
119 timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
120 __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */
121}
122
123void pnx4008_timer_resume(void)
124{
125 __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */
126}
127
128struct sys_timer pnx4008_timer = {
129 .init = pnx4008_setup_timer,
130 .offset = pnx4008_gettimeoffset,
131 .suspend = pnx4008_timer_suspend,
132 .resume = pnx4008_timer_resume,
133};
134
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
deleted file mode 100644
index 75e88c570aa7..000000000000
--- a/arch/arm/mach-pnx4008/time.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/timex.h
3 *
4 * PNX4008 timers header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef PNX_TIME_H
14#define PNX_TIME_H
15
16#include <linux/io.h>
17#include <mach/hardware.h>
18
19#define TICKS2USECS(x) (x)
20
21/* MilliSecond Timer - Chapter 21 Page 202 */
22
23#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
24#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
25#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
26#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
27#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
28#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
29
30/* High Speed Timer - Chpater 22, Page 205 */
31
32#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
33#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
34#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
35#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
36#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
37#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
38#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
39#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
40#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
41#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
42#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
43#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
44
45/* IMPORTANT: both timers are UPCOUNTING */
46
47/* xSTIM_MCTRL bit definitions */
48#define MR0_INT 1
49#define RESET_COUNT0 (1<<1)
50#define STOP_COUNT0 (1<<2)
51#define MR1_INT (1<<3)
52#define RESET_COUNT1 (1<<4)
53#define STOP_COUNT1 (1<<5)
54#define MR2_INT (1<<6)
55#define RESET_COUNT2 (1<<7)
56#define STOP_COUNT2 (1<<8)
57
58/* xSTIM_CTRL bit definitions */
59#define COUNT_ENAB 1
60#define RESET_COUNT (1<<1)
61#define DEBUG_EN (1<<2)
62
63/* xSTIM_INT bit definitions */
64#define MATCH0_INT 1
65#define MATCH1_INT (1<<1)
66#define MATCH2_INT (1<<2)
67#define RTC_TICK0 (1<<4)
68#define RTC_TICK1 (1<<5)
69
70#endif
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