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authorLinus Torvalds <torvalds@g5.osdl.org>2006-07-05 16:03:18 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-05 16:03:18 -0400
commit887e5d5fcc96e3a7c91e19d9bb419c10196ffdc1 (patch)
tree259fac45eddabae544b972c21fae7c031202b910 /arch/arm/mach-pnx4008/irq.c
parente8f75588dd5885868147b329ced4a5093dc6402e (diff)
parentba854e18413d2d827f050984edeb8286c3335895 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 3711/1: AT91 timer update [ARM] 3709/1: pnx4008: convert to generic irq subsystem [ARM] 3710/1: AT91 Serial: Use GPIO API
Diffstat (limited to 'arch/arm/mach-pnx4008/irq.c')
-rw-r--r--arch/arm/mach-pnx4008/irq.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 9b0a8e084e99..3a4bcf3d91fa 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -22,8 +22,8 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/ioport.h> 23#include <linux/ioport.h>
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/irq.h>
25#include <asm/hardware.h> 26#include <asm/hardware.h>
26#include <asm/irq.h>
27#include <asm/io.h> 27#include <asm/io.h>
28#include <asm/setup.h> 28#include <asm/setup.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
@@ -96,26 +96,24 @@ void __init pnx4008_init_irq(void)
96{ 96{
97 unsigned int i; 97 unsigned int i;
98 98
99 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */ 99 /* configure IRQ's */
100 for (i = 0; i < NR_IRQS; i++) {
101 set_irq_flags(i, IRQF_VALID);
102 set_irq_chip(i, &pnx4008_irq_chip);
103 pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
104 }
105
106 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
100 pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]); 107 pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
101 pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]); 108 pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
102 pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]); 109 pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
103 pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]); 110 pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
104 111
112 /* mask all others */
105 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | 113 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
106 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N), 114 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
107 INTC_ER(MAIN_BASE_INT)); 115 INTC_ER(MAIN_BASE_INT));
108 __raw_writel(0, INTC_ER(SIC1_BASE_INT)); 116 __raw_writel(0, INTC_ER(SIC1_BASE_INT));
109 __raw_writel(0, INTC_ER(SIC2_BASE_INT)); 117 __raw_writel(0, INTC_ER(SIC2_BASE_INT));
110
111 /* configure all other IRQ's */
112 for (i = 0; i < NR_IRQS; i++) {
113 if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
114 i == SUB2_IRQ_N || i == SUB1_IRQ_N)
115 continue;
116 set_irq_flags(i, IRQF_VALID);
117 set_irq_chip(i, &pnx4008_irq_chip);
118 pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
119 }
120} 118}
121 119