diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-10-19 19:51:03 -0400 |
---|---|---|
committer | Nicolas Pitre <nico@cam.org> | 2008-12-20 12:21:02 -0500 |
commit | 9569dae75f6f6987e79fa26cf6da3fc24006c996 (patch) | |
tree | b5982f41aea6ccee37af54fc8f7750aaff7e0bff /arch/arm/mach-orion5x | |
parent | 6fd7c7fe72a46dfd227fe8db0c7b6863af90a982 (diff) |
[ARM] Orion: share GPIO handling code
Split off Orion GPIO handling code into plat-orion/, and add
support for multiple sets of (32) GPIO pins.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion5x')
-rw-r--r-- | arch/arm/mach-orion5x/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/common.h | 7 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/gpio.c | 231 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/gpio.h | 26 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/irqs.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/orion5x.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/irq.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/mpp.c | 6 |
8 files changed, 35 insertions, 271 deletions
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 3d4a1bc12355..edc38e2c856f 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile | |||
@@ -1,4 +1,4 @@ | |||
1 | obj-y += common.o addr-map.o pci.o gpio.o irq.o mpp.o | 1 | obj-y += common.o addr-map.o pci.o irq.o mpp.o |
2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o | 2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o |
3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o | 3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o |
4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o | 4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index a000c7c6ee96..798b9a5e3da9 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h | |||
@@ -51,13 +51,6 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); | |||
51 | struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); | 51 | struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); |
52 | int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); | 52 | int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); |
53 | 53 | ||
54 | /* | ||
55 | * Valid GPIO pins according to MPP setup, used by machine-setup. | ||
56 | * (/mach-orion/gpio.c). | ||
57 | */ | ||
58 | void orion5x_gpio_set_valid(unsigned pin, int valid); | ||
59 | void gpio_display(void); /* debug */ | ||
60 | |||
61 | struct machine_desc; | 54 | struct machine_desc; |
62 | struct meminfo; | 55 | struct meminfo; |
63 | struct tag; | 56 | struct tag; |
diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c deleted file mode 100644 index f99d08811e5a..000000000000 --- a/arch/arm/mach-orion5x/gpio.c +++ /dev/null | |||
@@ -1,231 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-orion5x/gpio.c | ||
3 | * | ||
4 | * GPIO functions for Marvell Orion System On Chip | ||
5 | * | ||
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/spinlock.h> | ||
17 | #include <linux/bitops.h> | ||
18 | #include <linux/io.h> | ||
19 | #include <asm/gpio.h> | ||
20 | #include <mach/orion5x.h> | ||
21 | #include "common.h" | ||
22 | |||
23 | static DEFINE_SPINLOCK(gpio_lock); | ||
24 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; | ||
25 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ | ||
26 | |||
27 | void __init orion5x_gpio_set_valid(unsigned pin, int valid) | ||
28 | { | ||
29 | if (valid) | ||
30 | __set_bit(pin, gpio_valid); | ||
31 | else | ||
32 | __clear_bit(pin, gpio_valid); | ||
33 | } | ||
34 | |||
35 | /* | ||
36 | * GENERIC_GPIO primitives | ||
37 | */ | ||
38 | int gpio_direction_input(unsigned pin) | ||
39 | { | ||
40 | unsigned long flags; | ||
41 | |||
42 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | ||
43 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | ||
44 | return -EINVAL; | ||
45 | } | ||
46 | |||
47 | spin_lock_irqsave(&gpio_lock, flags); | ||
48 | |||
49 | /* | ||
50 | * Some callers might have not used the gpio_request(), | ||
51 | * so flag this pin as requested now. | ||
52 | */ | ||
53 | if (!gpio_label[pin]) | ||
54 | gpio_label[pin] = "?"; | ||
55 | |||
56 | orion5x_setbits(GPIO_IO_CONF, 1 << pin); | ||
57 | |||
58 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
59 | return 0; | ||
60 | } | ||
61 | EXPORT_SYMBOL(gpio_direction_input); | ||
62 | |||
63 | int gpio_direction_output(unsigned pin, int value) | ||
64 | { | ||
65 | unsigned long flags; | ||
66 | int mask; | ||
67 | |||
68 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | ||
69 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | ||
70 | return -EINVAL; | ||
71 | } | ||
72 | |||
73 | spin_lock_irqsave(&gpio_lock, flags); | ||
74 | |||
75 | /* | ||
76 | * Some callers might have not used the gpio_request(), | ||
77 | * so flag this pin as requested now. | ||
78 | */ | ||
79 | if (!gpio_label[pin]) | ||
80 | gpio_label[pin] = "?"; | ||
81 | |||
82 | mask = 1 << pin; | ||
83 | orion5x_clrbits(GPIO_BLINK_EN, mask); | ||
84 | if (value) | ||
85 | orion5x_setbits(GPIO_OUT, mask); | ||
86 | else | ||
87 | orion5x_clrbits(GPIO_OUT, mask); | ||
88 | orion5x_clrbits(GPIO_IO_CONF, mask); | ||
89 | |||
90 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
91 | return 0; | ||
92 | } | ||
93 | EXPORT_SYMBOL(gpio_direction_output); | ||
94 | |||
95 | int gpio_get_value(unsigned pin) | ||
96 | { | ||
97 | int val, mask = 1 << pin; | ||
98 | |||
99 | if (readl(GPIO_IO_CONF) & mask) | ||
100 | val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL); | ||
101 | else | ||
102 | val = readl(GPIO_OUT); | ||
103 | |||
104 | return val & mask; | ||
105 | } | ||
106 | EXPORT_SYMBOL(gpio_get_value); | ||
107 | |||
108 | void gpio_set_value(unsigned pin, int value) | ||
109 | { | ||
110 | unsigned long flags; | ||
111 | int mask = 1 << pin; | ||
112 | |||
113 | spin_lock_irqsave(&gpio_lock, flags); | ||
114 | |||
115 | orion5x_clrbits(GPIO_BLINK_EN, mask); | ||
116 | if (value) | ||
117 | orion5x_setbits(GPIO_OUT, mask); | ||
118 | else | ||
119 | orion5x_clrbits(GPIO_OUT, mask); | ||
120 | |||
121 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
122 | } | ||
123 | EXPORT_SYMBOL(gpio_set_value); | ||
124 | |||
125 | void orion5x_gpio_set_blink(unsigned pin, int blink) | ||
126 | { | ||
127 | unsigned long flags; | ||
128 | int mask = 1 << pin; | ||
129 | |||
130 | spin_lock_irqsave(&gpio_lock, flags); | ||
131 | |||
132 | orion5x_clrbits(GPIO_OUT, mask); | ||
133 | if (blink) | ||
134 | orion5x_setbits(GPIO_BLINK_EN, mask); | ||
135 | else | ||
136 | orion5x_clrbits(GPIO_BLINK_EN, mask); | ||
137 | |||
138 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
139 | } | ||
140 | EXPORT_SYMBOL(orion5x_gpio_set_blink); | ||
141 | |||
142 | int gpio_request(unsigned pin, const char *label) | ||
143 | { | ||
144 | int ret = 0; | ||
145 | unsigned long flags; | ||
146 | |||
147 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | ||
148 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | ||
149 | return -EINVAL; | ||
150 | } | ||
151 | |||
152 | spin_lock_irqsave(&gpio_lock, flags); | ||
153 | |||
154 | if (gpio_label[pin]) { | ||
155 | pr_debug("%s: GPIO %d already used as %s\n", | ||
156 | __func__, pin, gpio_label[pin]); | ||
157 | ret = -EBUSY; | ||
158 | } else | ||
159 | gpio_label[pin] = label ? label : "?"; | ||
160 | |||
161 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
162 | return ret; | ||
163 | } | ||
164 | EXPORT_SYMBOL(gpio_request); | ||
165 | |||
166 | void gpio_free(unsigned pin) | ||
167 | { | ||
168 | might_sleep(); | ||
169 | |||
170 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | ||
171 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | ||
172 | return; | ||
173 | } | ||
174 | |||
175 | if (!gpio_label[pin]) | ||
176 | pr_warning("%s: GPIO %d already freed\n", __func__, pin); | ||
177 | else | ||
178 | gpio_label[pin] = NULL; | ||
179 | } | ||
180 | EXPORT_SYMBOL(gpio_free); | ||
181 | |||
182 | /* Debug helper */ | ||
183 | void gpio_display(void) | ||
184 | { | ||
185 | int i; | ||
186 | |||
187 | for (i = 0; i < GPIO_MAX; i++) { | ||
188 | printk(KERN_DEBUG "Pin-%d: ", i); | ||
189 | |||
190 | if (!test_bit(i, gpio_valid)) { | ||
191 | printk("non-GPIO\n"); | ||
192 | } else if (!gpio_label[i]) { | ||
193 | printk("GPIO, free\n"); | ||
194 | } else { | ||
195 | printk("GPIO, used by %s, ", gpio_label[i]); | ||
196 | if (readl(GPIO_IO_CONF) & (1 << i)) { | ||
197 | printk("input, active %s, level %s, edge %s\n", | ||
198 | ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high", | ||
199 | ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", | ||
200 | ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); | ||
201 | } else { | ||
202 | printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1); | ||
203 | } | ||
204 | } | ||
205 | } | ||
206 | |||
207 | printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", | ||
208 | MPP_0_7_CTRL, readl(MPP_0_7_CTRL)); | ||
209 | printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", | ||
210 | MPP_8_15_CTRL, readl(MPP_8_15_CTRL)); | ||
211 | printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", | ||
212 | MPP_16_19_CTRL, readl(MPP_16_19_CTRL)); | ||
213 | printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", | ||
214 | MPP_DEV_CTRL, readl(MPP_DEV_CTRL)); | ||
215 | printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", | ||
216 | GPIO_OUT, readl(GPIO_OUT)); | ||
217 | printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", | ||
218 | GPIO_IO_CONF, readl(GPIO_IO_CONF)); | ||
219 | printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", | ||
220 | GPIO_BLINK_EN, readl(GPIO_BLINK_EN)); | ||
221 | printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", | ||
222 | GPIO_IN_POL, readl(GPIO_IN_POL)); | ||
223 | printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", | ||
224 | GPIO_DATA_IN, readl(GPIO_DATA_IN)); | ||
225 | printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", | ||
226 | GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK)); | ||
227 | printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", | ||
228 | GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE)); | ||
229 | printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", | ||
230 | GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK)); | ||
231 | } | ||
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h index 65dc136a86f7..a1a387b189a0 100644 --- a/arch/arm/mach-orion5x/include/mach/gpio.h +++ b/arch/arm/mach-orion5x/include/mach/gpio.h | |||
@@ -2,18 +2,23 @@ | |||
2 | * arch/arm/mach-orion5x/include/mach/gpio.h | 2 | * arch/arm/mach-orion5x/include/mach/gpio.h |
3 | * | 3 | * |
4 | * This file is licensed under the terms of the GNU General Public | 4 | * This file is licensed under the terms of the GNU General Public |
5 | * License version 2. This program is licensed "as is" without any | 5 | * License version 2. This program is licensed "as is" without any |
6 | * warranty of any kind, whether express or implied. | 6 | * warranty of any kind, whether express or implied. |
7 | */ | 7 | */ |
8 | 8 | ||
9 | extern int gpio_request(unsigned pin, const char *label); | 9 | #ifndef __ASM_ARCH_GPIO_H |
10 | extern void gpio_free(unsigned pin); | 10 | #define __ASM_ARCH_GPIO_H |
11 | extern int gpio_direction_input(unsigned pin); | 11 | |
12 | extern int gpio_direction_output(unsigned pin, int value); | 12 | #include <mach/irqs.h> |
13 | extern int gpio_get_value(unsigned pin); | 13 | #include <plat/gpio.h> |
14 | extern void gpio_set_value(unsigned pin, int value); | 14 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
15 | extern void orion5x_gpio_set_blink(unsigned pin, int blink); | 15 | |
16 | extern void gpio_display(void); /* debug */ | 16 | #define GPIO_MAX 32 |
17 | #define GPIO_OUT(pin) ORION5X_DEV_BUS_REG(0x100) | ||
18 | #define GPIO_IO_CONF(pin) ORION5X_DEV_BUS_REG(0x104) | ||
19 | #define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108) | ||
20 | #define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c) | ||
21 | #define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110) | ||
17 | 22 | ||
18 | static inline int gpio_to_irq(int pin) | 23 | static inline int gpio_to_irq(int pin) |
19 | { | 24 | { |
@@ -25,4 +30,5 @@ static inline int irq_to_gpio(int irq) | |||
25 | return irq - IRQ_ORION5X_GPIO_START; | 30 | return irq - IRQ_ORION5X_GPIO_START; |
26 | } | 31 | } |
27 | 32 | ||
28 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 33 | |
34 | #endif | ||
diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h index d5b0fbf6b965..a6fa9d8f12d8 100644 --- a/arch/arm/mach-orion5x/include/mach/irqs.h +++ b/arch/arm/mach-orion5x/include/mach/irqs.h | |||
@@ -13,8 +13,6 @@ | |||
13 | #ifndef __ASM_ARCH_IRQS_H | 13 | #ifndef __ASM_ARCH_IRQS_H |
14 | #define __ASM_ARCH_IRQS_H | 14 | #define __ASM_ARCH_IRQS_H |
15 | 15 | ||
16 | #include "orion5x.h" /* need GPIO_MAX */ | ||
17 | |||
18 | /* | 16 | /* |
19 | * Orion Main Interrupt Controller | 17 | * Orion Main Interrupt Controller |
20 | */ | 18 | */ |
@@ -54,7 +52,7 @@ | |||
54 | * Orion General Purpose Pins | 52 | * Orion General Purpose Pins |
55 | */ | 53 | */ |
56 | #define IRQ_ORION5X_GPIO_START 32 | 54 | #define IRQ_ORION5X_GPIO_START 32 |
57 | #define NR_GPIO_IRQS GPIO_MAX | 55 | #define NR_GPIO_IRQS 32 |
58 | 56 | ||
59 | #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) | 57 | #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) |
60 | 58 | ||
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 9f5ce1ce5840..a8915081773b 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h | |||
@@ -134,11 +134,6 @@ | |||
134 | #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) | 134 | #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) |
135 | #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) | 135 | #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) |
136 | #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) | 136 | #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) |
137 | #define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) | ||
138 | #define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) | ||
139 | #define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) | ||
140 | #define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) | ||
141 | #define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) | ||
142 | #define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) | 137 | #define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) |
143 | #define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) | 138 | #define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) |
144 | #define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) | 139 | #define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) |
@@ -149,7 +144,6 @@ | |||
149 | #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) | 144 | #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) |
150 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) | 145 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) |
151 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) | 146 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) |
152 | #define GPIO_MAX 32 | ||
153 | 147 | ||
154 | /*************************************************************************** | 148 | /*************************************************************************** |
155 | * Orion CPU Bridge Registers | 149 | * Orion CPU Bridge Registers |
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 632a36f5cf14..6b2f1353797e 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
@@ -22,7 +22,7 @@ | |||
22 | /***************************************************************************** | 22 | /***************************************************************************** |
23 | * Orion GPIO IRQ | 23 | * Orion GPIO IRQ |
24 | * | 24 | * |
25 | * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same | 25 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same |
26 | * value of the line or the opposite value. | 26 | * value of the line or the opposite value. |
27 | * | 27 | * |
28 | * Level IRQ handlers: DATA_IN is used directly as cause register. | 28 | * Level IRQ handlers: DATA_IN is used directly as cause register. |
@@ -82,7 +82,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) | |||
82 | int pin = irq_to_gpio(irq); | 82 | int pin = irq_to_gpio(irq); |
83 | struct irq_desc *desc; | 83 | struct irq_desc *desc; |
84 | 84 | ||
85 | if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) { | 85 | if ((readl(GPIO_IO_CONF(pin)) & (1 << pin)) == 0) { |
86 | printk(KERN_ERR "orion5x_gpio_set_irq_type failed " | 86 | printk(KERN_ERR "orion5x_gpio_set_irq_type failed " |
87 | "(irq %d, pin %d).\n", irq, pin); | 87 | "(irq %d, pin %d).\n", irq, pin); |
88 | return -EINVAL; | 88 | return -EINVAL; |
@@ -94,22 +94,22 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) | |||
94 | case IRQ_TYPE_LEVEL_HIGH: | 94 | case IRQ_TYPE_LEVEL_HIGH: |
95 | desc->handle_irq = handle_level_irq; | 95 | desc->handle_irq = handle_level_irq; |
96 | desc->status |= IRQ_LEVEL; | 96 | desc->status |= IRQ_LEVEL; |
97 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); | 97 | orion5x_clrbits(GPIO_IN_POL(pin), (1 << pin)); |
98 | break; | 98 | break; |
99 | case IRQ_TYPE_LEVEL_LOW: | 99 | case IRQ_TYPE_LEVEL_LOW: |
100 | desc->handle_irq = handle_level_irq; | 100 | desc->handle_irq = handle_level_irq; |
101 | desc->status |= IRQ_LEVEL; | 101 | desc->status |= IRQ_LEVEL; |
102 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); | 102 | orion5x_setbits(GPIO_IN_POL(pin), (1 << pin)); |
103 | break; | 103 | break; |
104 | case IRQ_TYPE_EDGE_RISING: | 104 | case IRQ_TYPE_EDGE_RISING: |
105 | desc->handle_irq = handle_edge_irq; | 105 | desc->handle_irq = handle_edge_irq; |
106 | desc->status &= ~IRQ_LEVEL; | 106 | desc->status &= ~IRQ_LEVEL; |
107 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); | 107 | orion5x_clrbits(GPIO_IN_POL(pin), (1 << pin)); |
108 | break; | 108 | break; |
109 | case IRQ_TYPE_EDGE_FALLING: | 109 | case IRQ_TYPE_EDGE_FALLING: |
110 | desc->handle_irq = handle_edge_irq; | 110 | desc->handle_irq = handle_edge_irq; |
111 | desc->status &= ~IRQ_LEVEL; | 111 | desc->status &= ~IRQ_LEVEL; |
112 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); | 112 | orion5x_setbits(GPIO_IN_POL(pin), (1 << pin)); |
113 | break; | 113 | break; |
114 | case IRQ_TYPE_EDGE_BOTH: | 114 | case IRQ_TYPE_EDGE_BOTH: |
115 | desc->handle_irq = handle_edge_irq; | 115 | desc->handle_irq = handle_edge_irq; |
@@ -117,11 +117,11 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) | |||
117 | /* | 117 | /* |
118 | * set initial polarity based on current input level | 118 | * set initial polarity based on current input level |
119 | */ | 119 | */ |
120 | if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN)) | 120 | if ((readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin))) |
121 | & (1 << pin)) | 121 | & (1 << pin)) |
122 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ | 122 | orion5x_setbits(GPIO_IN_POL(pin), (1 << pin)); /* falling */ |
123 | else | 123 | else |
124 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ | 124 | orion5x_clrbits(GPIO_IN_POL(pin), (1 << pin)); /* rising */ |
125 | 125 | ||
126 | break; | 126 | break; |
127 | default: | 127 | default: |
@@ -149,7 +149,7 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
149 | 149 | ||
150 | BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); | 150 | BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); |
151 | offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; | 151 | offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; |
152 | cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) | | 152 | cause = (readl(GPIO_DATA_IN(offs)) & readl(GPIO_LEVEL_MASK)) | |
153 | (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK)); | 153 | (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK)); |
154 | 154 | ||
155 | for (pin = offs; pin < offs + 8; pin++) { | 155 | for (pin = offs; pin < offs + 8; pin++) { |
@@ -158,9 +158,9 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
158 | desc = irq_desc + irq; | 158 | desc = irq_desc + irq; |
159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | 159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
160 | /* Swap polarity (race with GPIO line) */ | 160 | /* Swap polarity (race with GPIO line) */ |
161 | u32 polarity = readl(GPIO_IN_POL); | 161 | u32 polarity = readl(GPIO_IN_POL(pin)); |
162 | polarity ^= 1 << pin; | 162 | polarity ^= 1 << pin; |
163 | writel(polarity, GPIO_IN_POL); | 163 | writel(polarity, GPIO_IN_POL(pin)); |
164 | } | 164 | } |
165 | generic_handle_irq(irq); | 165 | generic_handle_irq(irq); |
166 | } | 166 | } |
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 640ea2a3fc6c..e23a3f91d6c6 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c | |||
@@ -12,6 +12,7 @@ | |||
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/mbus.h> | 13 | #include <linux/mbus.h> |
14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
15 | #include <asm/gpio.h> | ||
15 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
16 | #include "common.h" | 17 | #include "common.h" |
17 | #include "mpp.h" | 18 | #include "mpp.h" |
@@ -152,7 +153,10 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) | |||
152 | *reg &= ~(0xf << shift); | 153 | *reg &= ~(0xf << shift); |
153 | *reg |= (num_type & 0xf) << shift; | 154 | *reg |= (num_type & 0xf) << shift; |
154 | 155 | ||
155 | orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); | 156 | if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182())) |
157 | orion_gpio_set_unused(mode->mpp); | ||
158 | |||
159 | orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); | ||
156 | 160 | ||
157 | mode++; | 161 | mode++; |
158 | } | 162 | } |