diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-09 17:38:51 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-09 17:38:51 -0500 |
commit | 5ede3ceb7b2c2843e153a1803edbdc8c56655950 (patch) | |
tree | 4cfa82b619f7d39b671e4a2a213f4d040b09c486 /arch/arm/mach-orion5x | |
parent | 6d889d03ab1417645e76e129834f76204bae37c0 (diff) | |
parent | 3e2762c8f1141ae8dc708034ea41d6827818c328 (diff) |
Merge tag 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
New feature development
This adds support for new features, and contains stuff from most
platforms. A number of these patches could have fit into other
branches, too, but were small enough not to cause too much
confusion here.
* tag 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
mfd/db8500-prcmu: remove support for early silicon revisions
ARM: ux500: fix the smp_twd clock calculation
ARM: ux500: remove support for early silicon revisions
ARM: ux500: update register files
ARM: ux500: register DB5500 PMU dynamically
ARM: ux500: update ASIC detection for U5500
ARM: ux500: support DB8520
ARM: picoxcell: implement watchdog restart
ARM: OMAP3+: hwmod data: Add the default clockactivity for I2C
ARM: OMAP3: hwmod data: disable multiblock reads on MMC1/2 on OMAP34xx/35xx <= ES2.1
ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP4
ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP3
ARM: OMAP: hwmod data: Add support for AM35xx UART4/ttyO3
ARM: Orion: Remove address map info from all platform data structures
ARM: Orion: Get address map from plat-orion instead of via platform_data
ARM: Orion: mbus_dram_info consolidation
ARM: Orion: Consolidate the address map setup
ARM: Kirkwood: Add configuration for MPP12 as GPIO
ARM: Kirkwood: Recognize A1 revision of 6282 chip
ARM: ux500: update the MOP500 GPIO assignments
...
Diffstat (limited to 'arch/arm/mach-orion5x')
-rw-r--r-- | arch/arm/mach-orion5x/addr-map.c | 146 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/common.c | 23 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/common.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/orion5x.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/mpp.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/pci.c | 5 |
6 files changed, 59 insertions, 121 deletions
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 5ceafdccc456..3638e5c12b7e 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c | |||
@@ -14,8 +14,8 @@ | |||
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/mbus.h> | 15 | #include <linux/mbus.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/errno.h> | ||
18 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
18 | #include <plat/addr-map.h> | ||
19 | #include "common.h" | 19 | #include "common.h" |
20 | 20 | ||
21 | /* | 21 | /* |
@@ -41,7 +41,6 @@ | |||
41 | /* | 41 | /* |
42 | * Generic Address Decode Windows bit settings | 42 | * Generic Address Decode Windows bit settings |
43 | */ | 43 | */ |
44 | #define TARGET_DDR 0 | ||
45 | #define TARGET_DEV_BUS 1 | 44 | #define TARGET_DEV_BUS 1 |
46 | #define TARGET_PCI 3 | 45 | #define TARGET_PCI 3 |
47 | #define TARGET_PCIE 4 | 46 | #define TARGET_PCIE 4 |
@@ -57,27 +56,10 @@ | |||
57 | #define ATTR_DEV_BOOT 0xf | 56 | #define ATTR_DEV_BOOT 0xf |
58 | #define ATTR_SRAM 0x0 | 57 | #define ATTR_SRAM 0x0 |
59 | 58 | ||
60 | /* | ||
61 | * Helpers to get DDR bank info | ||
62 | */ | ||
63 | #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) | ||
64 | #define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3)) | ||
65 | #define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3)) | ||
66 | |||
67 | /* | ||
68 | * CPU Address Decode Windows registers | ||
69 | */ | ||
70 | #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) | ||
71 | #define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) | ||
72 | #define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) | ||
73 | #define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) | ||
74 | #define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) | ||
75 | |||
76 | |||
77 | struct mbus_dram_target_info orion5x_mbus_dram_info; | ||
78 | static int __initdata win_alloc_count; | 59 | static int __initdata win_alloc_count; |
79 | 60 | ||
80 | static int __init orion5x_cpu_win_can_remap(int win) | 61 | static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, |
62 | const int win) | ||
81 | { | 63 | { |
82 | u32 dev, rev; | 64 | u32 dev, rev; |
83 | 65 | ||
@@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win) | |||
91 | return 0; | 73 | return 0; |
92 | } | 74 | } |
93 | 75 | ||
94 | static int __init setup_cpu_win(int win, u32 base, u32 size, | 76 | /* |
95 | u8 target, u8 attr, int remap) | 77 | * Description of the windows needed by the platform code |
96 | { | 78 | */ |
97 | if (win >= 8) { | 79 | static struct __initdata orion_addr_map_cfg addr_map_cfg = { |
98 | printk(KERN_ERR "setup_cpu_win: trying to allocate " | 80 | .num_wins = 8, |
99 | "window %d\n", win); | 81 | .cpu_win_can_remap = cpu_win_can_remap, |
100 | return -ENOSPC; | 82 | .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, |
101 | } | 83 | }; |
102 | |||
103 | writel(base & 0xffff0000, CPU_WIN_BASE(win)); | ||
104 | writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1, | ||
105 | CPU_WIN_CTRL(win)); | ||
106 | |||
107 | if (orion5x_cpu_win_can_remap(win)) { | ||
108 | if (remap < 0) | ||
109 | remap = base; | ||
110 | |||
111 | writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); | ||
112 | writel(0, CPU_WIN_REMAP_HI(win)); | ||
113 | } | ||
114 | return 0; | ||
115 | } | ||
116 | |||
117 | void __init orion5x_setup_cpu_mbus_bridge(void) | ||
118 | { | ||
119 | int i; | ||
120 | int cs; | ||
121 | 84 | ||
85 | static const struct __initdata orion_addr_map_info addr_map_info[] = { | ||
122 | /* | 86 | /* |
123 | * First, disable and clear windows. | 87 | * Setup windows for PCI+PCIe IO+MEM space. |
124 | */ | 88 | */ |
125 | for (i = 0; i < 8; i++) { | 89 | { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, |
126 | writel(0, CPU_WIN_BASE(i)); | 90 | TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE |
127 | writel(0, CPU_WIN_CTRL(i)); | 91 | }, |
128 | if (orion5x_cpu_win_can_remap(i)) { | 92 | { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, |
129 | writel(0, CPU_WIN_REMAP_LO(i)); | 93 | TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE |
130 | writel(0, CPU_WIN_REMAP_HI(i)); | 94 | }, |
131 | } | 95 | { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, |
132 | } | 96 | TARGET_PCIE, ATTR_PCIE_MEM, -1 |
97 | }, | ||
98 | { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, | ||
99 | TARGET_PCI, ATTR_PCI_MEM, -1 | ||
100 | }, | ||
101 | /* End marker */ | ||
102 | { -1, 0, 0, 0, 0, 0 } | ||
103 | }; | ||
133 | 104 | ||
105 | void __init orion5x_setup_cpu_mbus_bridge(void) | ||
106 | { | ||
134 | /* | 107 | /* |
135 | * Setup windows for PCI+PCIe IO+MEM space. | 108 | * Disable, clear and configure windows. |
136 | */ | 109 | */ |
137 | setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, | 110 | orion_config_wins(&addr_map_cfg, addr_map_info); |
138 | TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); | ||
139 | setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, | ||
140 | TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); | ||
141 | setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, | ||
142 | TARGET_PCIE, ATTR_PCIE_MEM, -1); | ||
143 | setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, | ||
144 | TARGET_PCI, ATTR_PCI_MEM, -1); | ||
145 | win_alloc_count = 4; | 111 | win_alloc_count = 4; |
146 | 112 | ||
147 | /* | 113 | /* |
148 | * Setup MBUS dram target info. | 114 | * Setup MBUS dram target info. |
149 | */ | 115 | */ |
150 | orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | 116 | orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); |
151 | |||
152 | for (i = 0, cs = 0; i < 4; i++) { | ||
153 | u32 base = readl(DDR_BASE_CS(i)); | ||
154 | u32 size = readl(DDR_SIZE_CS(i)); | ||
155 | |||
156 | /* | ||
157 | * Chip select enabled? | ||
158 | */ | ||
159 | if (size & 1) { | ||
160 | struct mbus_dram_window *w; | ||
161 | |||
162 | w = &orion5x_mbus_dram_info.cs[cs++]; | ||
163 | w->cs_index = i; | ||
164 | w->mbus_attr = 0xf & ~(1 << i); | ||
165 | w->base = base & 0xffff0000; | ||
166 | w->size = (size | 0x0000ffff) + 1; | ||
167 | } | ||
168 | } | ||
169 | orion5x_mbus_dram_info.num_cs = cs; | ||
170 | } | 117 | } |
171 | 118 | ||
172 | void __init orion5x_setup_dev_boot_win(u32 base, u32 size) | 119 | void __init orion5x_setup_dev_boot_win(u32 base, u32 size) |
173 | { | 120 | { |
174 | setup_cpu_win(win_alloc_count++, base, size, | 121 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, |
175 | TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); | 122 | TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); |
176 | } | 123 | } |
177 | 124 | ||
178 | void __init orion5x_setup_dev0_win(u32 base, u32 size) | 125 | void __init orion5x_setup_dev0_win(u32 base, u32 size) |
179 | { | 126 | { |
180 | setup_cpu_win(win_alloc_count++, base, size, | 127 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, |
181 | TARGET_DEV_BUS, ATTR_DEV_CS0, -1); | 128 | TARGET_DEV_BUS, ATTR_DEV_CS0, -1); |
182 | } | 129 | } |
183 | 130 | ||
184 | void __init orion5x_setup_dev1_win(u32 base, u32 size) | 131 | void __init orion5x_setup_dev1_win(u32 base, u32 size) |
185 | { | 132 | { |
186 | setup_cpu_win(win_alloc_count++, base, size, | 133 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, |
187 | TARGET_DEV_BUS, ATTR_DEV_CS1, -1); | 134 | TARGET_DEV_BUS, ATTR_DEV_CS1, -1); |
188 | } | 135 | } |
189 | 136 | ||
190 | void __init orion5x_setup_dev2_win(u32 base, u32 size) | 137 | void __init orion5x_setup_dev2_win(u32 base, u32 size) |
191 | { | 138 | { |
192 | setup_cpu_win(win_alloc_count++, base, size, | 139 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, |
193 | TARGET_DEV_BUS, ATTR_DEV_CS2, -1); | 140 | TARGET_DEV_BUS, ATTR_DEV_CS2, -1); |
194 | } | 141 | } |
195 | 142 | ||
196 | void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) | 143 | void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) |
197 | { | 144 | { |
198 | setup_cpu_win(win_alloc_count++, base, size, | 145 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, |
199 | TARGET_PCIE, ATTR_PCIE_WA, -1); | 146 | TARGET_PCIE, ATTR_PCIE_WA, -1); |
200 | } | 147 | } |
201 | 148 | ||
202 | int __init orion5x_setup_sram_win(void) | 149 | void __init orion5x_setup_sram_win(void) |
203 | { | 150 | { |
204 | return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, | 151 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, |
205 | ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); | 152 | ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, |
153 | TARGET_SRAM, ATTR_SRAM, -1); | ||
206 | } | 154 | } |
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 41127e80cc1e..0e28bae20bd4 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
16 | #include <linux/dma-mapping.h> | 16 | #include <linux/dma-mapping.h> |
17 | #include <linux/serial_8250.h> | 17 | #include <linux/serial_8250.h> |
18 | #include <linux/mbus.h> | ||
19 | #include <linux/mv643xx_i2c.h> | 18 | #include <linux/mv643xx_i2c.h> |
20 | #include <linux/ata_platform.h> | 19 | #include <linux/ata_platform.h> |
21 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
@@ -32,6 +31,7 @@ | |||
32 | #include <plat/orion_nand.h> | 31 | #include <plat/orion_nand.h> |
33 | #include <plat/time.h> | 32 | #include <plat/time.h> |
34 | #include <plat/common.h> | 33 | #include <plat/common.h> |
34 | #include <plat/addr-map.h> | ||
35 | #include "common.h" | 35 | #include "common.h" |
36 | 36 | ||
37 | /***************************************************************************** | 37 | /***************************************************************************** |
@@ -72,8 +72,7 @@ void __init orion5x_map_io(void) | |||
72 | ****************************************************************************/ | 72 | ****************************************************************************/ |
73 | void __init orion5x_ehci0_init(void) | 73 | void __init orion5x_ehci0_init(void) |
74 | { | 74 | { |
75 | orion_ehci_init(&orion5x_mbus_dram_info, | 75 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); |
76 | ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); | ||
77 | } | 76 | } |
78 | 77 | ||
79 | 78 | ||
@@ -82,8 +81,7 @@ void __init orion5x_ehci0_init(void) | |||
82 | ****************************************************************************/ | 81 | ****************************************************************************/ |
83 | void __init orion5x_ehci1_init(void) | 82 | void __init orion5x_ehci1_init(void) |
84 | { | 83 | { |
85 | orion_ehci_1_init(&orion5x_mbus_dram_info, | 84 | orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); |
86 | ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); | ||
87 | } | 85 | } |
88 | 86 | ||
89 | 87 | ||
@@ -92,7 +90,7 @@ void __init orion5x_ehci1_init(void) | |||
92 | ****************************************************************************/ | 90 | ****************************************************************************/ |
93 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) | 91 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
94 | { | 92 | { |
95 | orion_ge00_init(eth_data, &orion5x_mbus_dram_info, | 93 | orion_ge00_init(eth_data, |
96 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, | 94 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, |
97 | IRQ_ORION5X_ETH_ERR, orion5x_tclk); | 95 | IRQ_ORION5X_ETH_ERR, orion5x_tclk); |
98 | } | 96 | } |
@@ -122,8 +120,7 @@ void __init orion5x_i2c_init(void) | |||
122 | ****************************************************************************/ | 120 | ****************************************************************************/ |
123 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) | 121 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
124 | { | 122 | { |
125 | orion_sata_init(sata_data, &orion5x_mbus_dram_info, | 123 | orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); |
126 | ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); | ||
127 | } | 124 | } |
128 | 125 | ||
129 | 126 | ||
@@ -159,8 +156,7 @@ void __init orion5x_uart1_init(void) | |||
159 | ****************************************************************************/ | 156 | ****************************************************************************/ |
160 | void __init orion5x_xor_init(void) | 157 | void __init orion5x_xor_init(void) |
161 | { | 158 | { |
162 | orion_xor0_init(&orion5x_mbus_dram_info, | 159 | orion_xor0_init(ORION5X_XOR_PHYS_BASE, |
163 | ORION5X_XOR_PHYS_BASE, | ||
164 | ORION5X_XOR_PHYS_BASE + 0x200, | 160 | ORION5X_XOR_PHYS_BASE + 0x200, |
165 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); | 161 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); |
166 | } | 162 | } |
@@ -170,12 +166,7 @@ void __init orion5x_xor_init(void) | |||
170 | ****************************************************************************/ | 166 | ****************************************************************************/ |
171 | static void __init orion5x_crypto_init(void) | 167 | static void __init orion5x_crypto_init(void) |
172 | { | 168 | { |
173 | int ret; | 169 | orion5x_setup_sram_win(); |
174 | |||
175 | ret = orion5x_setup_sram_win(); | ||
176 | if (ret) | ||
177 | return; | ||
178 | |||
179 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, | 170 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
180 | SZ_8K, IRQ_ORION5X_CESA); | 171 | SZ_8K, IRQ_ORION5X_CESA); |
181 | } | 172 | } |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 37ef18de61b7..d2513ac79ff5 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h | |||
@@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer; | |||
20 | * functions to map its interfaces and by the machine-setup to map its on- | 20 | * functions to map its interfaces and by the machine-setup to map its on- |
21 | * board devices. Details in /mach-orion/addr-map.c | 21 | * board devices. Details in /mach-orion/addr-map.c |
22 | */ | 22 | */ |
23 | extern struct mbus_dram_target_info orion5x_mbus_dram_info; | ||
24 | void orion5x_setup_cpu_mbus_bridge(void); | 23 | void orion5x_setup_cpu_mbus_bridge(void); |
25 | void orion5x_setup_dev_boot_win(u32 base, u32 size); | 24 | void orion5x_setup_dev_boot_win(u32 base, u32 size); |
26 | void orion5x_setup_dev0_win(u32 base, u32 size); | 25 | void orion5x_setup_dev0_win(u32 base, u32 size); |
27 | void orion5x_setup_dev1_win(u32 base, u32 size); | 26 | void orion5x_setup_dev1_win(u32 base, u32 size); |
28 | void orion5x_setup_dev2_win(u32 base, u32 size); | 27 | void orion5x_setup_dev2_win(u32 base, u32 size); |
29 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); | 28 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); |
30 | int orion5x_setup_sram_win(void); | 29 | void orion5x_setup_sram_win(void); |
31 | 30 | ||
32 | void orion5x_ehci0_init(void); | 31 | void orion5x_ehci0_init(void); |
33 | void orion5x_ehci1_init(void); | 32 | void orion5x_ehci1_init(void); |
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 0a28bbc76891..2745f5d95b3f 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h | |||
@@ -69,7 +69,7 @@ | |||
69 | ******************************************************************************/ | 69 | ******************************************************************************/ |
70 | 70 | ||
71 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) | 71 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) |
72 | 72 | #define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) | |
73 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) | 73 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) |
74 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) | 74 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) |
75 | #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) | 75 | #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) |
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index b6ddd7a5db6a..5b70026f478c 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c | |||
@@ -10,7 +10,6 @@ | |||
10 | 10 | ||
11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/mbus.h> | ||
14 | #include <linux/io.h> | 13 | #include <linux/io.h> |
15 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
16 | #include <plat/mpp.h> | 15 | #include <plat/mpp.h> |
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index bc4a920e26ee..a494c470e3e4 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <asm/irq.h> | 18 | #include <asm/irq.h> |
19 | #include <asm/mach/pci.h> | 19 | #include <asm/mach/pci.h> |
20 | #include <plat/pcie.h> | 20 | #include <plat/pcie.h> |
21 | #include <plat/addr-map.h> | ||
21 | #include "common.h" | 22 | #include "common.h" |
22 | 23 | ||
23 | /***************************************************************************** | 24 | /***************************************************************************** |
@@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
145 | /* | 146 | /* |
146 | * Generic PCIe unit setup. | 147 | * Generic PCIe unit setup. |
147 | */ | 148 | */ |
148 | orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); | 149 | orion_pcie_setup(PCIE_BASE); |
149 | 150 | ||
150 | /* | 151 | /* |
151 | * Check whether to apply Orion-1/Orion-NAS PCIe config | 152 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
@@ -477,7 +478,7 @@ static int __init pci_setup(struct pci_sys_data *sys) | |||
477 | /* | 478 | /* |
478 | * Point PCI unit MBUS decode windows to DRAM space. | 479 | * Point PCI unit MBUS decode windows to DRAM space. |
479 | */ | 480 | */ |
480 | orion5x_setup_pci_wins(&orion5x_mbus_dram_info); | 481 | orion5x_setup_pci_wins(&orion_mbus_dram_info); |
481 | 482 | ||
482 | /* | 483 | /* |
483 | * Master + Slave enable | 484 | * Master + Slave enable |