ARM: Orion: Consolidate the address map setup

Compile tested on Dove, orion5x, mv78xx0. Boot tested on Kirkwood.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Michael Walle <michael@walle.cc>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>

4 files changed, 51 insertions, 106 deletions

diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 5ceafdccc456..73ceb49de894 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -14,8 +14,8 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
-#include <linux/errno.h>
 #include <mach/hardware.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
@@ -41,7 +41,6 @@
 /*
  * Generic Address Decode Windows bit settings
  */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_PCI              3
 #define TARGET_PCIE             4
@@ -57,27 +56,11 @@
 #define ATTR_DEV_BOOT           0xf
 #define ATTR_SRAM               0x0
 
-/*
- * Helpers to get DDR bank info
- */
-#define ORION5X_DDR_REG(x)      (ORION5X_DDR_VIRT_BASE | (x))
-#define DDR_BASE_CS(n)          ORION5X_DDR_REG(0x1500 + ((n) << 3))
-#define DDR_SIZE_CS(n)          ORION5X_DDR_REG(0x1504 + ((n) << 3))
-
-/*
- * CPU Address Decode Windows registers
- */
-#define ORION5X_BRIDGE_REG(x)   (ORION5X_BRIDGE_VIRT_BASE | (x))
-#define CPU_WIN_CTRL(n)         ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n)         ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n)     ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n)     ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
-
-
 struct mbus_dram_target_info orion5x_mbus_dram_info;
 static int __initdata win_alloc_count;
 
-static int __init orion5x_cpu_win_can_remap(int win)
+static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
+                  const int win)
 {
         u32 dev, rev;
 
@@ -91,116 +74,83 @@ static int __init orion5x_cpu_win_can_remap(int win)
         return 0;
 }
 
-static int __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        if (win >= 8) {
-                printk(KERN_ERR "setup_cpu_win: trying to allocate "
-                                "window %d\n", win);
-                return -ENOSPC;
-        }
-
-        writel(base & 0xffff0000, CPU_WIN_BASE(win));
-        writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
-                CPU_WIN_CTRL(win));
-
-        if (orion5x_cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-
-                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
-                writel(0, CPU_WIN_REMAP_HI(win));
-        }
-        return 0;
-}
-
-void __init orion5x_setup_cpu_mbus_bridge(void)
-{
-        int i;
-        int cs;
+/*
+ * Description of the windows needed by the platform code
+ */
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 8,
+        .cpu_win_can_remap = cpu_win_can_remap,
+        .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
+};
 
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
         /*
-         * First, disable and clear windows.
+         * Setup windows for PCI+PCIe IO+MEM space.
          */
-        for (i = 0; i < 8; i++) {
-                writel(0, CPU_WIN_BASE(i));
-                writel(0, CPU_WIN_CTRL(i));
-                if (orion5x_cpu_win_can_remap(i)) {
-                        writel(0, CPU_WIN_REMAP_LO(i));
-                        writel(0, CPU_WIN_REMAP_HI(i));
-                }
-        }
+        { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
+          TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
+        },
+        { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
+          TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
+        },
+        { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
+          TARGET_PCIE, ATTR_PCIE_MEM, -1
+        },
+        { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
+          TARGET_PCI, ATTR_PCI_MEM, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
 
+void __init orion5x_setup_cpu_mbus_bridge(void)
+{
         /*
-         * Setup windows for PCI+PCIe IO+MEM space.
+         * Disable, clear and configure windows.
          */
-        setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
-                TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
-        setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
-                TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
-        setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
-                TARGET_PCIE, ATTR_PCIE_MEM, -1);
-        setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
-                TARGET_PCI, ATTR_PCI_MEM, -1);
+        orion_config_wins(&addr_map_cfg, addr_map_info);
         win_alloc_count = 4;
 
         /*
          * Setup MBUS dram target info.
          */
-        orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(DDR_BASE_CS(i));
-                u32 size = readl(DDR_SIZE_CS(i));
-
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-
-                        w = &orion5x_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        orion5x_mbus_dram_info.num_cs = cs;
+        orion_setup_cpu_mbus_target(&addr_map_cfg, &orion5x_mbus_dram_info,
+                                    ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 }
 
 void __init orion5x_setup_dev0_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 }
 
 void __init orion5x_setup_dev1_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 }
 
 void __init orion5x_setup_dev2_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 }
 
 void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_PCIE, ATTR_PCIE_WA, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
 
-int __init orion5x_setup_sram_win(void)
+void __init orion5x_setup_sram_win(void)
 {
-        return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE,
-                        ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
+                            ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
+                            TARGET_SRAM, ATTR_SRAM, -1);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 22ace0bf2f92..47ca0ee44a6a 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -169,12 +169,7 @@ void __init orion5x_xor_init(void)
  ****************************************************************************/
 static void __init orion5x_crypto_init(void)
 {
-        int ret;
-
-        ret = orion5x_setup_sram_win();
-        if (ret)
-                return;
-
+        orion5x_setup_sram_win();
         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
                           SZ_8K, IRQ_ORION5X_CESA);
 }
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 909489f4d23e..465e8a458bfb 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -27,7 +27,7 @@ void orion5x_setup_dev0_win(u32 base, u32 size);
 void orion5x_setup_dev1_win(u32 base, u32 size);
 void orion5x_setup_dev2_win(u32 base, u32 size);
 void orion5x_setup_pcie_wa_win(u32 base, u32 size);
-int orion5x_setup_sram_win(void);
+void orion5x_setup_sram_win(void);
 
 void orion5x_ehci0_init(void);
 void orion5x_ehci1_init(void);
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 0a28bbc76891..2745f5d95b3f 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -69,7 +69,7 @@
  ******************************************************************************/
 
 #define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
-
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))