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authorSylver Bruneau <sylver.bruneau@googlemail.com>2008-04-25 20:35:29 -0400
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 16:44:50 -0400
commit47e9cffde663eafd5f78987036429fc0994d90e8 (patch)
tree2200ed5b306d2e8989b097745315c0767ad979c7 /arch/arm/mach-orion5x/ts409-setup.c
parenta0087f2fcf5cb4e16502f5334168fbe304af318b (diff)
[ARM] Orion: add QNAP TS-409 support
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion5x/ts409-setup.c')
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c385
1 files changed, 385 insertions, 0 deletions
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
new file mode 100644
index 000000000000..524e4249f082
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -0,0 +1,385 @@
1/*
2 * QNAP TS-409 Board Setup
3 *
4 * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/irq.h>
17#include <linux/mtd/physmap.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/gpio_keys.h>
20#include <linux/input.h>
21#include <linux/i2c.h>
22#include <linux/serial_reg.h>
23#include <asm/mach-types.h>
24#include <asm/gpio.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/orion5x.h>
28#include "common.h"
29#include "mpp.h"
30
31/*****************************************************************************
32 * QNAP TS-409 Info
33 ****************************************************************************/
34
35/*
36 * QNAP TS-409 hardware :
37 * - Marvell 88F5281-D0
38 * - Marvell 88SX7042 SATA controller (PCIe)
39 * - Marvell 88E1118 Gigabit Ethernet PHY
40 * - RTC S35390A (@0x30) on I2C bus
41 * - 8MB NOR flash
42 * - 256MB of DDR-2 RAM
43 */
44
45/*
46 * 8MB NOR flash Device bus boot chip select
47 */
48
49#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
50#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
51
52/****************************************************************************
53 * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
54 * partitions on the device because we want to keep compatability with
55 * existing QNAP firmware.
56 *
57 * Layout as used by QNAP:
58 * [2] 0x00000000-0x00200000 : "Kernel"
59 * [3] 0x00200000-0x00600000 : "RootFS1"
60 * [4] 0x00600000-0x00700000 : "RootFS2"
61 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
62 * [5] 0x00760000-0x00780000 : "U-Boot Config"
63 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
64 ***************************************************************************/
65static struct mtd_partition qnap_ts409_partitions[] = {
66 {
67 .name = "U-Boot",
68 .size = 0x00080000,
69 .offset = 0x00780000,
70 .mask_flags = MTD_WRITEABLE,
71 }, {
72 .name = "Kernel",
73 .size = 0x00200000,
74 .offset = 0,
75 }, {
76 .name = "RootFS1",
77 .size = 0x00400000,
78 .offset = 0x00200000,
79 }, {
80 .name = "RootFS2",
81 .size = 0x00100000,
82 .offset = 0x00600000,
83 }, {
84 .name = "U-Boot Config",
85 .size = 0x00020000,
86 .offset = 0x00760000,
87 }, {
88 .name = "NAS Config",
89 .size = 0x00060000,
90 .offset = 0x00700000,
91 .mask_flags = MTD_WRITEABLE,
92 },
93};
94
95static struct physmap_flash_data qnap_ts409_nor_flash_data = {
96 .width = 1,
97 .parts = qnap_ts409_partitions,
98 .nr_parts = ARRAY_SIZE(qnap_ts409_partitions)
99};
100
101static struct resource qnap_ts409_nor_flash_resource = {
102 .flags = IORESOURCE_MEM,
103 .start = QNAP_TS409_NOR_BOOT_BASE,
104 .end = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
105};
106
107static struct platform_device qnap_ts409_nor_flash = {
108 .name = "physmap-flash",
109 .id = 0,
110 .dev = { .platform_data = &qnap_ts409_nor_flash_data, },
111 .num_resources = 1,
112 .resource = &qnap_ts409_nor_flash_resource,
113};
114
115/*****************************************************************************
116 * PCI
117 ****************************************************************************/
118
119static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
120{
121 int irq;
122
123 /*
124 * Check for devices with hard-wired IRQs.
125 */
126 irq = orion5x_pci_map_irq(dev, slot, pin);
127 if (irq != -1)
128 return irq;
129
130 /*
131 * PCI isn't used on the TS-409
132 */
133 return -1;
134}
135
136static struct hw_pci qnap_ts409_pci __initdata = {
137 .nr_controllers = 2,
138 .swizzle = pci_std_swizzle,
139 .setup = orion5x_pci_sys_setup,
140 .scan = orion5x_pci_sys_scan_bus,
141 .map_irq = qnap_ts409_pci_map_irq,
142};
143
144static int __init qnap_ts409_pci_init(void)
145{
146 if (machine_is_ts409())
147 pci_common_init(&qnap_ts409_pci);
148
149 return 0;
150}
151
152subsys_initcall(qnap_ts409_pci_init);
153
154/*****************************************************************************
155 * Ethernet
156 ****************************************************************************/
157
158static struct mv643xx_eth_platform_data qnap_ts409_eth_data = {
159 .phy_addr = 8,
160};
161
162static int __init parse_hex_nibble(char n)
163{
164 if (n >= '0' && n <= '9')
165 return n - '0';
166
167 if (n >= 'A' && n <= 'F')
168 return n - 'A' + 10;
169
170 if (n >= 'a' && n <= 'f')
171 return n - 'a' + 10;
172
173 return -1;
174}
175
176static int __init parse_hex_byte(const char *b)
177{
178 int hi;
179 int lo;
180
181 hi = parse_hex_nibble(b[0]);
182 lo = parse_hex_nibble(b[1]);
183
184 if (hi < 0 || lo < 0)
185 return -1;
186
187 return (hi << 4) | lo;
188}
189
190static int __init check_mac_addr(const char *addr_str)
191{
192 u_int8_t addr[6];
193 int i;
194
195 for (i = 0; i < 6; i++) {
196 int byte;
197
198 /*
199 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
200 */
201 if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
202 return -1;
203
204 byte = parse_hex_byte(addr_str + (i * 3));
205 if (byte < 0)
206 return -1;
207 addr[i] = byte;
208 }
209
210 printk(KERN_INFO "ts409: found ethernet mac address ");
211 for (i = 0; i < 6; i++)
212 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
213
214 memcpy(qnap_ts409_eth_data.mac_addr, addr, 6);
215
216 return 0;
217}
218
219/*
220 * The 'NAS Config' flash partition has an ext2 filesystem which
221 * contains a file that has the ethernet MAC address in plain text
222 * (format "xx:xx:xx:xx:xx:xx\n").
223 */
224static void __init ts409_find_mac_addr(void)
225{
226 unsigned long addr;
227
228 for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
229 char *nor_page;
230 int ret = 0;
231
232 nor_page = ioremap(QNAP_TS409_NOR_BOOT_BASE + addr, 1024);
233 if (nor_page != NULL) {
234 ret = check_mac_addr(nor_page);
235 iounmap(nor_page);
236 }
237
238 if (ret == 0)
239 break;
240 }
241}
242
243/*****************************************************************************
244 * RTC S35390A on I2C bus
245 ****************************************************************************/
246
247#define TS409_RTC_GPIO 10
248
249static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
250 I2C_BOARD_INFO("s35390a", 0x30),
251};
252
253/****************************************************************************
254 * GPIO Attached Keys
255 * Power button is attached to the PIC microcontroller
256 ****************************************************************************/
257
258#define QNAP_TS409_GPIO_KEY_MEDIA 15
259
260static struct gpio_keys_button qnap_ts409_buttons[] = {
261 {
262 .code = KEY_RESTART,
263 .gpio = QNAP_TS409_GPIO_KEY_MEDIA,
264 .desc = "USB Copy Button",
265 .active_low = 1,
266 },
267};
268
269static struct gpio_keys_platform_data qnap_ts409_button_data = {
270 .buttons = qnap_ts409_buttons,
271 .nbuttons = ARRAY_SIZE(qnap_ts409_buttons),
272};
273
274static struct platform_device qnap_ts409_button_device = {
275 .name = "gpio-keys",
276 .id = -1,
277 .num_resources = 0,
278 .dev = {
279 .platform_data = &qnap_ts409_button_data,
280 },
281};
282
283/*****************************************************************************
284 * General Setup
285 ****************************************************************************/
286static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
287 { 0, MPP_UNUSED },
288 { 1, MPP_UNUSED },
289 { 2, MPP_UNUSED },
290 { 3, MPP_UNUSED },
291 { 4, MPP_GPIO }, /* HDD 1 status */
292 { 5, MPP_GPIO }, /* HDD 2 status */
293 { 6, MPP_GPIO }, /* HDD 3 status */
294 { 7, MPP_GPIO }, /* HDD 4 status */
295 { 8, MPP_UNUSED },
296 { 9, MPP_UNUSED },
297 { 10, MPP_GPIO }, /* RTC int */
298 { 11, MPP_UNUSED },
299 { 12, MPP_UNUSED },
300 { 13, MPP_UNUSED },
301 { 14, MPP_GPIO }, /* SW_RST */
302 { 15, MPP_GPIO }, /* USB copy button */
303 { 16, MPP_UART }, /* UART1 RXD */
304 { 17, MPP_UART }, /* UART1 TXD */
305 { 18, MPP_UNUSED },
306 { 19, MPP_UNUSED },
307 { -1 },
308};
309
310/*
311 * QNAP TS-409 specific power off method via UART1-attached PIC
312 */
313
314#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
315
316static void qnap_ts409_power_off(void)
317{
318 /* 19200 baud divisor */
319 const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
320
321 pr_info("%s: triggering power-off...\n", __func__);
322
323 /* hijack uart1 and reset into sane state (19200,8n1) */
324 writel(0x83, UART1_REG(LCR));
325 writel(divisor & 0xff, UART1_REG(DLL));
326 writel((divisor >> 8) & 0xff, UART1_REG(DLM));
327 writel(0x03, UART1_REG(LCR));
328 writel(0x00, UART1_REG(IER));
329 writel(0x00, UART1_REG(FCR));
330 writel(0x00, UART1_REG(MCR));
331
332 /* send the power-off command 'A' to PIC */
333 writel('A', UART1_REG(TX));
334}
335
336static void __init qnap_ts409_init(void)
337{
338 /*
339 * Setup basic Orion functions. Need to be called early.
340 */
341 orion5x_init();
342
343 orion5x_mpp_conf(ts409_mpp_modes);
344
345 /*
346 * Configure peripherals.
347 */
348 orion5x_ehci0_init();
349 ts409_find_mac_addr();
350 orion5x_eth_init(&qnap_ts409_eth_data);
351 orion5x_i2c_init();
352 orion5x_uart0_init();
353
354 orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
355 QNAP_TS409_NOR_BOOT_SIZE);
356 platform_device_register(&qnap_ts409_nor_flash);
357
358 platform_device_register(&qnap_ts409_button_device);
359
360 /* Get RTC IRQ and register the chip */
361 if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
362 if (gpio_direction_input(TS409_RTC_GPIO) == 0)
363 qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
364 else
365 gpio_free(TS409_RTC_GPIO);
366 }
367 if (qnap_ts409_i2c_rtc.irq == 0)
368 pr_warning("qnap_ts409_init: failed to get RTC IRQ\n");
369 i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
370
371 /* register ts409 specific power-off method */
372 pm_power_off = qnap_ts409_power_off;
373}
374
375MACHINE_START(TS409, "QNAP TS-409")
376 /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */
377 .phys_io = ORION5X_REGS_PHYS_BASE,
378 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
379 .boot_params = 0x00000100,
380 .init_machine = qnap_ts409_init,
381 .map_io = orion5x_map_io,
382 .init_irq = orion5x_init_irq,
383 .timer = &orion5x_timer,
384 .fixup = tag_fixup_mem32,
385MACHINE_END