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authorLennert Buytenhek <buytenh@wantstofly.org>2008-06-30 14:25:24 -0400
committerNicolas Pitre <nico@cam.org>2008-07-07 18:38:24 -0400
commit70129132322cdbb6683ab9e90419cd5a6f8294d3 (patch)
treec4b61fb3ea0fa087f8d1fe9cab994fbaf8af2735 /arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
parent2f8209788d774c66efb5e2991affc06b1d1c7314 (diff)
[ARM] Orion: add RD88F5181L-GE support
This patch adds support for the Marvell Orion-VoIP RD2-88F5181L-GE Reference Design, and enables use of the ethernet, USB, Cardbus and mini-PCIe ports. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion5x/rd88f5181l-ge-setup.c')
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-ge-setup.c172
1 files changed, 172 insertions, 0 deletions
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
new file mode 100644
index 000000000000..b56447d32e17
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -0,0 +1,172 @@
1/*
2 * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
3 *
4 * Marvell Orion-VoIP GE Reference Design Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mv643xx_eth.h>
18#include <linux/i2c.h>
19#include <asm/mach-types.h>
20#include <asm/gpio.h>
21#include <asm/leds.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/pci.h>
24#include <asm/arch/orion5x.h>
25#include "common.h"
26#include "mpp.h"
27
28/*****************************************************************************
29 * RD-88F5181L GE Info
30 ****************************************************************************/
31/*
32 * 16M NOR flash Device bus boot chip select
33 */
34#define RD88F5181L_GE_NOR_BOOT_BASE 0xff000000
35#define RD88F5181L_GE_NOR_BOOT_SIZE SZ_16M
36
37
38/*****************************************************************************
39 * 16M NOR Flash on Device bus Boot chip select
40 ****************************************************************************/
41static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
42 .width = 1,
43};
44
45static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
46 .flags = IORESOURCE_MEM,
47 .start = RD88F5181L_GE_NOR_BOOT_BASE,
48 .end = RD88F5181L_GE_NOR_BOOT_BASE +
49 RD88F5181L_GE_NOR_BOOT_SIZE - 1,
50};
51
52static struct platform_device rd88f5181l_ge_nor_boot_flash = {
53 .name = "physmap-flash",
54 .id = 0,
55 .dev = {
56 .platform_data = &rd88f5181l_ge_nor_boot_flash_data,
57 },
58 .num_resources = 1,
59 .resource = &rd88f5181l_ge_nor_boot_flash_resource,
60};
61
62
63/*****************************************************************************
64 * General Setup
65 ****************************************************************************/
66static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
67 { 0, MPP_GPIO }, /* LED1 */
68 { 1, MPP_GPIO }, /* LED5 */
69 { 2, MPP_GPIO }, /* LED4 */
70 { 3, MPP_GPIO }, /* LED3 */
71 { 4, MPP_GPIO }, /* PCI_intA */
72 { 5, MPP_GPIO }, /* RTC interrupt */
73 { 6, MPP_PCI_CLK }, /* CPU PCI refclk */
74 { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
75 { 8, MPP_GPIO }, /* 88e6131 interrupt */
76 { 9, MPP_GPIO }, /* GE_RXERR */
77 { 10, MPP_GPIO }, /* PCI_intB */
78 { 11, MPP_GPIO }, /* LED2 */
79 { 12, MPP_GIGE }, /* GE_TXD[4] */
80 { 13, MPP_GIGE }, /* GE_TXD[5] */
81 { 14, MPP_GIGE }, /* GE_TXD[6] */
82 { 15, MPP_GIGE }, /* GE_TXD[7] */
83 { 16, MPP_GIGE }, /* GE_RXD[4] */
84 { 17, MPP_GIGE }, /* GE_RXD[5] */
85 { 18, MPP_GIGE }, /* GE_RXD[6] */
86 { 19, MPP_GIGE }, /* GE_RXD[7] */
87 { -1 },
88};
89
90static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
91 .phy_addr = -1,
92};
93
94static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
95 I2C_BOARD_INFO("ds1338", 0x68),
96};
97
98static void __init rd88f5181l_ge_init(void)
99{
100 /*
101 * Setup basic Orion functions. Need to be called early.
102 */
103 orion5x_init();
104
105 orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
106
107 /*
108 * Configure peripherals.
109 */
110 orion5x_ehci0_init();
111 orion5x_eth_init(&rd88f5181l_ge_eth_data);
112 orion5x_i2c_init();
113 orion5x_uart0_init();
114
115 orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
116 RD88F5181L_GE_NOR_BOOT_SIZE);
117 platform_device_register(&rd88f5181l_ge_nor_boot_flash);
118
119 i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
120}
121
122static int __init
123rd88f5181l_ge_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
124{
125 int irq;
126
127 /*
128 * Check for devices with hard-wired IRQs.
129 */
130 irq = orion5x_pci_map_irq(dev, slot, pin);
131 if (irq != -1)
132 return irq;
133
134 /*
135 * Cardbus slot.
136 */
137 if (pin == 1)
138 return gpio_to_irq(4);
139 else
140 return gpio_to_irq(10);
141}
142
143static struct hw_pci rd88f5181l_ge_pci __initdata = {
144 .nr_controllers = 2,
145 .swizzle = pci_std_swizzle,
146 .setup = orion5x_pci_sys_setup,
147 .scan = orion5x_pci_sys_scan_bus,
148 .map_irq = rd88f5181l_ge_pci_map_irq,
149};
150
151static int __init rd88f5181l_ge_pci_init(void)
152{
153 if (machine_is_rd88f5181l_ge()) {
154 orion5x_pci_set_cardbus_mode();
155 pci_common_init(&rd88f5181l_ge_pci);
156 }
157
158 return 0;
159}
160subsys_initcall(rd88f5181l_ge_pci_init);
161
162MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
163 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
164 .phys_io = ORION5X_REGS_PHYS_BASE,
165 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
166 .boot_params = 0x00000100,
167 .init_machine = rd88f5181l_ge_init,
168 .map_io = orion5x_map_io,
169 .init_irq = orion5x_init_irq,
170 .timer = &orion5x_timer,
171 .fixup = tag_fixup_mem32,
172MACHINE_END