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authorLennert Buytenhek <buytenh@wantstofly.org>2008-03-27 14:51:40 -0400
committerNicolas Pitre <nico@marvell.com>2008-03-27 14:51:40 -0400
commit98f79d1ea0459b907f95846bad5e967a06b7a0d5 (patch)
tree2a9148e04a36f7cfdf1be90874b7b5eb84e7cf6e /arch/arm/mach-orion/dns323-setup.c
parent5d4294c524fc53746b5ec138d2e90f9d34d754b0 (diff)
Orion: revamp cpu mbus window handling
Instead of forcing all device bus window setup through one function with some enum as the first argument, create separate window setup functions for each of the four possible targets, and do the demux internally. This allows getting rid of the window identifier enum and the big switch statement in orion_setup_cpu_win(). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion/dns323-setup.c')
-rw-r--r--arch/arm/mach-orion/dns323-setup.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c
index 38593784d76f..88991f764794 100644
--- a/arch/arm/mach-orion/dns323-setup.c
+++ b/arch/arm/mach-orion/dns323-setup.c
@@ -251,16 +251,13 @@ static void __init dns323_init(void)
251 /* setup flash mapping 251 /* setup flash mapping
252 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 252 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
253 */ 253 */
254 orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, 254 orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
255 DNS323_NOR_BOOT_SIZE, -1);
256 255
257 /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE 256 /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
258 * 257 *
259 * Open a special address decode windows for the PCIE WA. 258 * Open a special address decode windows for the PCIE WA.
260 */ 259 */
261 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 260 orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE);
262 orion_write(ORION_REGS_VIRT_BASE | 0x20070,
263 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
264 261
265 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ 262 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
266 orion_write(MPP_0_7_CTRL, 0); 263 orion_write(MPP_0_7_CTRL, 0);