aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-orion/addr-map.c
diff options
context:
space:
mode:
authorLennert Buytenhek <buytenh@wantstofly.org>2008-03-27 14:51:40 -0400
committerNicolas Pitre <nico@marvell.com>2008-03-27 14:51:40 -0400
commit98f79d1ea0459b907f95846bad5e967a06b7a0d5 (patch)
tree2a9148e04a36f7cfdf1be90874b7b5eb84e7cf6e /arch/arm/mach-orion/addr-map.c
parent5d4294c524fc53746b5ec138d2e90f9d34d754b0 (diff)
Orion: revamp cpu mbus window handling
Instead of forcing all device bus window setup through one function with some enum as the first argument, create separate window setup functions for each of the four possible targets, and do the demux internally. This allows getting rid of the window identifier enum and the big switch statement in orion_setup_cpu_win(). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion/addr-map.c')
-rw-r--r--arch/arm/mach-orion/addr-map.c144
1 files changed, 50 insertions, 94 deletions
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
index 3de5de9ac656..ca641db6214d 100644
--- a/arch/arm/mach-orion/addr-map.c
+++ b/arch/arm/mach-orion/addr-map.c
@@ -25,10 +25,10 @@
25 * CPU address decoding -- 25 * CPU address decoding --
26 * Linux assumes that it is the boot loader that already setup the access to 26 * Linux assumes that it is the boot loader that already setup the access to
27 * DDR and internal registers. 27 * DDR and internal registers.
28 * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. 28 * Setup access to PCI and PCI-E IO/MEM space is issued by this file.
29 * Setup access to various devices located on the device bus interface (e.g. 29 * Setup access to various devices located on the device bus interface (e.g.
30 * flashes, RTC, etc) should be issued by machine-setup.c according to 30 * flashes, RTC, etc) should be issued by machine-setup.c according to
31 * specific board population (by using orion_setup_cpu_win()). 31 * specific board population (by using orion_setup_*_win()).
32 * 32 *
33 * Non-CPU Masters address decoding -- 33 * Non-CPU Masters address decoding --
34 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR 34 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
@@ -53,6 +53,7 @@
53 ((n) == 3) ? 0x7 : 0xf) 53 ((n) == 3) ? 0x7 : 0xf)
54#define ATTR_PCIE_MEM 0x59 54#define ATTR_PCIE_MEM 0x59
55#define ATTR_PCIE_IO 0x51 55#define ATTR_PCIE_IO 0x51
56#define ATTR_PCIE_WA 0x79
56#define ATTR_PCI_MEM 0x59 57#define ATTR_PCI_MEM 0x59
57#define ATTR_PCI_IO 0x51 58#define ATTR_PCI_IO 0x51
58#define ATTR_DEV_CS0 0x1e 59#define ATTR_DEV_CS0 0x1e
@@ -78,19 +79,6 @@
78#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) 79#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4))
79#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) 80#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4))
80#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) 81#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4))
81#define CPU_MAX_WIN 8
82
83/*
84 * Use this CPU address decode windows allocation
85 */
86#define CPU_WIN_PCIE_IO 0
87#define CPU_WIN_PCI_IO 1
88#define CPU_WIN_PCIE_MEM 2
89#define CPU_WIN_PCI_MEM 3
90#define CPU_WIN_DEV_BOOT 4
91#define CPU_WIN_DEV_CS0 5
92#define CPU_WIN_DEV_CS1 6
93#define CPU_WIN_DEV_CS2 7
94 82
95/* 83/*
96 * Gigabit Ethernet Address Decode Windows registers 84 * Gigabit Ethernet Address Decode Windows registers
@@ -106,7 +94,7 @@
106 94
107struct mbus_dram_target_info orion_mbus_dram_info; 95struct mbus_dram_target_info orion_mbus_dram_info;
108 96
109static int __init orion_cpu_win_can_remap(u32 win) 97static int __init orion_cpu_win_can_remap(int win)
110{ 98{
111 u32 dev, rev; 99 u32 dev, rev;
112 100
@@ -119,88 +107,31 @@ static int __init orion_cpu_win_can_remap(u32 win)
119 return 0; 107 return 0;
120} 108}
121 109
122void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) 110static void __init setup_cpu_win(int win, u32 base, u32 size,
111 u8 target, u8 attr, int remap)
123{ 112{
124 u32 win, attr, ctrl; 113 orion_write(CPU_WIN_BASE(win), base & 0xffff0000);
125 114 orion_write(CPU_WIN_CTRL(win),
126 switch (target) { 115 ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
127 case ORION_PCIE_IO:
128 target = TARGET_PCIE;
129 attr = ATTR_PCIE_IO;
130 win = CPU_WIN_PCIE_IO;
131 break;
132 case ORION_PCI_IO:
133 target = TARGET_PCI;
134 attr = ATTR_PCI_IO;
135 win = CPU_WIN_PCI_IO;
136 break;
137 case ORION_PCIE_MEM:
138 target = TARGET_PCIE;
139 attr = ATTR_PCIE_MEM;
140 win = CPU_WIN_PCIE_MEM;
141 break;
142 case ORION_PCI_MEM:
143 target = TARGET_PCI;
144 attr = ATTR_PCI_MEM;
145 win = CPU_WIN_PCI_MEM;
146 break;
147 case ORION_DEV_BOOT:
148 target = TARGET_DEV_BUS;
149 attr = ATTR_DEV_BOOT;
150 win = CPU_WIN_DEV_BOOT;
151 break;
152 case ORION_DEV0:
153 target = TARGET_DEV_BUS;
154 attr = ATTR_DEV_CS0;
155 win = CPU_WIN_DEV_CS0;
156 break;
157 case ORION_DEV1:
158 target = TARGET_DEV_BUS;
159 attr = ATTR_DEV_CS1;
160 win = CPU_WIN_DEV_CS1;
161 break;
162 case ORION_DEV2:
163 target = TARGET_DEV_BUS;
164 attr = ATTR_DEV_CS2;
165 win = CPU_WIN_DEV_CS2;
166 break;
167 case ORION_DDR:
168 case ORION_REGS:
169 /*
170 * Must be mapped by bootloader.
171 */
172 default:
173 target = attr = win = -1;
174 BUG();
175 }
176
177 base &= 0xffff0000;
178 ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
179 (target << 4) | WIN_EN);
180
181 orion_write(CPU_WIN_BASE(win), base);
182 orion_write(CPU_WIN_CTRL(win), ctrl);
183 116
184 if (orion_cpu_win_can_remap(win)) { 117 if (orion_cpu_win_can_remap(win)) {
185 if (remap >= 0) { 118 if (remap < 0)
186 orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); 119 remap = base;
187 orion_write(CPU_WIN_REMAP_HI(win), 0); 120
188 } else { 121 orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
189 orion_write(CPU_WIN_REMAP_LO(win), base); 122 orion_write(CPU_WIN_REMAP_HI(win), 0);
190 orion_write(CPU_WIN_REMAP_HI(win), 0);
191 }
192 } 123 }
193} 124}
194 125
195void __init orion_setup_cpu_wins(void) 126void __init orion_setup_cpu_mbus_bridge(void)
196{ 127{
197 int i; 128 int i;
198 int cs; 129 int cs;
199 130
200 /* 131 /*
201 * First, disable and clear windows 132 * First, disable and clear windows.
202 */ 133 */
203 for (i = 0; i < CPU_MAX_WIN; i++) { 134 for (i = 0; i < 8; i++) {
204 orion_write(CPU_WIN_BASE(i), 0); 135 orion_write(CPU_WIN_BASE(i), 0);
205 orion_write(CPU_WIN_CTRL(i), 0); 136 orion_write(CPU_WIN_CTRL(i), 0);
206 if (orion_cpu_win_can_remap(i)) { 137 if (orion_cpu_win_can_remap(i)) {
@@ -212,14 +143,14 @@ void __init orion_setup_cpu_wins(void)
212 /* 143 /*
213 * Setup windows for PCI+PCIe IO+MEM space. 144 * Setup windows for PCI+PCIe IO+MEM space.
214 */ 145 */
215 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, 146 setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE,
216 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); 147 TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE);
217 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, 148 setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE,
218 ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); 149 TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE);
219 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, 150 setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE,
220 ORION_PCIE_MEM_SIZE, -1); 151 TARGET_PCIE, ATTR_PCIE_MEM, -1);
221 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, 152 setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE,
222 ORION_PCI_MEM_SIZE, -1); 153 TARGET_PCI, ATTR_PCI_MEM, -1);
223 154
224 /* 155 /*
225 * Setup MBUS dram target info. 156 * Setup MBUS dram target info.
@@ -246,6 +177,31 @@ void __init orion_setup_cpu_wins(void)
246 orion_mbus_dram_info.num_cs = cs; 177 orion_mbus_dram_info.num_cs = cs;
247} 178}
248 179
180void __init orion_setup_dev_boot_win(u32 base, u32 size)
181{
182 setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
183}
184
185void __init orion_setup_dev0_win(u32 base, u32 size)
186{
187 setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
188}
189
190void __init orion_setup_dev1_win(u32 base, u32 size)
191{
192 setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
193}
194
195void __init orion_setup_dev2_win(u32 base, u32 size)
196{
197 setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
198}
199
200void __init orion_setup_pcie_wa_win(u32 base, u32 size)
201{
202 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
203}
204
249void __init orion_setup_eth_wins(void) 205void __init orion_setup_eth_wins(void)
250{ 206{
251 int i; 207 int i;