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authorLennert Buytenhek <buytenh@wantstofly.org>2008-03-27 14:51:39 -0400
committerNicolas Pitre <nico@marvell.com>2008-03-27 14:51:39 -0400
commit83b6d822e4237052371e771b1f994823615a5341 (patch)
treeb129c2ed5bdad53710d9a0396359d184cf3eb913 /arch/arm/mach-orion/addr-map.c
parentabc848c182960118fbb7cdae397b5608c5bcef1b (diff)
Orion: initialise mbus DRAM target info on boot
Initialise orion_mbus_dram_info on boot, and prepare for passing this info into peripheral drivers. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion/addr-map.c')
-rw-r--r--arch/arm/mach-orion/addr-map.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
index 58cc3c0333b6..ab4484cc14b7 100644
--- a/arch/arm/mach-orion/addr-map.c
+++ b/arch/arm/mach-orion/addr-map.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/mbus.h>
15#include <asm/hardware.h> 16#include <asm/hardware.h>
16#include "common.h" 17#include "common.h"
17 18
@@ -168,6 +169,9 @@
168#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) 169#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
169#define SATA_MAX_WIN 4 170#define SATA_MAX_WIN 4
170 171
172
173struct mbus_dram_target_info orion_mbus_dram_info;
174
171static int __init orion_cpu_win_can_remap(u32 win) 175static int __init orion_cpu_win_can_remap(u32 win)
172{ 176{
173 u32 dev, rev; 177 u32 dev, rev;
@@ -257,6 +261,7 @@ void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, in
257void __init orion_setup_cpu_wins(void) 261void __init orion_setup_cpu_wins(void)
258{ 262{
259 int i; 263 int i;
264 int cs;
260 265
261 /* 266 /*
262 * First, disable and clear windows 267 * First, disable and clear windows
@@ -281,6 +286,30 @@ void __init orion_setup_cpu_wins(void)
281 ORION_PCIE_MEM_SIZE, -1); 286 ORION_PCIE_MEM_SIZE, -1);
282 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, 287 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
283 ORION_PCI_MEM_SIZE, -1); 288 ORION_PCI_MEM_SIZE, -1);
289
290 /*
291 * Setup MBUS dram target info.
292 */
293 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
294
295 for (i = 0, cs = 0; i < 4; i++) {
296 u32 base = readl(DDR_BASE_CS(i));
297 u32 size = readl(DDR_SIZE_CS(i));
298
299 /*
300 * Chip select enabled?
301 */
302 if (size & 1) {
303 struct mbus_dram_window *w;
304
305 w = &orion_mbus_dram_info.cs[cs++];
306 w->cs_index = i;
307 w->mbus_attr = 0xf & ~(1 << i);
308 w->base = base & 0xff000000;
309 w->size = (size | 0x00ffffff) + 1;
310 }
311 }
312 orion_mbus_dram_info.num_cs = cs;
284} 313}
285 314
286/* 315/*