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authorTony Lindgren <tony@atomide.com>2005-07-10 14:58:09 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-07-10 14:58:09 -0400
commit3b59b6beb423267e8fe2ef3596d98aba0b910341 (patch)
tree585d06163371608f1192e1d104da06290f1c5bd9 /arch/arm/mach-omap
parentb288f75ffa6f26f720d0c69fcd09b4ee7122e17b (diff)
[PATCH] ARM: 2800/1: OMAP update 3/11: Move OMAP1 core code into mach-omap1 directory
Patch from Tony Lindgren This patch by Paul Mundt and other OMAP developers moves OMAP1 specific IRQ, time, and FPGA code into mach-omap1 directory. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap')
-rw-r--r--arch/arm/mach-omap/fpga.c188
-rw-r--r--arch/arm/mach-omap/irq.c219
-rw-r--r--arch/arm/mach-omap/time.c424
3 files changed, 0 insertions, 831 deletions
diff --git a/arch/arm/mach-omap/fpga.c b/arch/arm/mach-omap/fpga.c
deleted file mode 100644
index 7c08f6c2e1d0..000000000000
--- a/arch/arm/mach-omap/fpga.c
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap/fpga.c
3 *
4 * Interrupt handler for OMAP-1510 Innovator FPGA
5 *
6 * Copyright (C) 2001 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * Copyright (C) 2002 MontaVista Software, Inc.
10 *
11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
12 * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/config.h>
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/device.h>
24#include <linux/errno.h>
25
26#include <asm/hardware.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/mach/irq.h>
30
31#include <asm/arch/fpga.h>
32#include <asm/arch/gpio.h>
33
34static void fpga_mask_irq(unsigned int irq)
35{
36 irq -= OMAP1510_IH_FPGA_BASE;
37
38 if (irq < 8)
39 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
40 & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
41 else if (irq < 16)
42 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
43 & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
44 else
45 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
46 & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
47}
48
49
50static inline u32 get_fpga_unmasked_irqs(void)
51{
52 return
53 ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
54 __raw_readb(OMAP1510_FPGA_IMR_LO))) |
55 ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
56 __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
57 ((__raw_readb(INNOVATOR_FPGA_ISR2) &
58 __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
59}
60
61
62static void fpga_ack_irq(unsigned int irq)
63{
64 /* Don't need to explicitly ACK FPGA interrupts */
65}
66
67static void fpga_unmask_irq(unsigned int irq)
68{
69 irq -= OMAP1510_IH_FPGA_BASE;
70
71 if (irq < 8)
72 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
73 OMAP1510_FPGA_IMR_LO);
74 else if (irq < 16)
75 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
76 | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
77 else
78 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
79 | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
80}
81
82static void fpga_mask_ack_irq(unsigned int irq)
83{
84 fpga_mask_irq(irq);
85 fpga_ack_irq(irq);
86}
87
88void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
89 struct pt_regs *regs)
90{
91 struct irqdesc *d;
92 u32 stat;
93 int fpga_irq;
94
95 stat = get_fpga_unmasked_irqs();
96
97 if (!stat)
98 return;
99
100 for (fpga_irq = OMAP1510_IH_FPGA_BASE;
101 (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
102 fpga_irq++, stat >>= 1) {
103 if (stat & 1) {
104 d = irq_desc + fpga_irq;
105 d->handle(fpga_irq, d, regs);
106 }
107 }
108}
109
110static struct irqchip omap_fpga_irq_ack = {
111 .ack = fpga_mask_ack_irq,
112 .mask = fpga_mask_irq,
113 .unmask = fpga_unmask_irq,
114};
115
116
117static struct irqchip omap_fpga_irq = {
118 .ack = fpga_ack_irq,
119 .mask = fpga_mask_irq,
120 .unmask = fpga_unmask_irq,
121};
122
123/*
124 * All of the FPGA interrupt request inputs except for the touchscreen are
125 * edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive
126 * interrupts are acknowledged as a side-effect of reading the interrupt
127 * status register from the FPGA. The edge-sensitive interrupt inputs
128 * cause a problem with level interrupt requests, such as Ethernet. The
129 * problem occurs when a level interrupt request is asserted while its
130 * interrupt input is masked in the FPGA, which results in a missed
131 * interrupt.
132 *
133 * In an attempt to workaround the problem with missed interrupts, the
134 * mask_ack routine for all of the FPGA interrupts has been changed from
135 * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
136 * being serviced is left unmasked. We can do this because the FPGA cascade
137 * interrupt is installed with the SA_INTERRUPT flag, which leaves all
138 * interrupts masked at the CPU while an FPGA interrupt handler executes.
139 *
140 * Limited testing indicates that this workaround appears to be effective
141 * for the smc9194 Ethernet driver used on the Innovator. It should work
142 * on other FPGA interrupts as well, but any drivers that explicitly mask
143 * interrupts at the interrupt controller via disable_irq/enable_irq
144 * could pose a problem.
145 */
146void omap1510_fpga_init_irq(void)
147{
148 int i;
149
150 __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
151 __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
152 __raw_writeb(0, INNOVATOR_FPGA_IMR2);
153
154 for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
155
156 if (i == OMAP1510_INT_FPGA_TS) {
157 /*
158 * The touchscreen interrupt is level-sensitive, so
159 * we'll use the regular mask_ack routine for it.
160 */
161 set_irq_chip(i, &omap_fpga_irq_ack);
162 }
163 else {
164 /*
165 * All FPGA interrupts except the touchscreen are
166 * edge-sensitive, so we won't mask them.
167 */
168 set_irq_chip(i, &omap_fpga_irq);
169 }
170
171 set_irq_handler(i, do_edge_IRQ);
172 set_irq_flags(i, IRQF_VALID);
173 }
174
175 /*
176 * The FPGA interrupt line is connected to GPIO13. Claim this pin for
177 * the ARM.
178 *
179 * NOTE: For general GPIO/MPUIO access and interrupts, please see
180 * gpio.[ch]
181 */
182 omap_request_gpio(13);
183 omap_set_gpio_direction(13, 1);
184 omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
185 set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
186}
187
188EXPORT_SYMBOL(omap1510_fpga_init_irq);
diff --git a/arch/arm/mach-omap/irq.c b/arch/arm/mach-omap/irq.c
deleted file mode 100644
index f01c99266a86..000000000000
--- a/arch/arm/mach-omap/irq.c
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap/irq.c
3 *
4 * Interrupt handler for all OMAP boards
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * Completely re-written to support various OMAP chips with bank specific
11 * interrupt handlers.
12 *
13 * Some snippets of the code taken from the older OMAP interrupt handler
14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38
39#include <linux/config.h>
40#include <linux/init.h>
41#include <linux/module.h>
42#include <linux/sched.h>
43#include <linux/interrupt.h>
44#include <linux/ptrace.h>
45
46#include <asm/hardware.h>
47#include <asm/irq.h>
48#include <asm/mach/irq.h>
49#include <asm/arch/gpio.h>
50
51#include <asm/io.h>
52
53#define IRQ_BANK(irq) ((irq) >> 5)
54#define IRQ_BIT(irq) ((irq) & 0x1f)
55
56struct omap_irq_bank {
57 unsigned long base_reg;
58 unsigned long trigger_map;
59};
60
61static unsigned int irq_bank_count = 0;
62static struct omap_irq_bank *irq_banks;
63
64static inline unsigned int irq_bank_readl(int bank, int offset)
65{
66 return omap_readl(irq_banks[bank].base_reg + offset);
67}
68
69static inline void irq_bank_writel(unsigned long value, int bank, int offset)
70{
71 omap_writel(value, irq_banks[bank].base_reg + offset);
72}
73
74static void omap_ack_irq(unsigned int irq)
75{
76 if (irq > 31)
77 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
78
79 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
80}
81
82static void omap_mask_irq(unsigned int irq)
83{
84 int bank = IRQ_BANK(irq);
85 u32 l;
86
87 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
88 l |= 1 << IRQ_BIT(irq);
89 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
90}
91
92static void omap_unmask_irq(unsigned int irq)
93{
94 int bank = IRQ_BANK(irq);
95 u32 l;
96
97 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
98 l &= ~(1 << IRQ_BIT(irq));
99 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
100}
101
102static void omap_mask_ack_irq(unsigned int irq)
103{
104 omap_mask_irq(irq);
105 omap_ack_irq(irq);
106}
107
108/*
109 * Allows tuning the IRQ type and priority
110 *
111 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
112 * mailing list threads on FIQ handlers if you are planning to
113 * add a FIQ handler for OMAP.
114 */
115static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
116{
117 signed int bank;
118 unsigned long val, offset;
119
120 bank = IRQ_BANK(irq);
121 /* FIQ is only available on bank 0 interrupts */
122 fiq = bank ? 0 : (fiq & 0x1);
123 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
124 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
125 irq_bank_writel(val, bank, offset);
126}
127
128#ifdef CONFIG_ARCH_OMAP730
129static struct omap_irq_bank omap730_irq_banks[] = {
130 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
131 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
132 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
133};
134#endif
135
136#ifdef CONFIG_ARCH_OMAP1510
137static struct omap_irq_bank omap1510_irq_banks[] = {
138 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
139 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
140};
141#endif
142
143#if defined(CONFIG_ARCH_OMAP16XX)
144
145static struct omap_irq_bank omap1610_irq_banks[] = {
146 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
147 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
148 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xfffff7ff },
149 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
150};
151#endif
152
153static struct irqchip omap_irq_chip = {
154 .ack = omap_mask_ack_irq,
155 .mask = omap_mask_irq,
156 .unmask = omap_unmask_irq,
157};
158
159void __init omap_init_irq(void)
160{
161 int i, j;
162
163#ifdef CONFIG_ARCH_OMAP730
164 if (cpu_is_omap730()) {
165 irq_banks = omap730_irq_banks;
166 irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
167 }
168#endif
169#ifdef CONFIG_ARCH_OMAP1510
170 if (cpu_is_omap1510()) {
171 irq_banks = omap1510_irq_banks;
172 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
173 }
174#endif
175#if defined(CONFIG_ARCH_OMAP16XX)
176 if (cpu_is_omap16xx()) {
177 irq_banks = omap1610_irq_banks;
178 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
179 }
180#endif
181 printk("Total of %i interrupts in %i interrupt banks\n",
182 irq_bank_count * 32, irq_bank_count);
183
184 /* Mask and clear all interrupts */
185 for (i = 0; i < irq_bank_count; i++) {
186 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
187 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
188 }
189
190 /* Clear any pending interrupts */
191 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
192 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
193
194 /* Enable interrupts in global mask */
195 if (cpu_is_omap730()) {
196 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
197 }
198
199 /* Install the interrupt handlers for each bank */
200 for (i = 0; i < irq_bank_count; i++) {
201 for (j = i * 32; j < (i + 1) * 32; j++) {
202 int irq_trigger;
203
204 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
205 omap_irq_set_cfg(j, 0, 0, irq_trigger);
206
207 set_irq_chip(j, &omap_irq_chip);
208 set_irq_handler(j, do_level_IRQ);
209 set_irq_flags(j, IRQF_VALID);
210 }
211 }
212
213 /* Unmask level 2 handler */
214 if (cpu_is_omap730()) {
215 omap_unmask_irq(INT_730_IH2_IRQ);
216 } else {
217 omap_unmask_irq(INT_IH2_IRQ);
218 }
219}
diff --git a/arch/arm/mach-omap/time.c b/arch/arm/mach-omap/time.c
deleted file mode 100644
index dd34e9f4c413..000000000000
--- a/arch/arm/mach-omap/time.c
+++ /dev/null
@@ -1,424 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap/time.c
3 *
4 * OMAP Timers
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 *
11 * MPU timer code based on the older MPU timer code for OMAP
12 * Copyright (C) 2000 RidgeRun, Inc.
13 * Author: Greg Lonnon <glonnon@ridgerun.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#include <linux/config.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/sched.h>
42#include <linux/spinlock.h>
43
44#include <asm/system.h>
45#include <asm/hardware.h>
46#include <asm/io.h>
47#include <asm/leds.h>
48#include <asm/irq.h>
49#include <asm/mach/irq.h>
50#include <asm/mach/time.h>
51
52struct sys_timer omap_timer;
53
54#ifdef CONFIG_OMAP_MPU_TIMER
55
56/*
57 * ---------------------------------------------------------------------------
58 * MPU timer
59 * ---------------------------------------------------------------------------
60 */
61#define OMAP_MPU_TIMER1_BASE (0xfffec500)
62#define OMAP_MPU_TIMER2_BASE (0xfffec600)
63#define OMAP_MPU_TIMER3_BASE (0xfffec700)
64#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
65#define OMAP_MPU_TIMER_OFFSET 0x100
66
67#define MPU_TIMER_FREE (1 << 6)
68#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
69#define MPU_TIMER_AR (1 << 1)
70#define MPU_TIMER_ST (1 << 0)
71
72/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
73 * converted to use kHz by Kevin Hilman */
74/* convert from cycles(64bits) => nanoseconds (64bits)
75 * basic equation:
76 * ns = cycles / (freq / ns_per_sec)
77 * ns = cycles * (ns_per_sec / freq)
78 * ns = cycles * (10^9 / (cpu_khz * 10^3))
79 * ns = cycles * (10^6 / cpu_khz)
80 *
81 * Then we use scaling math (suggested by george at mvista.com) to get:
82 * ns = cycles * (10^6 * SC / cpu_khz / SC
83 * ns = cycles * cyc2ns_scale / SC
84 *
85 * And since SC is a constant power of two, we can convert the div
86 * into a shift.
87 * -johnstul at us.ibm.com "math is hard, lets go shopping!"
88 */
89static unsigned long cyc2ns_scale;
90#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
91
92static inline void set_cyc2ns_scale(unsigned long cpu_khz)
93{
94 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
95}
96
97static inline unsigned long long cycles_2_ns(unsigned long long cyc)
98{
99 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
100}
101
102/*
103 * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
104 * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
105 * with 0. This divides the 13MHz input by 2, and is undocumented.
106 */
107#ifdef CONFIG_MACH_OMAP_PERSEUS2
108/* REVISIT: This ifdef construct should be replaced by a query to clock
109 * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
110 */
111#define MPU_TICKS_PER_SEC (13000000 / 2)
112#else
113#define MPU_TICKS_PER_SEC (12000000 / 2)
114#endif
115
116#define MPU_TIMER_TICK_PERIOD ((MPU_TICKS_PER_SEC / HZ) - 1)
117
118typedef struct {
119 u32 cntl; /* CNTL_TIMER, R/W */
120 u32 load_tim; /* LOAD_TIM, W */
121 u32 read_tim; /* READ_TIM, R */
122} omap_mpu_timer_regs_t;
123
124#define omap_mpu_timer_base(n) \
125((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
126 (n)*OMAP_MPU_TIMER_OFFSET))
127
128static inline unsigned long omap_mpu_timer_read(int nr)
129{
130 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
131 return timer->read_tim;
132}
133
134static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
135{
136 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
137
138 timer->cntl = MPU_TIMER_CLOCK_ENABLE;
139 udelay(1);
140 timer->load_tim = load_val;
141 udelay(1);
142 timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
143}
144
145unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
146{
147 unsigned long long nsec;
148
149 nsec = cycles_2_ns((unsigned long long)nr_ticks);
150 return (unsigned long)nsec / 1000;
151}
152
153/*
154 * Last processed system timer interrupt
155 */
156static unsigned long omap_mpu_timer_last = 0;
157
158/*
159 * Returns elapsed usecs since last system timer interrupt
160 */
161static unsigned long omap_mpu_timer_gettimeoffset(void)
162{
163 unsigned long now = 0 - omap_mpu_timer_read(0);
164 unsigned long elapsed = now - omap_mpu_timer_last;
165
166 return omap_mpu_timer_ticks_to_usecs(elapsed);
167}
168
169/*
170 * Elapsed time between interrupts is calculated using timer0.
171 * Latency during the interrupt is calculated using timer1.
172 * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
173 */
174static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
175 struct pt_regs *regs)
176{
177 unsigned long now, latency;
178
179 write_seqlock(&xtime_lock);
180 now = 0 - omap_mpu_timer_read(0);
181 latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
182 omap_mpu_timer_last = now - latency;
183 timer_tick(regs);
184 write_sequnlock(&xtime_lock);
185
186 return IRQ_HANDLED;
187}
188
189static struct irqaction omap_mpu_timer_irq = {
190 .name = "mpu timer",
191 .flags = SA_INTERRUPT | SA_TIMER,
192 .handler = omap_mpu_timer_interrupt,
193};
194
195static unsigned long omap_mpu_timer1_overflows;
196static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
197 struct pt_regs *regs)
198{
199 omap_mpu_timer1_overflows++;
200 return IRQ_HANDLED;
201}
202
203static struct irqaction omap_mpu_timer1_irq = {
204 .name = "mpu timer1 overflow",
205 .flags = SA_INTERRUPT,
206 .handler = omap_mpu_timer1_interrupt,
207};
208
209static __init void omap_init_mpu_timer(void)
210{
211 set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
212 omap_timer.offset = omap_mpu_timer_gettimeoffset;
213 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
214 setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
215 omap_mpu_timer_start(0, 0xffffffff);
216 omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
217}
218
219/*
220 * Scheduler clock - returns current time in nanosec units.
221 */
222unsigned long long sched_clock(void)
223{
224 unsigned long ticks = 0 - omap_mpu_timer_read(0);
225 unsigned long long ticks64;
226
227 ticks64 = omap_mpu_timer1_overflows;
228 ticks64 <<= 32;
229 ticks64 |= ticks;
230
231 return cycles_2_ns(ticks64);
232}
233#endif /* CONFIG_OMAP_MPU_TIMER */
234
235#ifdef CONFIG_OMAP_32K_TIMER
236
237#ifdef CONFIG_ARCH_OMAP1510
238#error OMAP 32KHz timer does not currently work on 1510!
239#endif
240
241/*
242 * ---------------------------------------------------------------------------
243 * 32KHz OS timer
244 *
245 * This currently works only on 16xx, as 1510 does not have the continuous
246 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
247 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
248 * on 1510 would be possible, but the timer would not be as accurate as
249 * with the 32KHz synchronized timer.
250 * ---------------------------------------------------------------------------
251 */
252#define OMAP_32K_TIMER_BASE 0xfffb9000
253#define OMAP_32K_TIMER_CR 0x08
254#define OMAP_32K_TIMER_TVR 0x00
255#define OMAP_32K_TIMER_TCR 0x04
256
257#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
258
259/*
260 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
261 * so with HZ = 100, TVR = 327.68.
262 */
263#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
264#define TIMER_32K_SYNCHRONIZED 0xfffbc410
265
266#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
267 (((nr_jiffies) * (clock_rate)) / HZ)
268
269static inline void omap_32k_timer_write(int val, int reg)
270{
271 omap_writew(val, reg + OMAP_32K_TIMER_BASE);
272}
273
274static inline unsigned long omap_32k_timer_read(int reg)
275{
276 return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
277}
278
279/*
280 * The 32KHz synchronized timer is an additional timer on 16xx.
281 * It is always running.
282 */
283static inline unsigned long omap_32k_sync_timer_read(void)
284{
285 return omap_readl(TIMER_32K_SYNCHRONIZED);
286}
287
288static inline void omap_32k_timer_start(unsigned long load_val)
289{
290 omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
291 omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
292}
293
294static inline void omap_32k_timer_stop(void)
295{
296 omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
297}
298
299/*
300 * Rounds down to nearest usec
301 */
302static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
303{
304 return (ticks_32k * 5*5*5*5*5*5) >> 9;
305}
306
307static unsigned long omap_32k_last_tick = 0;
308
309/*
310 * Returns elapsed usecs since last 32k timer interrupt
311 */
312static unsigned long omap_32k_timer_gettimeoffset(void)
313{
314 unsigned long now = omap_32k_sync_timer_read();
315 return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
316}
317
318/*
319 * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
320 * function is also called from other interrupts to remove latency
321 * issues with dynamic tick. In the dynamic tick case, we need to lock
322 * with irqsave.
323 */
324static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
325 struct pt_regs *regs)
326{
327 unsigned long flags;
328 unsigned long now;
329
330 write_seqlock_irqsave(&xtime_lock, flags);
331 now = omap_32k_sync_timer_read();
332
333 while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
334 omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
335 timer_tick(regs);
336 }
337
338 /* Restart timer so we don't drift off due to modulo or dynamic tick.
339 * By default we program the next timer to be continuous to avoid
340 * latencies during high system load. During dynamic tick operation the
341 * continuous timer can be overridden from pm_idle to be longer.
342 */
343 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
344 write_sequnlock_irqrestore(&xtime_lock, flags);
345
346 return IRQ_HANDLED;
347}
348
349#ifdef CONFIG_NO_IDLE_HZ
350/*
351 * Programs the next timer interrupt needed. Called when dynamic tick is
352 * enabled, and to reprogram the ticks to skip from pm_idle. Note that
353 * we can keep the timer continuous, and don't need to set it to run in
354 * one-shot mode. This is because the timer will get reprogrammed again
355 * after next interrupt.
356 */
357void omap_32k_timer_reprogram(unsigned long next_tick)
358{
359 omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
360}
361
362static struct irqaction omap_32k_timer_irq;
363extern struct timer_update_handler timer_update;
364
365static int omap_32k_timer_enable_dyn_tick(void)
366{
367 /* No need to reprogram timer, just use the next interrupt */
368 return 0;
369}
370
371static int omap_32k_timer_disable_dyn_tick(void)
372{
373 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
374 return 0;
375}
376
377static struct dyn_tick_timer omap_dyn_tick_timer = {
378 .enable = omap_32k_timer_enable_dyn_tick,
379 .disable = omap_32k_timer_disable_dyn_tick,
380 .reprogram = omap_32k_timer_reprogram,
381 .handler = omap_32k_timer_interrupt,
382};
383#endif /* CONFIG_NO_IDLE_HZ */
384
385static struct irqaction omap_32k_timer_irq = {
386 .name = "32KHz timer",
387 .flags = SA_INTERRUPT | SA_TIMER,
388 .handler = omap_32k_timer_interrupt,
389};
390
391static __init void omap_init_32k_timer(void)
392{
393
394#ifdef CONFIG_NO_IDLE_HZ
395 omap_timer.dyn_tick = &omap_dyn_tick_timer;
396#endif
397
398 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
399 omap_timer.offset = omap_32k_timer_gettimeoffset;
400 omap_32k_last_tick = omap_32k_sync_timer_read();
401 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
402}
403#endif /* CONFIG_OMAP_32K_TIMER */
404
405/*
406 * ---------------------------------------------------------------------------
407 * Timer initialization
408 * ---------------------------------------------------------------------------
409 */
410void __init omap_timer_init(void)
411{
412#if defined(CONFIG_OMAP_MPU_TIMER)
413 omap_init_mpu_timer();
414#elif defined(CONFIG_OMAP_32K_TIMER)
415 omap_init_32k_timer();
416#else
417#error No system timer selected in Kconfig!
418#endif
419}
420
421struct sys_timer omap_timer = {
422 .init = omap_timer_init,
423 .offset = NULL, /* Initialized later */
424};
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