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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 14:14:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 14:14:29 -0400
commitb3345d7c57d70e6cb6749af25cdbe80515582e99 (patch)
tree04cce706bc7e944ad1fb257108a8ae735948f97f /arch/arm/mach-omap2
parent44c916d58b9ef1f2c4aec2def57fa8289c716a60 (diff)
parentc2fff85e21818952aa0ee5778926beee6c03e579 (diff)
Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/cm2_7xx.h4
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-omap2/dma.c3
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c14
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c13
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c40
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c100
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c574
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c55
-rw-r--r--arch/arm/mach-omap2/prcm43xx.h1
-rw-r--r--arch/arm/mach-omap2/prm7xx.h4
16 files changed, 734 insertions, 107 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fa7800015753..4481b6867902 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -202,6 +202,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
202obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o 202obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
203 203
204# hwmod data 204# hwmod data
205obj-y += omap_hwmod_common_ipblock_data.o
205obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o 206obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
206obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o 207obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
207obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o 208obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594e7622..e966e3a3c931 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) 357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
360#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
361#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
362#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
363#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
360#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 364#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
361#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 365#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
362#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 366#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index b6f8f348296e..324f02bf8a51 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -432,9 +432,9 @@ static int __init omap2_init_devices(void)
432 */ 432 */
433 omap_init_audio(); 433 omap_init_audio();
434 omap_init_camera(); 434 omap_init_camera();
435 omap_init_mbox();
436 /* If dtb is there, the devices will be created dynamically */ 435 /* If dtb is there, the devices will be created dynamically */
437 if (!of_have_populated_dt()) { 436 if (!of_have_populated_dt()) {
437 omap_init_mbox();
438 omap_init_mcspi(); 438 omap_init_mcspi();
439 omap_init_sham(); 439 omap_init_sham();
440 omap_init_aes(); 440 omap_init_aes();
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index a6d2cf1f8d02..e1a56d87599e 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -259,6 +259,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
259 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 259 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
260 d->dev_caps |= HS_CHANNELS_RESERVED; 260 d->dev_caps |= HS_CHANNELS_RESERVED;
261 261
262 if (platform_get_irq_byname(pdev, "0") < 0)
263 d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
264
262 /* Check the capabilities register for descriptor loading feature */ 265 /* Check the capabilities register for descriptor loading feature */
263 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) 266 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
264 dma_common_ch_end = CCDN; 267 dma_common_ch_end = CCDN;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 2f15979c2e9c..65b1647092bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,7 +16,6 @@
16#include <linux/i2c-omap.h> 16#include <linux/i2c-omap.h>
17#include <linux/platform_data/spi-omap2-mcspi.h> 17#include <linux/platform_data/spi-omap2-mcspi.h>
18#include <linux/omap-dma.h> 18#include <linux/omap-dma.h>
19#include <linux/platform_data/mailbox-omap.h>
20#include <plat/dmtimer.h> 19#include <plat/dmtimer.h>
21 20
22#include "omap_hwmod.h" 21#include "omap_hwmod.h"
@@ -163,18 +162,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
163}; 162};
164 163
165/* mailbox */ 164/* mailbox */
166static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
167 { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
168 { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
169};
170
171static struct omap_mbox_pdata omap2420_mailbox_attrs = {
172 .num_users = 4,
173 .num_fifos = 6,
174 .info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
175 .info = omap2420_mailbox_info,
176};
177
178static struct omap_hwmod omap2420_mailbox_hwmod = { 165static struct omap_hwmod omap2420_mailbox_hwmod = {
179 .name = "mailbox", 166 .name = "mailbox",
180 .class = &omap2xxx_mailbox_hwmod_class, 167 .class = &omap2xxx_mailbox_hwmod_class,
@@ -188,7 +175,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
188 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 175 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
189 }, 176 },
190 }, 177 },
191 .dev_attr = &omap2420_mailbox_attrs,
192}; 178};
193 179
194/* 180/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 6d1b60902179..c2555cb95e71 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,7 +17,6 @@
17#include <linux/platform_data/asoc-ti-mcbsp.h> 17#include <linux/platform_data/asoc-ti-mcbsp.h>
18#include <linux/platform_data/spi-omap2-mcspi.h> 18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include <linux/omap-dma.h> 19#include <linux/omap-dma.h>
20#include <linux/platform_data/mailbox-omap.h>
21#include <plat/dmtimer.h> 20#include <plat/dmtimer.h>
22 21
23#include "omap_hwmod.h" 22#include "omap_hwmod.h"
@@ -161,17 +160,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
161}; 160};
162 161
163/* mailbox */ 162/* mailbox */
164static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
165 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
166};
167
168static struct omap_mbox_pdata omap2430_mailbox_attrs = {
169 .num_users = 4,
170 .num_fifos = 6,
171 .info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
172 .info = omap2430_mailbox_info,
173};
174
175static struct omap_hwmod omap2430_mailbox_hwmod = { 163static struct omap_hwmod omap2430_mailbox_hwmod = {
176 .name = "mailbox", 164 .name = "mailbox",
177 .class = &omap2xxx_mailbox_hwmod_class, 165 .class = &omap2xxx_mailbox_hwmod_class,
@@ -185,7 +173,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
185 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 173 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
186 }, 174 },
187 }, 175 },
188 .dev_attr = &omap2430_mailbox_attrs,
189}; 176};
190 177
191/* mcspi3 */ 178/* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index 0413daba2dba..c1e98d589100 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -152,15 +152,6 @@ struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
152 { } 152 { }
153}; 153};
154 154
155struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
156 {
157 .pa_start = 0x48094000,
158 .pa_end = 0x48094000 + SZ_512 - 1,
159 .flags = ADDR_TYPE_RT,
160 },
161 { }
162};
163
164struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = { 155struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
165 { 156 {
166 .name = "mpu", 157 .name = "mpu",
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 5da7a42a6d90..c6c6384de867 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -37,46 +37,6 @@ struct omap_hwmod_class omap2_uart_class = {
37}; 37};
38 38
39/* 39/*
40 * 'dss' class
41 * display sub-system
42 */
43
44static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
45 .rev_offs = 0x0000,
46 .sysc_offs = 0x0010,
47 .syss_offs = 0x0014,
48 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
49 SYSS_HAS_RESET_STATUS),
50 .sysc_fields = &omap_hwmod_sysc_type1,
51};
52
53struct omap_hwmod_class omap2_dss_hwmod_class = {
54 .name = "dss",
55 .sysc = &omap2_dss_sysc,
56 .reset = omap_dss_reset,
57};
58
59/*
60 * 'rfbi' class
61 * remote frame buffer interface
62 */
63
64static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
65 .rev_offs = 0x0000,
66 .sysc_offs = 0x0010,
67 .syss_offs = 0x0014,
68 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
69 SYSC_HAS_AUTOIDLE),
70 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
71 .sysc_fields = &omap_hwmod_sysc_type1,
72};
73
74struct omap_hwmod_class omap2_rfbi_hwmod_class = {
75 .name = "rfbi",
76 .sysc = &omap2_rfbi_sysc,
77};
78
79/*
80 * 'venc' class 40 * 'venc' class
81 * video encoder 41 * video encoder
82 */ 42 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
index e2db378b849e..8f5989d48a80 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -317,21 +317,11 @@ struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
317 .user = OCP_USER_MPU, 317 .user = OCP_USER_MPU,
318}; 318};
319 319
320static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
321 {
322 .pa_start = 0x480C8000,
323 .pa_end = 0x480C8000 + (SZ_4K - 1),
324 .flags = ADDR_TYPE_RT
325 },
326 { }
327};
328
329/* l4 ls -> mailbox */ 320/* l4 ls -> mailbox */
330struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { 321struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
331 .master = &am33xx_l4_ls_hwmod, 322 .master = &am33xx_l4_ls_hwmod,
332 .slave = &am33xx_mailbox_hwmod, 323 .slave = &am33xx_mailbox_hwmod,
333 .clk = "l4ls_gclk", 324 .clk = "l4ls_gclk",
334 .addr = am33xx_mailbox_addrs,
335 .user = OCP_USER_MPU, 325 .user = OCP_USER_MPU,
336}; 326};
337 327
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 5c2cc8083fdd..fea01aa3ef42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -19,6 +19,8 @@
19#include "omap_hwmod.h" 19#include "omap_hwmod.h"
20#include "omap_hwmod_33xx_43xx_common_data.h" 20#include "omap_hwmod_33xx_43xx_common_data.h"
21#include "prcm43xx.h" 21#include "prcm43xx.h"
22#include "omap_hwmod_common_data.h"
23
22 24
23/* IP blocks */ 25/* IP blocks */
24static struct omap_hwmod am43xx_l4_hs_hwmod = { 26static struct omap_hwmod am43xx_l4_hs_hwmod = {
@@ -415,6 +417,72 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
415 }, 417 },
416}; 418};
417 419
420/* dss */
421
422static struct omap_hwmod am43xx_dss_core_hwmod = {
423 .name = "dss_core",
424 .class = &omap2_dss_hwmod_class,
425 .clkdm_name = "dss_clkdm",
426 .main_clk = "disp_clk",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
430 .modulemode = MODULEMODE_SWCTRL,
431 },
432 },
433};
434
435/* dispc */
436
437struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
438 .manager_count = 1,
439 .has_framedonetv_irq = 0
440};
441
442static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
443 .rev_offs = 0x0000,
444 .sysc_offs = 0x0010,
445 .syss_offs = 0x0014,
446 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
447 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
448 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
449 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
450 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
451 .sysc_fields = &omap_hwmod_sysc_type1,
452};
453
454static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
455 .name = "dispc",
456 .sysc = &am43xx_dispc_sysc,
457};
458
459static struct omap_hwmod am43xx_dss_dispc_hwmod = {
460 .name = "dss_dispc",
461 .class = &am43xx_dispc_hwmod_class,
462 .clkdm_name = "dss_clkdm",
463 .main_clk = "disp_clk",
464 .prcm = {
465 .omap4 = {
466 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
467 },
468 },
469 .dev_attr = &am43xx_dss_dispc_dev_attr,
470};
471
472/* rfbi */
473
474static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
475 .name = "dss_rfbi",
476 .class = &omap2_rfbi_hwmod_class,
477 .clkdm_name = "dss_clkdm",
478 .main_clk = "disp_clk",
479 .prcm = {
480 .omap4 = {
481 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
482 },
483 },
484};
485
418/* Interfaces */ 486/* Interfaces */
419static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { 487static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
420 .master = &am33xx_l3_main_hwmod, 488 .master = &am33xx_l3_main_hwmod,
@@ -654,6 +722,34 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
654 .user = OCP_USER_MPU | OCP_USER_SDMA, 722 .user = OCP_USER_MPU | OCP_USER_SDMA,
655}; 723};
656 724
725static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
726 .master = &am43xx_dss_core_hwmod,
727 .slave = &am33xx_l3_main_hwmod,
728 .clk = "l3_gclk",
729 .user = OCP_USER_MPU | OCP_USER_SDMA,
730};
731
732static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
733 .master = &am33xx_l4_ls_hwmod,
734 .slave = &am43xx_dss_core_hwmod,
735 .clk = "l4ls_gclk",
736 .user = OCP_USER_MPU | OCP_USER_SDMA,
737};
738
739static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
740 .master = &am33xx_l4_ls_hwmod,
741 .slave = &am43xx_dss_dispc_hwmod,
742 .clk = "l4ls_gclk",
743 .user = OCP_USER_MPU | OCP_USER_SDMA,
744};
745
746static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
747 .master = &am33xx_l4_ls_hwmod,
748 .slave = &am43xx_dss_rfbi_hwmod,
749 .clk = "l4ls_gclk",
750 .user = OCP_USER_MPU | OCP_USER_SDMA,
751};
752
657static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { 753static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
658 &am33xx_l4_wkup__synctimer, 754 &am33xx_l4_wkup__synctimer,
659 &am43xx_l4_ls__timer8, 755 &am43xx_l4_ls__timer8,
@@ -748,6 +844,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
748 &am43xx_l4_ls__ocp2scp1, 844 &am43xx_l4_ls__ocp2scp1,
749 &am43xx_l3_s__usbotgss0, 845 &am43xx_l3_s__usbotgss0,
750 &am43xx_l3_s__usbotgss1, 846 &am43xx_l3_s__usbotgss1,
847 &am43xx_dss__l3_main,
848 &am43xx_l4_ls__dss,
849 &am43xx_l4_ls__dss_dispc,
850 &am43xx_l4_ls__dss_rfbi,
751 NULL, 851 NULL,
752}; 852};
753 853
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index b4acc0a7576f..44e5634bba34 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -4138,21 +4138,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4138 .user = OCP_USER_MPU | OCP_USER_SDMA, 4138 .user = OCP_USER_MPU | OCP_USER_SDMA,
4139}; 4139};
4140 4140
4141static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4142 {
4143 .pa_start = 0x4a0f4000,
4144 .pa_end = 0x4a0f41ff,
4145 .flags = ADDR_TYPE_RT
4146 },
4147 { }
4148};
4149
4150/* l4_cfg -> mailbox */ 4141/* l4_cfg -> mailbox */
4151static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { 4142static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4152 .master = &omap44xx_l4_cfg_hwmod, 4143 .master = &omap44xx_l4_cfg_hwmod,
4153 .slave = &omap44xx_mailbox_hwmod, 4144 .slave = &omap44xx_mailbox_hwmod,
4154 .clk = "l4_div_ck", 4145 .clk = "l4_div_ck",
4155 .addr = omap44xx_mailbox_addrs,
4156 .user = OCP_USER_MPU | OCP_USER_SDMA, 4146 .user = OCP_USER_MPU | OCP_USER_SDMA,
4157}; 4147};
4158 4148
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 284324f2b98a..2757abf87fbc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -273,6 +273,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
273}; 273};
274 274
275/* 275/*
276 * 'gmac' class
277 * cpsw/gmac sub system
278 */
279static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
280 .rev_offs = 0x0,
281 .sysc_offs = 0x8,
282 .syss_offs = 0x4,
283 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
284 SYSS_HAS_RESET_STATUS),
285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
286 MSTANDBY_NO),
287 .sysc_fields = &omap_hwmod_sysc_type3,
288};
289
290static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
291 .name = "gmac",
292 .sysc = &dra7xx_gmac_sysc,
293};
294
295static struct omap_hwmod dra7xx_gmac_hwmod = {
296 .name = "gmac",
297 .class = &dra7xx_gmac_hwmod_class,
298 .clkdm_name = "gmac_clkdm",
299 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
300 .main_clk = "dpll_gmac_ck",
301 .mpu_rt_idx = 1,
302 .prcm = {
303 .omap4 = {
304 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
305 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
306 .modulemode = MODULEMODE_SWCTRL,
307 },
308 },
309};
310
311/*
312 * 'mdio' class
313 */
314static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
315 .name = "davinci_mdio",
316};
317
318static struct omap_hwmod dra7xx_mdio_hwmod = {
319 .name = "davinci_mdio",
320 .class = &dra7xx_mdio_hwmod_class,
321 .clkdm_name = "gmac_clkdm",
322 .main_clk = "dpll_gmac_ck",
323};
324
325/*
276 * 'dcan' class 326 * 'dcan' class
277 * 327 *
278 */ 328 */
@@ -343,19 +393,10 @@ static struct omap_dma_dev_attr dma_dev_attr = {
343}; 393};
344 394
345/* dma_system */ 395/* dma_system */
346static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
351 { .irq = -1 }
352};
353
354static struct omap_hwmod dra7xx_dma_system_hwmod = { 396static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system", 397 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class, 398 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm", 399 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div", 400 .main_clk = "l3_iclk_div",
360 .prcm = { 401 .prcm = {
361 .omap4 = { 402 .omap4 = {
@@ -939,6 +980,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = {
939}; 980};
940 981
941/* 982/*
983 * 'mailbox' class
984 *
985 */
986
987static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
988 .rev_offs = 0x0000,
989 .sysc_offs = 0x0010,
990 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
991 SYSC_HAS_SOFTRESET),
992 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
993 .sysc_fields = &omap_hwmod_sysc_type2,
994};
995
996static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
997 .name = "mailbox",
998 .sysc = &dra7xx_mailbox_sysc,
999};
1000
1001/* mailbox1 */
1002static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1003 .name = "mailbox1",
1004 .class = &dra7xx_mailbox_hwmod_class,
1005 .clkdm_name = "l4cfg_clkdm",
1006 .prcm = {
1007 .omap4 = {
1008 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1009 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1010 },
1011 },
1012};
1013
1014/* mailbox2 */
1015static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1016 .name = "mailbox2",
1017 .class = &dra7xx_mailbox_hwmod_class,
1018 .clkdm_name = "l4cfg_clkdm",
1019 .prcm = {
1020 .omap4 = {
1021 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1022 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1023 },
1024 },
1025};
1026
1027/* mailbox3 */
1028static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1029 .name = "mailbox3",
1030 .class = &dra7xx_mailbox_hwmod_class,
1031 .clkdm_name = "l4cfg_clkdm",
1032 .prcm = {
1033 .omap4 = {
1034 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1035 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1036 },
1037 },
1038};
1039
1040/* mailbox4 */
1041static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1042 .name = "mailbox4",
1043 .class = &dra7xx_mailbox_hwmod_class,
1044 .clkdm_name = "l4cfg_clkdm",
1045 .prcm = {
1046 .omap4 = {
1047 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1048 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1049 },
1050 },
1051};
1052
1053/* mailbox5 */
1054static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1055 .name = "mailbox5",
1056 .class = &dra7xx_mailbox_hwmod_class,
1057 .clkdm_name = "l4cfg_clkdm",
1058 .prcm = {
1059 .omap4 = {
1060 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1061 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1062 },
1063 },
1064};
1065
1066/* mailbox6 */
1067static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1068 .name = "mailbox6",
1069 .class = &dra7xx_mailbox_hwmod_class,
1070 .clkdm_name = "l4cfg_clkdm",
1071 .prcm = {
1072 .omap4 = {
1073 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1074 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1075 },
1076 },
1077};
1078
1079/* mailbox7 */
1080static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1081 .name = "mailbox7",
1082 .class = &dra7xx_mailbox_hwmod_class,
1083 .clkdm_name = "l4cfg_clkdm",
1084 .prcm = {
1085 .omap4 = {
1086 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1087 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1088 },
1089 },
1090};
1091
1092/* mailbox8 */
1093static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1094 .name = "mailbox8",
1095 .class = &dra7xx_mailbox_hwmod_class,
1096 .clkdm_name = "l4cfg_clkdm",
1097 .prcm = {
1098 .omap4 = {
1099 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1100 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1101 },
1102 },
1103};
1104
1105/* mailbox9 */
1106static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1107 .name = "mailbox9",
1108 .class = &dra7xx_mailbox_hwmod_class,
1109 .clkdm_name = "l4cfg_clkdm",
1110 .prcm = {
1111 .omap4 = {
1112 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1113 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1114 },
1115 },
1116};
1117
1118/* mailbox10 */
1119static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1120 .name = "mailbox10",
1121 .class = &dra7xx_mailbox_hwmod_class,
1122 .clkdm_name = "l4cfg_clkdm",
1123 .prcm = {
1124 .omap4 = {
1125 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1126 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1127 },
1128 },
1129};
1130
1131/* mailbox11 */
1132static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1133 .name = "mailbox11",
1134 .class = &dra7xx_mailbox_hwmod_class,
1135 .clkdm_name = "l4cfg_clkdm",
1136 .prcm = {
1137 .omap4 = {
1138 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1139 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1140 },
1141 },
1142};
1143
1144/* mailbox12 */
1145static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1146 .name = "mailbox12",
1147 .class = &dra7xx_mailbox_hwmod_class,
1148 .clkdm_name = "l4cfg_clkdm",
1149 .prcm = {
1150 .omap4 = {
1151 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1152 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1153 },
1154 },
1155};
1156
1157/* mailbox13 */
1158static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1159 .name = "mailbox13",
1160 .class = &dra7xx_mailbox_hwmod_class,
1161 .clkdm_name = "l4cfg_clkdm",
1162 .prcm = {
1163 .omap4 = {
1164 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1165 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1166 },
1167 },
1168};
1169
1170/*
942 * 'mcspi' class 1171 * 'mcspi' class
943 * 1172 *
944 */ 1173 */
@@ -1215,6 +1444,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1215 }, 1444 },
1216}; 1445};
1217 1446
1447/* ocp2scp3 */
1448static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1449 .name = "ocp2scp3",
1450 .class = &dra7xx_ocp2scp_hwmod_class,
1451 .clkdm_name = "l3init_clkdm",
1452 .main_clk = "l4_root_clk_div",
1453 .prcm = {
1454 .omap4 = {
1455 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1456 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1457 .modulemode = MODULEMODE_HWCTRL,
1458 },
1459 },
1460};
1461
1462/*
1463 * 'PCIE' class
1464 *
1465 */
1466
1467static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1468 .name = "pcie",
1469};
1470
1471/* pcie1 */
1472static struct omap_hwmod dra7xx_pcie1_hwmod = {
1473 .name = "pcie1",
1474 .class = &dra7xx_pcie_hwmod_class,
1475 .clkdm_name = "pcie_clkdm",
1476 .main_clk = "l4_root_clk_div",
1477 .prcm = {
1478 .omap4 = {
1479 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1480 .modulemode = MODULEMODE_SWCTRL,
1481 },
1482 },
1483};
1484
1485/* pcie2 */
1486static struct omap_hwmod dra7xx_pcie2_hwmod = {
1487 .name = "pcie2",
1488 .class = &dra7xx_pcie_hwmod_class,
1489 .clkdm_name = "pcie_clkdm",
1490 .main_clk = "l4_root_clk_div",
1491 .prcm = {
1492 .omap4 = {
1493 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1494 .modulemode = MODULEMODE_SWCTRL,
1495 },
1496 },
1497};
1498
1499/*
1500 * 'PCIE PHY' class
1501 *
1502 */
1503
1504static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1505 .name = "pcie-phy",
1506};
1507
1508/* pcie1 phy */
1509static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1510 .name = "pcie1-phy",
1511 .class = &dra7xx_pcie_phy_hwmod_class,
1512 .clkdm_name = "l3init_clkdm",
1513 .main_clk = "l4_root_clk_div",
1514 .prcm = {
1515 .omap4 = {
1516 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1517 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1518 .modulemode = MODULEMODE_SWCTRL,
1519 },
1520 },
1521};
1522
1523/* pcie2 phy */
1524static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1525 .name = "pcie2-phy",
1526 .class = &dra7xx_pcie_phy_hwmod_class,
1527 .clkdm_name = "l3init_clkdm",
1528 .main_clk = "l4_root_clk_div",
1529 .prcm = {
1530 .omap4 = {
1531 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1532 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1533 .modulemode = MODULEMODE_SWCTRL,
1534 },
1535 },
1536};
1537
1218/* 1538/*
1219 * 'qspi' class 1539 * 'qspi' class
1220 * 1540 *
@@ -1249,6 +1569,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = {
1249}; 1569};
1250 1570
1251/* 1571/*
1572 * 'rtcss' class
1573 *
1574 */
1575static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1576 .sysc_offs = 0x0078,
1577 .sysc_flags = SYSC_HAS_SIDLEMODE,
1578 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1579 SIDLE_SMART_WKUP),
1580 .sysc_fields = &omap_hwmod_sysc_type3,
1581};
1582
1583static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1584 .name = "rtcss",
1585 .sysc = &dra7xx_rtcss_sysc,
1586};
1587
1588/* rtcss */
1589static struct omap_hwmod dra7xx_rtcss_hwmod = {
1590 .name = "rtcss",
1591 .class = &dra7xx_rtcss_hwmod_class,
1592 .clkdm_name = "rtc_clkdm",
1593 .main_clk = "sys_32k_ck",
1594 .prcm = {
1595 .omap4 = {
1596 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1597 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1598 .modulemode = MODULEMODE_SWCTRL,
1599 },
1600 },
1601};
1602
1603/*
1252 * 'sata' class 1604 * 'sata' class
1253 * 1605 *
1254 */ 1606 */
@@ -2007,6 +2359,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2007 .user = OCP_USER_MPU | OCP_USER_SDMA, 2359 .user = OCP_USER_MPU | OCP_USER_SDMA,
2008}; 2360};
2009 2361
2362static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2363 .master = &dra7xx_l4_per2_hwmod,
2364 .slave = &dra7xx_gmac_hwmod,
2365 .clk = "dpll_gmac_ck",
2366 .user = OCP_USER_MPU,
2367};
2368
2369static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2370 .master = &dra7xx_gmac_hwmod,
2371 .slave = &dra7xx_mdio_hwmod,
2372 .user = OCP_USER_MPU,
2373};
2374
2010/* l4_wkup -> dcan1 */ 2375/* l4_wkup -> dcan1 */
2011static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { 2376static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2012 .master = &dra7xx_l4_wkup_hwmod, 2377 .master = &dra7xx_l4_wkup_hwmod,
@@ -2254,6 +2619,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2254 .user = OCP_USER_MPU | OCP_USER_SDMA, 2619 .user = OCP_USER_MPU | OCP_USER_SDMA,
2255}; 2620};
2256 2621
2622/* l4_cfg -> mailbox1 */
2623static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2624 .master = &dra7xx_l4_cfg_hwmod,
2625 .slave = &dra7xx_mailbox1_hwmod,
2626 .clk = "l3_iclk_div",
2627 .user = OCP_USER_MPU | OCP_USER_SDMA,
2628};
2629
2630/* l4_per3 -> mailbox2 */
2631static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2632 .master = &dra7xx_l4_per3_hwmod,
2633 .slave = &dra7xx_mailbox2_hwmod,
2634 .clk = "l3_iclk_div",
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636};
2637
2638/* l4_per3 -> mailbox3 */
2639static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2640 .master = &dra7xx_l4_per3_hwmod,
2641 .slave = &dra7xx_mailbox3_hwmod,
2642 .clk = "l3_iclk_div",
2643 .user = OCP_USER_MPU | OCP_USER_SDMA,
2644};
2645
2646/* l4_per3 -> mailbox4 */
2647static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2648 .master = &dra7xx_l4_per3_hwmod,
2649 .slave = &dra7xx_mailbox4_hwmod,
2650 .clk = "l3_iclk_div",
2651 .user = OCP_USER_MPU | OCP_USER_SDMA,
2652};
2653
2654/* l4_per3 -> mailbox5 */
2655static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2656 .master = &dra7xx_l4_per3_hwmod,
2657 .slave = &dra7xx_mailbox5_hwmod,
2658 .clk = "l3_iclk_div",
2659 .user = OCP_USER_MPU | OCP_USER_SDMA,
2660};
2661
2662/* l4_per3 -> mailbox6 */
2663static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2664 .master = &dra7xx_l4_per3_hwmod,
2665 .slave = &dra7xx_mailbox6_hwmod,
2666 .clk = "l3_iclk_div",
2667 .user = OCP_USER_MPU | OCP_USER_SDMA,
2668};
2669
2670/* l4_per3 -> mailbox7 */
2671static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2672 .master = &dra7xx_l4_per3_hwmod,
2673 .slave = &dra7xx_mailbox7_hwmod,
2674 .clk = "l3_iclk_div",
2675 .user = OCP_USER_MPU | OCP_USER_SDMA,
2676};
2677
2678/* l4_per3 -> mailbox8 */
2679static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2680 .master = &dra7xx_l4_per3_hwmod,
2681 .slave = &dra7xx_mailbox8_hwmod,
2682 .clk = "l3_iclk_div",
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684};
2685
2686/* l4_per3 -> mailbox9 */
2687static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2688 .master = &dra7xx_l4_per3_hwmod,
2689 .slave = &dra7xx_mailbox9_hwmod,
2690 .clk = "l3_iclk_div",
2691 .user = OCP_USER_MPU | OCP_USER_SDMA,
2692};
2693
2694/* l4_per3 -> mailbox10 */
2695static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2696 .master = &dra7xx_l4_per3_hwmod,
2697 .slave = &dra7xx_mailbox10_hwmod,
2698 .clk = "l3_iclk_div",
2699 .user = OCP_USER_MPU | OCP_USER_SDMA,
2700};
2701
2702/* l4_per3 -> mailbox11 */
2703static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2704 .master = &dra7xx_l4_per3_hwmod,
2705 .slave = &dra7xx_mailbox11_hwmod,
2706 .clk = "l3_iclk_div",
2707 .user = OCP_USER_MPU | OCP_USER_SDMA,
2708};
2709
2710/* l4_per3 -> mailbox12 */
2711static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2712 .master = &dra7xx_l4_per3_hwmod,
2713 .slave = &dra7xx_mailbox12_hwmod,
2714 .clk = "l3_iclk_div",
2715 .user = OCP_USER_MPU | OCP_USER_SDMA,
2716};
2717
2718/* l4_per3 -> mailbox13 */
2719static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2720 .master = &dra7xx_l4_per3_hwmod,
2721 .slave = &dra7xx_mailbox13_hwmod,
2722 .clk = "l3_iclk_div",
2723 .user = OCP_USER_MPU | OCP_USER_SDMA,
2724};
2725
2257/* l4_per1 -> mcspi1 */ 2726/* l4_per1 -> mcspi1 */
2258static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { 2727static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2259 .master = &dra7xx_l4_per1_hwmod, 2728 .master = &dra7xx_l4_per1_hwmod,
@@ -2334,6 +2803,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2334 .user = OCP_USER_MPU | OCP_USER_SDMA, 2803 .user = OCP_USER_MPU | OCP_USER_SDMA,
2335}; 2804};
2336 2805
2806/* l4_cfg -> ocp2scp3 */
2807static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2808 .master = &dra7xx_l4_cfg_hwmod,
2809 .slave = &dra7xx_ocp2scp3_hwmod,
2810 .clk = "l4_root_clk_div",
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2812};
2813
2814/* l3_main_1 -> pcie1 */
2815static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
2816 .master = &dra7xx_l3_main_1_hwmod,
2817 .slave = &dra7xx_pcie1_hwmod,
2818 .clk = "l3_iclk_div",
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2820};
2821
2822/* l4_cfg -> pcie1 */
2823static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2824 .master = &dra7xx_l4_cfg_hwmod,
2825 .slave = &dra7xx_pcie1_hwmod,
2826 .clk = "l4_root_clk_div",
2827 .user = OCP_USER_MPU | OCP_USER_SDMA,
2828};
2829
2830/* l3_main_1 -> pcie2 */
2831static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
2832 .master = &dra7xx_l3_main_1_hwmod,
2833 .slave = &dra7xx_pcie2_hwmod,
2834 .clk = "l3_iclk_div",
2835 .user = OCP_USER_MPU | OCP_USER_SDMA,
2836};
2837
2838/* l4_cfg -> pcie2 */
2839static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2840 .master = &dra7xx_l4_cfg_hwmod,
2841 .slave = &dra7xx_pcie2_hwmod,
2842 .clk = "l4_root_clk_div",
2843 .user = OCP_USER_MPU | OCP_USER_SDMA,
2844};
2845
2846/* l4_cfg -> pcie1 phy */
2847static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2848 .master = &dra7xx_l4_cfg_hwmod,
2849 .slave = &dra7xx_pcie1_phy_hwmod,
2850 .clk = "l4_root_clk_div",
2851 .user = OCP_USER_MPU | OCP_USER_SDMA,
2852};
2853
2854/* l4_cfg -> pcie2 phy */
2855static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2856 .master = &dra7xx_l4_cfg_hwmod,
2857 .slave = &dra7xx_pcie2_phy_hwmod,
2858 .clk = "l4_root_clk_div",
2859 .user = OCP_USER_MPU | OCP_USER_SDMA,
2860};
2861
2337static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { 2862static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2338 { 2863 {
2339 .pa_start = 0x4b300000, 2864 .pa_start = 0x4b300000,
@@ -2352,6 +2877,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2352 .user = OCP_USER_MPU | OCP_USER_SDMA, 2877 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353}; 2878};
2354 2879
2880/* l4_per3 -> rtcss */
2881static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2882 .master = &dra7xx_l4_per3_hwmod,
2883 .slave = &dra7xx_rtcss_hwmod,
2884 .clk = "l4_root_clk_div",
2885 .user = OCP_USER_MPU | OCP_USER_SDMA,
2886};
2887
2355static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { 2888static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2356 { 2889 {
2357 .name = "sysc", 2890 .name = "sysc",
@@ -2650,6 +3183,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2650 &dra7xx_l4_wkup__ctrl_module_wkup, 3183 &dra7xx_l4_wkup__ctrl_module_wkup,
2651 &dra7xx_l4_wkup__dcan1, 3184 &dra7xx_l4_wkup__dcan1,
2652 &dra7xx_l4_per2__dcan2, 3185 &dra7xx_l4_per2__dcan2,
3186 &dra7xx_l4_per2__cpgmac0,
3187 &dra7xx_gmac__mdio,
2653 &dra7xx_l4_cfg__dma_system, 3188 &dra7xx_l4_cfg__dma_system,
2654 &dra7xx_l3_main_1__dss, 3189 &dra7xx_l3_main_1__dss,
2655 &dra7xx_l3_main_1__dispc, 3190 &dra7xx_l3_main_1__dispc,
@@ -2670,6 +3205,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2670 &dra7xx_l4_per1__i2c3, 3205 &dra7xx_l4_per1__i2c3,
2671 &dra7xx_l4_per1__i2c4, 3206 &dra7xx_l4_per1__i2c4,
2672 &dra7xx_l4_per1__i2c5, 3207 &dra7xx_l4_per1__i2c5,
3208 &dra7xx_l4_cfg__mailbox1,
3209 &dra7xx_l4_per3__mailbox2,
3210 &dra7xx_l4_per3__mailbox3,
3211 &dra7xx_l4_per3__mailbox4,
3212 &dra7xx_l4_per3__mailbox5,
3213 &dra7xx_l4_per3__mailbox6,
3214 &dra7xx_l4_per3__mailbox7,
3215 &dra7xx_l4_per3__mailbox8,
3216 &dra7xx_l4_per3__mailbox9,
3217 &dra7xx_l4_per3__mailbox10,
3218 &dra7xx_l4_per3__mailbox11,
3219 &dra7xx_l4_per3__mailbox12,
3220 &dra7xx_l4_per3__mailbox13,
2673 &dra7xx_l4_per1__mcspi1, 3221 &dra7xx_l4_per1__mcspi1,
2674 &dra7xx_l4_per1__mcspi2, 3222 &dra7xx_l4_per1__mcspi2,
2675 &dra7xx_l4_per1__mcspi3, 3223 &dra7xx_l4_per1__mcspi3,
@@ -2680,7 +3228,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2680 &dra7xx_l4_per1__mmc4, 3228 &dra7xx_l4_per1__mmc4,
2681 &dra7xx_l4_cfg__mpu, 3229 &dra7xx_l4_cfg__mpu,
2682 &dra7xx_l4_cfg__ocp2scp1, 3230 &dra7xx_l4_cfg__ocp2scp1,
3231 &dra7xx_l4_cfg__ocp2scp3,
3232 &dra7xx_l3_main_1__pcie1,
3233 &dra7xx_l4_cfg__pcie1,
3234 &dra7xx_l3_main_1__pcie2,
3235 &dra7xx_l4_cfg__pcie2,
3236 &dra7xx_l4_cfg__pcie1_phy,
3237 &dra7xx_l4_cfg__pcie2_phy,
2683 &dra7xx_l3_main_1__qspi, 3238 &dra7xx_l3_main_1__qspi,
3239 &dra7xx_l4_per3__rtcss,
2684 &dra7xx_l4_cfg__sata, 3240 &dra7xx_l4_cfg__sata,
2685 &dra7xx_l4_cfg__smartreflex_core, 3241 &dra7xx_l4_cfg__smartreflex_core,
2686 &dra7xx_l4_cfg__smartreflex_mpu, 3242 &dra7xx_l4_cfg__smartreflex_mpu,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 2c38c6b0ee03..11ed5a17dd77 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -33,7 +33,6 @@ extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
33extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[]; 33extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
34extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[]; 34extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
35extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; 35extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
36extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
37extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; 36extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
38extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; 37extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
39 38
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c
new file mode 100644
index 000000000000..f21664da25a2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c
@@ -0,0 +1,55 @@
1/*
2 * omap_hwmod_common_ipblock_data.c - common IP block data for OMAP2+
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include "omap_hwmod.h"
14#include "omap_hwmod_common_data.h"
15
16/*
17 * 'dss' class
18 * display sub-system
19 */
20
21static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
22 .rev_offs = 0x0000,
23 .sysc_offs = 0x0010,
24 .syss_offs = 0x0014,
25 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
26 SYSS_HAS_RESET_STATUS),
27 .sysc_fields = &omap_hwmod_sysc_type1,
28};
29
30struct omap_hwmod_class omap2_dss_hwmod_class = {
31 .name = "dss",
32 .sysc = &omap2_dss_sysc,
33 .reset = omap_dss_reset,
34};
35
36/*
37 * 'rfbi' class
38 * remote frame buffer interface
39 */
40
41static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
42 .rev_offs = 0x0000,
43 .sysc_offs = 0x0010,
44 .syss_offs = 0x0014,
45 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
46 SYSC_HAS_AUTOIDLE),
47 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
48 .sysc_fields = &omap_hwmod_sysc_type1,
49};
50
51struct omap_hwmod_class omap2_rfbi_hwmod_class = {
52 .name = "rfbi",
53 .sysc = &omap2_rfbi_sysc,
54};
55
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 7785be984edd..ad7b3e9977f8 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -142,5 +142,6 @@
142#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 142#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8
143#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 143#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268
144#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 144#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
145#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
145 146
146#endif 147#endif
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a8404edc7..4bb50fbf29be 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
377#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
378#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4
379#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8
380#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc
377#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 381#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
378#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 382#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
379#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 383#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 16:40:24 -0500