diff options
author | Tero Kristo <t-kristo@ti.com> | 2014-02-20 12:09:18 -0500 |
---|---|---|
committer | Tero Kristo <t-kristo@ti.com> | 2014-07-02 07:26:06 -0400 |
commit | 944ee5dc154b1618d4c794376af237f370c1e6b3 (patch) | |
tree | c2a587ff9a954e04f7d333d2a0bb336aa6a27f07 /arch/arm/mach-omap2 | |
parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) |
ARM: OMAP2: convert sys_ck and osc_ck to standard clock types
osc_ck can be simply defined as a multiplexer clock, and the sys_ck
can be a simple divider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cclock2420_data.c | 52 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cclock2430_data.c | 60 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_osc.c | 69 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_sys.c | 47 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-24xx.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/pm24xx.c | 4 |
8 files changed, 67 insertions, 171 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 8421f38cf445..b5dc4b5aaac3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -174,10 +174,9 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o | |||
174 | 174 | ||
175 | # Clock framework | 175 | # Clock framework |
176 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o | 176 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o |
177 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o | ||
178 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o | 177 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o |
179 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o | 178 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o |
180 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o | 179 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o |
181 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o | 180 | obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o |
182 | obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o | 181 | obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o |
183 | obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o | 182 | obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o |
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 3662f4d4c8ea..3e46ac188533 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c | |||
@@ -57,40 +57,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); | |||
57 | 57 | ||
58 | DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); | 58 | DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); |
59 | 59 | ||
60 | static struct clk osc_ck; | 60 | DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); |
61 | 61 | ||
62 | static const struct clk_ops osc_ck_ops = { | 62 | DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); |
63 | .recalc_rate = &omap2_osc_clk_recalc, | ||
64 | }; | ||
65 | 63 | ||
66 | static struct clk_hw_omap osc_ck_hw = { | 64 | DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); |
67 | .hw = { | 65 | |
68 | .clk = &osc_ck, | 66 | DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); |
69 | }, | ||
70 | }; | ||
71 | 67 | ||
72 | static struct clk osc_ck = { | 68 | /* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */ |
73 | .name = "osc_ck", | 69 | static const char *aplls_clkin_ck_parent_names[] = { |
74 | .ops = &osc_ck_ops, | 70 | "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", |
75 | .hw = &osc_ck_hw.hw, | ||
76 | .flags = CLK_IS_ROOT, | ||
77 | }; | 71 | }; |
78 | 72 | ||
73 | DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, | ||
74 | OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, | ||
75 | OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); | ||
76 | |||
79 | DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); | 77 | DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); |
80 | 78 | ||
81 | static struct clk sys_ck; | 79 | DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, |
80 | 0x0, 2, 1); | ||
82 | 81 | ||
83 | static const char *sys_ck_parent_names[] = { | 82 | static const char *osc_ck_parent_names[] = { |
84 | "osc_ck", | 83 | "aplls_clkin_ck", "aplls_clkin_x2_ck", |
85 | }; | 84 | }; |
86 | 85 | ||
87 | static const struct clk_ops sys_ck_ops = { | 86 | DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, |
88 | .init = &omap2_init_clk_clkdm, | 87 | OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, |
89 | .recalc_rate = &omap2xxx_sys_clk_recalc, | 88 | OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); |
90 | }; | ||
91 | 89 | ||
92 | DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); | 90 | DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL, |
93 | DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); | 91 | OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, |
92 | CLK_DIVIDER_ONE_BASED, NULL); | ||
94 | 93 | ||
95 | static struct dpll_data dpll_dd = { | 94 | static struct dpll_data dpll_dd = { |
96 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 95 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
@@ -1741,6 +1740,12 @@ static struct omap_clk omap2420_clks[] = { | |||
1741 | /* external root sources */ | 1740 | /* external root sources */ |
1742 | CLK(NULL, "func_32k_ck", &func_32k_ck), | 1741 | CLK(NULL, "func_32k_ck", &func_32k_ck), |
1743 | CLK(NULL, "secure_32k_ck", &secure_32k_ck), | 1742 | CLK(NULL, "secure_32k_ck", &secure_32k_ck), |
1743 | CLK(NULL, "virt_12m_ck", &virt_12m_ck), | ||
1744 | CLK(NULL, "virt_13m_ck", &virt_13m_ck), | ||
1745 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), | ||
1746 | CLK(NULL, "virt_26m_ck", &virt_26m_ck), | ||
1747 | CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), | ||
1748 | CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), | ||
1744 | CLK(NULL, "osc_ck", &osc_ck), | 1749 | CLK(NULL, "osc_ck", &osc_ck), |
1745 | CLK(NULL, "sys_ck", &sys_ck), | 1750 | CLK(NULL, "sys_ck", &sys_ck), |
1746 | CLK(NULL, "alt_ck", &alt_ck), | 1751 | CLK(NULL, "alt_ck", &alt_ck), |
@@ -1904,7 +1909,6 @@ static const char *enable_init_clks[] = { | |||
1904 | 1909 | ||
1905 | int __init omap2420_clk_init(void) | 1910 | int __init omap2420_clk_init(void) |
1906 | { | 1911 | { |
1907 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | ||
1908 | cpu_mask = RATE_IN_242X; | 1912 | cpu_mask = RATE_IN_242X; |
1909 | rate_table = omap2420_rate_table; | 1913 | rate_table = omap2420_rate_table; |
1910 | 1914 | ||
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index 5e4b037bb24c..582abc221ece 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c | |||
@@ -55,42 +55,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); | |||
55 | 55 | ||
56 | DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); | 56 | DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); |
57 | 57 | ||
58 | static struct clk osc_ck; | 58 | DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); |
59 | 59 | ||
60 | static const struct clk_ops osc_ck_ops = { | 60 | DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); |
61 | .enable = &omap2_enable_osc_ck, | ||
62 | .disable = omap2_disable_osc_ck, | ||
63 | .recalc_rate = &omap2_osc_clk_recalc, | ||
64 | }; | ||
65 | 61 | ||
66 | static struct clk_hw_omap osc_ck_hw = { | 62 | DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); |
67 | .hw = { | ||
68 | .clk = &osc_ck, | ||
69 | }, | ||
70 | }; | ||
71 | 63 | ||
72 | static struct clk osc_ck = { | 64 | DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); |
73 | .name = "osc_ck", | 65 | |
74 | .ops = &osc_ck_ops, | 66 | /* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */ |
75 | .hw = &osc_ck_hw.hw, | 67 | static const char *aplls_clkin_ck_parent_names[] = { |
76 | .flags = CLK_IS_ROOT, | 68 | "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", |
77 | }; | 69 | }; |
78 | 70 | ||
71 | DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, | ||
72 | OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, | ||
73 | OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); | ||
74 | |||
79 | DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); | 75 | DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); |
80 | 76 | ||
81 | static struct clk sys_ck; | 77 | DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, |
78 | 0x0, 2, 1); | ||
82 | 79 | ||
83 | static const char *sys_ck_parent_names[] = { | 80 | static const char *osc_ck_parent_names[] = { |
84 | "osc_ck", | 81 | "aplls_clkin_ck", "aplls_clkin_x2_ck", |
85 | }; | 82 | }; |
86 | 83 | ||
87 | static const struct clk_ops sys_ck_ops = { | 84 | DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, |
88 | .init = &omap2_init_clk_clkdm, | 85 | OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, |
89 | .recalc_rate = &omap2xxx_sys_clk_recalc, | 86 | OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); |
90 | }; | ||
91 | 87 | ||
92 | DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); | 88 | DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL, |
93 | DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); | 89 | OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, |
90 | CLK_DIVIDER_ONE_BASED, NULL); | ||
94 | 91 | ||
95 | static struct dpll_data dpll_dd = { | 92 | static struct dpll_data dpll_dd = { |
96 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 93 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
@@ -1308,7 +1305,11 @@ static struct clk_hw_omap mdm_osc_ck_hw = { | |||
1308 | .clkdm_name = "mdm_clkdm", | 1305 | .clkdm_name = "mdm_clkdm", |
1309 | }; | 1306 | }; |
1310 | 1307 | ||
1311 | DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); | 1308 | static const char *mdm_osc_ck_parent_names[] = { |
1309 | "osc_ck", | ||
1310 | }; | ||
1311 | |||
1312 | DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops); | ||
1312 | 1313 | ||
1313 | static struct clk mmchs1_fck; | 1314 | static struct clk mmchs1_fck; |
1314 | 1315 | ||
@@ -1842,6 +1843,12 @@ static struct omap_clk omap2430_clks[] = { | |||
1842 | /* external root sources */ | 1843 | /* external root sources */ |
1843 | CLK(NULL, "func_32k_ck", &func_32k_ck), | 1844 | CLK(NULL, "func_32k_ck", &func_32k_ck), |
1844 | CLK(NULL, "secure_32k_ck", &secure_32k_ck), | 1845 | CLK(NULL, "secure_32k_ck", &secure_32k_ck), |
1846 | CLK(NULL, "virt_12m_ck", &virt_12m_ck), | ||
1847 | CLK(NULL, "virt_13m_ck", &virt_13m_ck), | ||
1848 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), | ||
1849 | CLK(NULL, "virt_26m_ck", &virt_26m_ck), | ||
1850 | CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), | ||
1851 | CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), | ||
1845 | CLK(NULL, "osc_ck", &osc_ck), | 1852 | CLK(NULL, "osc_ck", &osc_ck), |
1846 | CLK("twl", "fck", &osc_ck), | 1853 | CLK("twl", "fck", &osc_ck), |
1847 | CLK(NULL, "sys_ck", &sys_ck), | 1854 | CLK(NULL, "sys_ck", &sys_ck), |
@@ -2021,7 +2028,6 @@ static const char *enable_init_clks[] = { | |||
2021 | 2028 | ||
2022 | int __init omap2430_clk_init(void) | 2029 | int __init omap2430_clk_init(void) |
2023 | { | 2030 | { |
2024 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | ||
2025 | cpu_mask = RATE_IN_243X; | 2031 | cpu_mask = RATE_IN_243X; |
2026 | rate_table = omap2430_rate_table; | 2032 | rate_table = omap2430_rate_table; |
2027 | 2033 | ||
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c deleted file mode 100644 index 0717dff1bc04..000000000000 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ /dev/null | |||
@@ -1,69 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP2xxx osc_clk-specific clock code | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
6 | * | ||
7 | * Contacts: | ||
8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
12 | * Gordon McNutt and RidgeRun, Inc. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License version 2 as | ||
16 | * published by the Free Software Foundation. | ||
17 | */ | ||
18 | #undef DEBUG | ||
19 | |||
20 | #include <linux/module.h> | ||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/errno.h> | ||
23 | #include <linux/clk.h> | ||
24 | #include <linux/io.h> | ||
25 | |||
26 | #include "clock.h" | ||
27 | #include "clock2xxx.h" | ||
28 | #include "prm2xxx_3xxx.h" | ||
29 | #include "prm-regbits-24xx.h" | ||
30 | |||
31 | /* | ||
32 | * XXX This does not actually enable the osc_ck, since the osc_ck must | ||
33 | * be running for this function to be called. Instead, this function | ||
34 | * is used to disable an autoidle mode on the osc_ck. The existing | ||
35 | * clk_enable/clk_disable()-based usecounting for osc_ck should be | ||
36 | * replaced with autoidle-based usecounting. | ||
37 | */ | ||
38 | int omap2_enable_osc_ck(struct clk_hw *clk) | ||
39 | { | ||
40 | u32 pcc; | ||
41 | |||
42 | pcc = readl_relaxed(prcm_clksrc_ctrl); | ||
43 | |||
44 | writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
45 | |||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | /* | ||
50 | * XXX This does not actually disable the osc_ck, since doing so would | ||
51 | * immediately halt the system. Instead, this function is used to | ||
52 | * enable an autoidle mode on the osc_ck. The existing | ||
53 | * clk_enable/clk_disable()-based usecounting for osc_ck should be | ||
54 | * replaced with autoidle-based usecounting. | ||
55 | */ | ||
56 | void omap2_disable_osc_ck(struct clk_hw *clk) | ||
57 | { | ||
58 | u32 pcc; | ||
59 | |||
60 | pcc = readl_relaxed(prcm_clksrc_ctrl); | ||
61 | |||
62 | writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
63 | } | ||
64 | |||
65 | unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, | ||
66 | unsigned long parent_rate) | ||
67 | { | ||
68 | return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); | ||
69 | } | ||
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c deleted file mode 100644 index 58dd3a9b726c..000000000000 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP2xxx sys_clk-specific clock code | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
6 | * | ||
7 | * Contacts: | ||
8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
12 | * Gordon McNutt and RidgeRun, Inc. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License version 2 as | ||
16 | * published by the Free Software Foundation. | ||
17 | */ | ||
18 | #undef DEBUG | ||
19 | |||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/errno.h> | ||
22 | #include <linux/clk.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include "clock.h" | ||
26 | #include "clock2xxx.h" | ||
27 | #include "prm2xxx_3xxx.h" | ||
28 | #include "prm-regbits-24xx.h" | ||
29 | |||
30 | void __iomem *prcm_clksrc_ctrl; | ||
31 | |||
32 | u32 omap2xxx_get_sysclkdiv(void) | ||
33 | { | ||
34 | u32 div; | ||
35 | |||
36 | div = readl_relaxed(prcm_clksrc_ctrl); | ||
37 | div &= OMAP_SYSCLKDIV_MASK; | ||
38 | div >>= OMAP_SYSCLKDIV_SHIFT; | ||
39 | |||
40 | return div; | ||
41 | } | ||
42 | |||
43 | unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, | ||
44 | unsigned long parent_rate) | ||
45 | { | ||
46 | return parent_rate / omap2xxx_get_sysclkdiv(); | ||
47 | } | ||
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 45f41a411603..a090225ceeba 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
@@ -45,8 +45,6 @@ int omap2430_clk_init(void); | |||
45 | #define omap2430_clk_init() do { } while(0) | 45 | #define omap2430_clk_init() do { } while(0) |
46 | #endif | 46 | #endif |
47 | 47 | ||
48 | extern void __iomem *prcm_clksrc_ctrl; | ||
49 | |||
50 | extern struct clk_hw *dclk_hw; | 48 | extern struct clk_hw *dclk_hw; |
51 | int omap2_enable_osc_ck(struct clk_hw *hw); | 49 | int omap2_enable_osc_ck(struct clk_hw *hw); |
52 | void omap2_disable_osc_ck(struct clk_hw *hw); | 50 | void omap2_disable_osc_ck(struct clk_hw *hw); |
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 8538669cc2ad..d7a5d11cbcbf 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
@@ -107,6 +107,7 @@ | |||
107 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 | 107 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 |
108 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) | 108 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) |
109 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 | 109 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 |
110 | #define OMAP24XX_APLLS_CLKIN_WIDTH 3 | ||
110 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) | 111 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) |
111 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) | 112 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) |
112 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) | 113 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988ff340..d7ac05c6e5e2 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
@@ -249,6 +249,10 @@ static void __init prcm_setup_regs(void) | |||
249 | /* Enable wake-up events */ | 249 | /* Enable wake-up events */ |
250 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, | 250 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
251 | WKUP_MOD, PM_WKEN); | 251 | WKUP_MOD, PM_WKEN); |
252 | |||
253 | /* Enable SYS_CLKEN control when all domains idle */ | ||
254 | omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD, | ||
255 | OMAP2_PRCM_CLKSRC_CTRL_OFFSET); | ||
252 | } | 256 | } |
253 | 257 | ||
254 | int __init omap2_pm_init(void) | 258 | int __init omap2_pm_init(void) |