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authorTero Kristo <t-kristo@ti.com>2013-07-19 04:37:17 -0400
committerMike Turquette <mturquette@linaro.org>2014-01-17 15:37:28 -0500
commit149c09d3a61dcb90b9cc55beafc70f06e80389f1 (patch)
tree5cf709d8fcc90e453d49dae3719854f1b3abe612 /arch/arm/mach-omap2
parentd22031e2ac0777b35557bdd9f7959cc230de2625 (diff)
ARM: AM33xx: remove old clock data and link in new clock init code
AM33xx clocks have now been moved to DT, thus remove the old data file and use the new init code under OMAP clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c1064
-rw-r--r--arch/arm/mach-omap2/io.c2
3 files changed, 1 insertions, 1066 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 665455a852f4..8ebe9f3dd7d4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -190,7 +190,6 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
190obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) 190obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
191obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 191obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
192obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o 192obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
193obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
194obj-$(CONFIG_SOC_OMAP5) += $(clock-common) 193obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
195obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o 194obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
196obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) 195obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30ee812f..000000000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk-private.h>
20#include <linux/clkdev.h>
21#include <linux/io.h>
22
23#include "am33xx.h"
24#include "soc.h"
25#include "iomap.h"
26#include "clock.h"
27#include "control.h"
28#include "cm.h"
29#include "cm33xx.h"
30#include "cm-regbits-33xx.h"
31#include "prm.h"
32
33/* Modulemode control */
34#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
35#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
36
37/*LIST_HEAD(clocks);*/
38
39/* Root clocks */
40
41/* RTC 32k */
42DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
43
44/* On-Chip 32KHz RC OSC */
45DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
46
47/* Crystal input clks */
48DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
49
50DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
51
52DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
55
56/* Oscillator clock */
57/* 19.2, 24, 25 or 26 MHz */
58static const char *sys_clkin_ck_parents[] = {
59 "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
60 "virt_26000000_ck",
61};
62
63/*
64 * sys_clk in: input to the dpll and also used as funtional clock for,
65 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
66 *
67 */
68DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
69 AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
70 AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
71 AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
72 0, NULL);
73
74/* External clock - 12 MHz */
75DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
76
77/* Module clocks and DPLL outputs */
78
79/* DPLL_CORE */
80static struct dpll_data dpll_core_dd = {
81 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
82 .clk_bypass = &sys_clkin_ck,
83 .clk_ref = &sys_clkin_ck,
84 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
85 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
86 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
87 .mult_mask = AM33XX_DPLL_MULT_MASK,
88 .div1_mask = AM33XX_DPLL_DIV_MASK,
89 .enable_mask = AM33XX_DPLL_EN_MASK,
90 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
91 .max_multiplier = 2047,
92 .max_divider = 128,
93 .min_divider = 1,
94};
95
96/* CLKDCOLDO output */
97static const char *dpll_core_ck_parents[] = {
98 "sys_clkin_ck",
99};
100
101static struct clk dpll_core_ck;
102
103static const struct clk_ops dpll_core_ck_ops = {
104 .recalc_rate = &omap3_dpll_recalc,
105 .get_parent = &omap2_init_dpll_parent,
106};
107
108static struct clk_hw_omap dpll_core_ck_hw = {
109 .hw = {
110 .clk = &dpll_core_ck,
111 },
112 .dpll_data = &dpll_core_dd,
113 .ops = &clkhwops_omap3_dpll,
114};
115
116DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
117
118static const char *dpll_core_x2_ck_parents[] = {
119 "dpll_core_ck",
120};
121
122static struct clk dpll_core_x2_ck;
123
124static const struct clk_ops dpll_x2_ck_ops = {
125 .recalc_rate = &omap3_clkoutx2_recalc,
126};
127
128static struct clk_hw_omap dpll_core_x2_ck_hw = {
129 .hw = {
130 .clk = &dpll_core_x2_ck,
131 },
132 .flags = CLOCK_CLKOUTX2,
133};
134
135DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
136
137DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
138 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
139 AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
140 AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
141 NULL);
142
143DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
144 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
145 AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
146 AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
147 CLK_DIVIDER_ONE_BASED, NULL);
148
149DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
150 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
151 AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
152 AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
153 CLK_DIVIDER_ONE_BASED, NULL);
154
155
156/* DPLL_MPU */
157static struct dpll_data dpll_mpu_dd = {
158 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
159 .clk_bypass = &sys_clkin_ck,
160 .clk_ref = &sys_clkin_ck,
161 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
162 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
163 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
164 .mult_mask = AM33XX_DPLL_MULT_MASK,
165 .div1_mask = AM33XX_DPLL_DIV_MASK,
166 .enable_mask = AM33XX_DPLL_EN_MASK,
167 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
168 .max_multiplier = 2047,
169 .max_divider = 128,
170 .min_divider = 1,
171};
172
173/* CLKOUT: fdpll/M2 */
174static struct clk dpll_mpu_ck;
175
176static const struct clk_ops dpll_mpu_ck_ops = {
177 .enable = &omap3_noncore_dpll_enable,
178 .disable = &omap3_noncore_dpll_disable,
179 .recalc_rate = &omap3_dpll_recalc,
180 .round_rate = &omap2_dpll_round_rate,
181 .set_rate = &omap3_noncore_dpll_set_rate,
182 .get_parent = &omap2_init_dpll_parent,
183};
184
185static struct clk_hw_omap dpll_mpu_ck_hw = {
186 .hw = {
187 .clk = &dpll_mpu_ck,
188 },
189 .dpll_data = &dpll_mpu_dd,
190 .ops = &clkhwops_omap3_dpll,
191};
192
193DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
194
195/*
196 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
197 * and ALT_CLK1/2)
198 */
199DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
200 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
201 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
202
203/* DPLL_DDR */
204static struct dpll_data dpll_ddr_dd = {
205 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
206 .clk_bypass = &sys_clkin_ck,
207 .clk_ref = &sys_clkin_ck,
208 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
209 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
210 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
211 .mult_mask = AM33XX_DPLL_MULT_MASK,
212 .div1_mask = AM33XX_DPLL_DIV_MASK,
213 .enable_mask = AM33XX_DPLL_EN_MASK,
214 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
215 .max_multiplier = 2047,
216 .max_divider = 128,
217 .min_divider = 1,
218};
219
220/* CLKOUT: fdpll/M2 */
221static struct clk dpll_ddr_ck;
222
223static const struct clk_ops dpll_ddr_ck_ops = {
224 .recalc_rate = &omap3_dpll_recalc,
225 .get_parent = &omap2_init_dpll_parent,
226 .round_rate = &omap2_dpll_round_rate,
227 .set_rate = &omap3_noncore_dpll_set_rate,
228};
229
230static struct clk_hw_omap dpll_ddr_ck_hw = {
231 .hw = {
232 .clk = &dpll_ddr_ck,
233 },
234 .dpll_data = &dpll_ddr_dd,
235 .ops = &clkhwops_omap3_dpll,
236};
237
238DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
239
240/*
241 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
242 * and ALT_CLK1/2)
243 */
244DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
245 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
246 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
247 CLK_DIVIDER_ONE_BASED, NULL);
248
249/* emif_fck functional clock */
250DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
251 0x0, 1, 2);
252
253/* DPLL_DISP */
254static struct dpll_data dpll_disp_dd = {
255 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
256 .clk_bypass = &sys_clkin_ck,
257 .clk_ref = &sys_clkin_ck,
258 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
259 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
260 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
261 .mult_mask = AM33XX_DPLL_MULT_MASK,
262 .div1_mask = AM33XX_DPLL_DIV_MASK,
263 .enable_mask = AM33XX_DPLL_EN_MASK,
264 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
265 .max_multiplier = 2047,
266 .max_divider = 128,
267 .min_divider = 1,
268};
269
270/* CLKOUT: fdpll/M2 */
271static struct clk dpll_disp_ck;
272
273static struct clk_hw_omap dpll_disp_ck_hw = {
274 .hw = {
275 .clk = &dpll_disp_ck,
276 },
277 .dpll_data = &dpll_disp_dd,
278 .ops = &clkhwops_omap3_dpll,
279};
280
281DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
282
283/*
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2)
286 */
287DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
288 CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
289 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
290 CLK_DIVIDER_ONE_BASED, NULL);
291
292/* DPLL_PER */
293static struct dpll_data dpll_per_dd = {
294 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
295 .clk_bypass = &sys_clkin_ck,
296 .clk_ref = &sys_clkin_ck,
297 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
298 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
299 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
300 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
301 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
302 .enable_mask = AM33XX_DPLL_EN_MASK,
303 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
304 .max_multiplier = 2047,
305 .max_divider = 128,
306 .min_divider = 1,
307 .flags = DPLL_J_TYPE,
308};
309
310/* CLKDCOLDO */
311static struct clk dpll_per_ck;
312
313static struct clk_hw_omap dpll_per_ck_hw = {
314 .hw = {
315 .clk = &dpll_per_ck,
316 },
317 .dpll_data = &dpll_per_dd,
318 .ops = &clkhwops_omap3_dpll,
319};
320
321DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
322
323/* CLKOUT: fdpll/M2 */
324DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
325 AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
326 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
327 NULL);
328
329DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
330 &dpll_per_m2_ck, 0x0, 1, 4);
331
332DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
333 &dpll_per_m2_ck, 0x0, 1, 4);
334
335DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
336 &dpll_core_m4_ck, 0x0, 1, 2);
337
338DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
339 1, 2);
340
341DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
342 8);
343
344/*
345 * Below clock nodes describes clockdomains derived out
346 * of core clock.
347 */
348static const struct clk_ops clk_ops_null = {
349};
350
351static const char *l3_gclk_parents[] = {
352 "dpll_core_m4_ck"
353};
354
355static struct clk l3_gclk;
356DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
357DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
358
359static struct clk l4hs_gclk;
360DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
361DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
362
363static const char *l3s_gclk_parents[] = {
364 "dpll_core_m4_div2_ck"
365};
366
367static struct clk l3s_gclk;
368DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
369DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
370
371static struct clk l4fw_gclk;
372DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
373DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
374
375static struct clk l4ls_gclk;
376DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
377DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
378
379static struct clk sysclk_div_ck;
380DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
381DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
382
383/*
384 * In order to match the clock domain with hwmod clockdomain entry,
385 * separate clock nodes is required for the modules which are
386 * directly getting their funtioncal clock from sys_clkin.
387 */
388static struct clk adc_tsc_fck;
389DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
390DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
391
392static struct clk dcan0_fck;
393DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
394DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
395
396static struct clk dcan1_fck;
397DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
398DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
399
400static struct clk mcasp0_fck;
401DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
402DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
403
404static struct clk mcasp1_fck;
405DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
406DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
407
408static struct clk smartreflex0_fck;
409DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
410DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
411
412static struct clk smartreflex1_fck;
413DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
414DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
415
416static struct clk sha0_fck;
417DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
418DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
419
420static struct clk aes0_fck;
421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423
424static struct clk rng_fck;
425DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
426DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
427
428/*
429 * Modules clock nodes
430 *
431 * The following clock leaf nodes are added for the moment because:
432 *
433 * - hwmod data is not present for these modules, either hwmod
434 * control is not required or its not populated.
435 * - Driver code is not yet migrated to use hwmod/runtime pm
436 * - Modules outside kernel access (to disable them by default)
437 *
438 * - mmu (gfx domain)
439 * - cefuse
440 * - usbotg_fck (its additional clock and not really a modulemode)
441 * - ieee5000
442 */
443
444DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
445 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
446 0x0, NULL);
447
448DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
449 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
450 0x0, NULL);
451
452/*
453 * clkdiv32 is generated from fixed division of 732.4219
454 */
455DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
456
457static struct clk clkdiv32k_ick;
458
459static const char *clkdiv32k_ick_parent_names[] = {
460 "clkdiv32k_ck",
461};
462
463static const struct clk_ops clkdiv32k_ick_ops = {
464 .enable = &omap2_dflt_clk_enable,
465 .disable = &omap2_dflt_clk_disable,
466 .is_enabled = &omap2_dflt_clk_is_enabled,
467 .init = &omap2_init_clk_clkdm,
468};
469
470static struct clk_hw_omap clkdiv32k_ick_hw = {
471 .hw = {
472 .clk = &clkdiv32k_ick,
473 },
474 .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
475 .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
476 .clkdm_name = "clk_24mhz_clkdm",
477};
478
479DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
480
481/* "usbotg_fck" is an additional clock and not really a modulemode */
482DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
483 AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
484 0x0, NULL);
485
486DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
487 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
488 AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
489
490/* Timers */
491static const struct clksel timer1_clkmux_sel[] = {
492 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
493 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
494 { .parent = &tclkin_ck, .rates = div_1_2_rates },
495 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
496 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
497 { .parent = NULL },
498};
499
500static const char *timer1_ck_parents[] = {
501 "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
502 "clk_32768_ck",
503};
504
505static struct clk timer1_fck;
506
507static const struct clk_ops timer1_fck_ops = {
508 .recalc_rate = &omap2_clksel_recalc,
509 .get_parent = &omap2_clksel_find_parent_index,
510 .set_parent = &omap2_clksel_set_parent,
511 .init = &omap2_init_clk_clkdm,
512};
513
514static struct clk_hw_omap timer1_fck_hw = {
515 .hw = {
516 .clk = &timer1_fck,
517 },
518 .clkdm_name = "l4ls_clkdm",
519 .clksel = timer1_clkmux_sel,
520 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
521 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
522};
523
524DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
525
526static const struct clksel timer2_to_7_clk_sel[] = {
527 { .parent = &tclkin_ck, .rates = div_1_0_rates },
528 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
529 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
530 { .parent = NULL },
531};
532
533static const char *timer2_to_7_ck_parents[] = {
534 "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
535};
536
537static struct clk timer2_fck;
538
539static struct clk_hw_omap timer2_fck_hw = {
540 .hw = {
541 .clk = &timer2_fck,
542 },
543 .clkdm_name = "l4ls_clkdm",
544 .clksel = timer2_to_7_clk_sel,
545 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
546 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
547};
548
549DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
550
551static struct clk timer3_fck;
552
553static struct clk_hw_omap timer3_fck_hw = {
554 .hw = {
555 .clk = &timer3_fck,
556 },
557 .clkdm_name = "l4ls_clkdm",
558 .clksel = timer2_to_7_clk_sel,
559 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
560 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
561};
562
563DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
564
565static struct clk timer4_fck;
566
567static struct clk_hw_omap timer4_fck_hw = {
568 .hw = {
569 .clk = &timer4_fck,
570 },
571 .clkdm_name = "l4ls_clkdm",
572 .clksel = timer2_to_7_clk_sel,
573 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
574 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
575};
576
577DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
578
579static struct clk timer5_fck;
580
581static struct clk_hw_omap timer5_fck_hw = {
582 .hw = {
583 .clk = &timer5_fck,
584 },
585 .clkdm_name = "l4ls_clkdm",
586 .clksel = timer2_to_7_clk_sel,
587 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
588 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
589};
590
591DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
592
593static struct clk timer6_fck;
594
595static struct clk_hw_omap timer6_fck_hw = {
596 .hw = {
597 .clk = &timer6_fck,
598 },
599 .clkdm_name = "l4ls_clkdm",
600 .clksel = timer2_to_7_clk_sel,
601 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
602 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
603};
604
605DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
606
607static struct clk timer7_fck;
608
609static struct clk_hw_omap timer7_fck_hw = {
610 .hw = {
611 .clk = &timer7_fck,
612 },
613 .clkdm_name = "l4ls_clkdm",
614 .clksel = timer2_to_7_clk_sel,
615 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
616 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
617};
618
619DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
620
621DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
622 "dpll_core_m5_ck",
623 &dpll_core_m5_ck,
624 0x0,
625 1, 2);
626
627static const struct clk_ops cpsw_fck_ops = {
628 .recalc_rate = &omap2_clksel_recalc,
629 .get_parent = &omap2_clksel_find_parent_index,
630 .set_parent = &omap2_clksel_set_parent,
631};
632
633static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
634 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
635 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
636 { .parent = NULL },
637};
638
639static const char *cpsw_cpts_rft_ck_parents[] = {
640 "dpll_core_m5_ck", "dpll_core_m4_ck",
641};
642
643static struct clk cpsw_cpts_rft_clk;
644
645static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
646 .hw = {
647 .clk = &cpsw_cpts_rft_clk,
648 },
649 .clkdm_name = "cpsw_125mhz_clkdm",
650 .clksel = cpsw_cpts_rft_clkmux_sel,
651 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
652 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
653};
654
655DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
656
657
658/* gpio */
659static const char *gpio0_ck_parents[] = {
660 "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
661};
662
663static const struct clksel gpio0_dbclk_mux_sel[] = {
664 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
665 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
666 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
667 { .parent = NULL },
668};
669
670static const struct clk_ops gpio_fck_ops = {
671 .recalc_rate = &omap2_clksel_recalc,
672 .get_parent = &omap2_clksel_find_parent_index,
673 .set_parent = &omap2_clksel_set_parent,
674 .init = &omap2_init_clk_clkdm,
675};
676
677static struct clk gpio0_dbclk_mux_ck;
678
679static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
680 .hw = {
681 .clk = &gpio0_dbclk_mux_ck,
682 },
683 .clkdm_name = "l4_wkup_clkdm",
684 .clksel = gpio0_dbclk_mux_sel,
685 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
686 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
687};
688
689DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
690
691DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
692 AM33XX_CM_WKUP_GPIO0_CLKCTRL,
693 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
694
695DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
696 AM33XX_CM_PER_GPIO1_CLKCTRL,
697 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
698
699DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
700 AM33XX_CM_PER_GPIO2_CLKCTRL,
701 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
702
703DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
704 AM33XX_CM_PER_GPIO3_CLKCTRL,
705 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
706
707
708static const char *pruss_ck_parents[] = {
709 "l3_gclk", "dpll_disp_m2_ck",
710};
711
712static const struct clksel pruss_ocp_clk_mux_sel[] = {
713 { .parent = &l3_gclk, .rates = div_1_0_rates },
714 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
715 { .parent = NULL },
716};
717
718static struct clk pruss_ocp_gclk;
719
720static struct clk_hw_omap pruss_ocp_gclk_hw = {
721 .hw = {
722 .clk = &pruss_ocp_gclk,
723 },
724 .clkdm_name = "pruss_ocp_clkdm",
725 .clksel = pruss_ocp_clk_mux_sel,
726 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
727 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
728};
729
730DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
731
732static const char *lcd_ck_parents[] = {
733 "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
734};
735
736static const struct clksel lcd_clk_mux_sel[] = {
737 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
738 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
739 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
740 { .parent = NULL },
741};
742
743static struct clk lcd_gclk;
744
745static struct clk_hw_omap lcd_gclk_hw = {
746 .hw = {
747 .clk = &lcd_gclk,
748 },
749 .clkdm_name = "lcdc_clkdm",
750 .clksel = lcd_clk_mux_sel,
751 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
752 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
753};
754
755DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
756 gpio_fck_ops, CLK_SET_RATE_PARENT);
757
758DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
759
760static const char *gfx_ck_parents[] = {
761 "dpll_core_m4_ck", "dpll_per_m2_ck",
762};
763
764static const struct clksel gfx_clksel_sel[] = {
765 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
766 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
767 { .parent = NULL },
768};
769
770static struct clk gfx_fclk_clksel_ck;
771
772static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
773 .hw = {
774 .clk = &gfx_fclk_clksel_ck,
775 },
776 .clksel = gfx_clksel_sel,
777 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
778 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
779};
780
781DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
782
783static const struct clk_div_table div_1_0_2_1_rates[] = {
784 { .div = 1, .val = 0, },
785 { .div = 2, .val = 1, },
786 { .div = 0 },
787};
788
789DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
790 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
791 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
792 0x0, div_1_0_2_1_rates, NULL);
793
794static const char *sysclkout_ck_parents[] = {
795 "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
796 "lcd_gclk",
797};
798
799static const struct clksel sysclkout_pre_sel[] = {
800 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
801 { .parent = &l3_gclk, .rates = div_1_1_rates },
802 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
803 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
804 { .parent = &lcd_gclk, .rates = div_1_4_rates },
805 { .parent = NULL },
806};
807
808static struct clk sysclkout_pre_ck;
809
810static struct clk_hw_omap sysclkout_pre_ck_hw = {
811 .hw = {
812 .clk = &sysclkout_pre_ck,
813 },
814 .clksel = sysclkout_pre_sel,
815 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
816 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
817};
818
819DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
820
821/* Divide by 8 clock rates with default clock is 1/1*/
822static const struct clk_div_table div8_rates[] = {
823 { .div = 1, .val = 0, },
824 { .div = 2, .val = 1, },
825 { .div = 3, .val = 2, },
826 { .div = 4, .val = 3, },
827 { .div = 5, .val = 4, },
828 { .div = 6, .val = 5, },
829 { .div = 7, .val = 6, },
830 { .div = 8, .val = 7, },
831 { .div = 0 },
832};
833
834DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
835 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
836 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
837
838DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
839 AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
840
841static const char *wdt_ck_parents[] = {
842 "clk_rc32k_ck", "clkdiv32k_ick",
843};
844
845static const struct clksel wdt_clkmux_sel[] = {
846 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
847 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
848 { .parent = NULL },
849};
850
851static struct clk wdt1_fck;
852
853static struct clk_hw_omap wdt1_fck_hw = {
854 .hw = {
855 .clk = &wdt1_fck,
856 },
857 .clkdm_name = "l4_wkup_clkdm",
858 .clksel = wdt_clkmux_sel,
859 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
860 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
861};
862
863DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
864
865static const char *pwmss_clk_parents[] = {
866 "dpll_per_m2_ck",
867};
868
869static const struct clk_ops ehrpwm_tbclk_ops = {
870 .enable = &omap2_dflt_clk_enable,
871 .disable = &omap2_dflt_clk_disable,
872};
873
874DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
875 NULL, NULL, 0,
876 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
877 AM33XX_PWMSS0_TBCLKEN_SHIFT,
878 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
879
880DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
881 NULL, NULL, 0,
882 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
883 AM33XX_PWMSS1_TBCLKEN_SHIFT,
884 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
885
886DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
887 NULL, NULL, 0,
888 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
889 AM33XX_PWMSS2_TBCLKEN_SHIFT,
890 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
891
892/*
893 * debugss optional clocks
894 */
895DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
896 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
897 AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
898
899DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
900 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
901 AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
902
903static const char *stm_pmd_clock_mux_ck_parents[] = {
904 "dbg_sysclk_ck", "dbg_clka_ck",
905};
906
907DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
908 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
909 AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
910
911DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
912 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
913 AM33XX_TRC_PMD_CLKSEL_SHIFT,
914 AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
915
916DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
917 &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
918 AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
919 AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
920 NULL);
921
922DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
923 &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
924 AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
925 AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
926 NULL);
927
928/*
929 * clkdev
930 */
931static struct omap_clk am33xx_clks[] = {
932 CLK(NULL, "clk_32768_ck", &clk_32768_ck),
933 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
934 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
935 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
936 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
937 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
938 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
939 CLK(NULL, "tclkin_ck", &tclkin_ck),
940 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
941 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
942 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
943 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
944 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
945 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
946 CLK("cpu0", NULL, &dpll_mpu_ck),
947 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
948 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
949 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
950 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
951 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
952 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
953 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
954 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
955 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
956 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
957 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
958 CLK(NULL, "cefuse_fck", &cefuse_fck),
959 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
960 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
961 CLK(NULL, "dcan0_fck", &dcan0_fck),
962 CLK("481cc000.d_can", NULL, &dcan0_fck),
963 CLK(NULL, "dcan1_fck", &dcan1_fck),
964 CLK("481d0000.d_can", NULL, &dcan1_fck),
965 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
966 CLK(NULL, "mcasp0_fck", &mcasp0_fck),
967 CLK(NULL, "mcasp1_fck", &mcasp1_fck),
968 CLK(NULL, "mmu_fck", &mmu_fck),
969 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
970 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
971 CLK(NULL, "sha0_fck", &sha0_fck),
972 CLK(NULL, "aes0_fck", &aes0_fck),
973 CLK(NULL, "rng_fck", &rng_fck),
974 CLK(NULL, "timer1_fck", &timer1_fck),
975 CLK(NULL, "timer2_fck", &timer2_fck),
976 CLK(NULL, "timer3_fck", &timer3_fck),
977 CLK(NULL, "timer4_fck", &timer4_fck),
978 CLK(NULL, "timer5_fck", &timer5_fck),
979 CLK(NULL, "timer6_fck", &timer6_fck),
980 CLK(NULL, "timer7_fck", &timer7_fck),
981 CLK(NULL, "usbotg_fck", &usbotg_fck),
982 CLK(NULL, "ieee5000_fck", &ieee5000_fck),
983 CLK(NULL, "wdt1_fck", &wdt1_fck),
984 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
985 CLK(NULL, "l3_gclk", &l3_gclk),
986 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
987 CLK(NULL, "l4hs_gclk", &l4hs_gclk),
988 CLK(NULL, "l3s_gclk", &l3s_gclk),
989 CLK(NULL, "l4fw_gclk", &l4fw_gclk),
990 CLK(NULL, "l4ls_gclk", &l4ls_gclk),
991 CLK(NULL, "clk_24mhz", &clk_24mhz),
992 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
993 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
994 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
995 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
996 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
997 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
998 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
999 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
1000 CLK(NULL, "lcd_gclk", &lcd_gclk),
1001 CLK(NULL, "mmc_clk", &mmc_clk),
1002 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
1003 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
1004 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
1005 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
1006 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
1007 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
1008 CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck),
1009 CLK(NULL, "dbg_clka_ck", &dbg_clka_ck),
1010 CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
1011 CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
1012 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
1013 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
1014 CLK(NULL, "clkout2_ck", &clkout2_ck),
1015 CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
1016 CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
1017 CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
1018};
1019
1020
1021static const char *enable_init_clks[] = {
1022 "dpll_ddr_m2_ck",
1023 "dpll_mpu_m2_ck",
1024 "l3_gclk",
1025 "l4hs_gclk",
1026 "l4fw_gclk",
1027 "l4ls_gclk",
1028 "clkout2_ck", /* Required for external peripherals like, Audio codecs */
1029};
1030
1031int __init am33xx_clk_init(void)
1032{
1033 if (soc_is_am33xx())
1034 cpu_mask = RATE_IN_AM33XX;
1035
1036 omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
1037
1038 omap2_clk_disable_autoidle_all();
1039
1040 omap2_clk_enable_init_clocks(enable_init_clks,
1041 ARRAY_SIZE(enable_init_clks));
1042
1043 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
1044 * physically present, in such a case HWMOD enabling of
1045 * clock would be failure with default parent. And timer
1046 * probe thinks clock is already enabled, this leads to
1047 * crash upon accessing timer 3 & 6 registers in probe.
1048 * Fix by setting parent of both these timers to master
1049 * oscillator clock.
1050 */
1051
1052 clk_set_parent(&timer3_fck, &sys_clkin_ck);
1053 clk_set_parent(&timer6_fck, &sys_clkin_ck);
1054 /*
1055 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
1056 * the design/spec, so as a result, for example, timer which supposed
1057 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
1058 * not expected by any use-case, so change WDT1 clock source to PRCM
1059 * 32KHz clock.
1060 */
1061 clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
1062
1063 return 0;
1064}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index bbd2959c63d6..f28399f7ed4f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -581,7 +581,7 @@ void __init am33xx_init_early(void)
581 am33xx_clockdomains_init(); 581 am33xx_clockdomains_init();
582 am33xx_hwmod_init(); 582 am33xx_hwmod_init();
583 omap_hwmod_init_postsetup(); 583 omap_hwmod_init_postsetup();
584 omap_clk_soc_init = am33xx_clk_init; 584 omap_clk_soc_init = am33xx_dt_clk_init;
585} 585}
586 586
587void __init am33xx_init_late(void) 587void __init am33xx_init_late(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 03:38:03 -0500