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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-01 23:58:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-01 23:58:25 -0400
commit81a3c10ce8a7fd5bf9a06bfc38bd417512911831 (patch)
tree12ceac10fae8c4b2dc17b362672a5db305a8d960 /arch/arm/mach-omap2
parent6585dea1f99cc2265582ff2e4cc1727062136e92 (diff)
parentdf80442d1ee2902c2e39f90f18160f2e08d14c06 (diff)
Merge branch 'next/cleanup2' of git://git.linaro.org/people/arnd/arm-soc
* 'next/cleanup2' of git://git.linaro.org/people/arnd/arm-soc: (31 commits) ARM: OMAP: Warn if omap_ioremap is called before SoC detection ARM: OMAP: Move set_globals initialization to happen in init_early ARM: OMAP: Map SRAM later on with ioremap_exec() ARM: OMAP: Remove calls to SRAM allocations for framebuffer ARM: OMAP: Avoid cpu_is_omapxxxx usage until map_io is done ARM: OMAP1: Use generic map_io, init_early and init_irq arm/dts: OMAP3+: Add mpu, dsp and iva nodes arm/dts: OMAP4: Add a main ocp entry bound to l3-noc driver ARM: OMAP2+: l3-noc: Add support for device-tree ARM: OMAP2+: board-generic: Add i2c static init ARM: OMAP2+: board-generic: Add DT support to generic board arm/dts: Add support for OMAP3 Beagle board arm/dts: Add initial device tree support for OMAP3 SoC arm/dts: Add support for OMAP4 SDP board arm/dts: Add support for OMAP4 PandaBoard arm/dts: Add initial device tree support for OMAP4 SoC ARM: OMAP: omap_device: Add a method to build an omap_device from a DT node ARM: OMAP: omap_device: Add omap_device_[alloc|delete] for DT integration of: Add helpers to get one string in multiple strings property ARM: OMAP2+: devices: Remove all omap_device_pm_latency structures ... Fix up trivial header file conflicts in arch/arm/mach-omap2/board-generic.c
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig8
-rw-r--r--arch/arm/mach-omap2/board-generic.c159
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c11
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c1
-rw-r--r--arch/arm/mach-omap2/common.c50
-rw-r--r--arch/arm/mach-omap2/control.c14
-rw-r--r--arch/arm/mach-omap2/devices.c51
-rw-r--r--arch/arm/mach-omap2/display.c11
-rw-r--r--arch/arm/mach-omap2/dma.c11
-rw-r--r--arch/arm/mach-omap2/gpio.c12
-rw-r--r--arch/arm/mach-omap2/hsmmc.c18
-rw-r--r--arch/arm/mach-omap2/hwspinlock.c12
-rw-r--r--arch/arm/mach-omap2/io.c129
-rw-r--r--arch/arm/mach-omap2/io.h7
-rw-r--r--arch/arm/mach-omap2/mcbsp.c11
-rw-r--r--arch/arm/mach-omap2/omap-smp.c7
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c147
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h224
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c91
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h164
-rw-r--r--arch/arm/mach-omap2/pm.c72
-rw-r--r--arch/arm/mach-omap2/prcm.c19
-rw-r--r--arch/arm/mach-omap2/sdrc.c13
-rw-r--r--arch/arm/mach-omap2/serial.c25
-rw-r--r--arch/arm/mach-omap2/sr_device.c11
-rw-r--r--arch/arm/mach-omap2/timer.c6
-rw-r--r--arch/arm/mach-omap2/usb-musb.c26
27 files changed, 622 insertions, 688 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 89bfb49389f2..497e9dc27958 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -108,9 +108,13 @@ comment "OMAP Board Type"
108 depends on ARCH_OMAP2PLUS 108 depends on ARCH_OMAP2PLUS
109 109
110config MACH_OMAP_GENERIC 110config MACH_OMAP_GENERIC
111 bool "Generic OMAP board" 111 bool "Generic OMAP2+ board"
112 depends on ARCH_OMAP2 112 depends on ARCH_OMAP2PLUS
113 select USE_OF
113 default y 114 default y
115 help
116 Support for generic TI OMAP2+ boards using Flattened Device Tree.
117 More information at Documentation/devicetree
114 118
115config MACH_OMAP2_TUSB6010 119config MACH_OMAP2_TUSB6010
116 bool 120 bool
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 7ac546219e5d..0c427976d62f 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -1,75 +1,158 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/board-generic.c
3 *
4 * Copyright (C) 2005 Nokia Corporation 2 * Copyright (C) 2005 Nokia Corporation
5 * Author: Paul Mundt <paul.mundt@nokia.com> 3 * Author: Paul Mundt <paul.mundt@nokia.com>
6 * 4 *
7 * Modified from mach-omap/omap1/board-generic.c 5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 * 6 *
9 * Code for generic OMAP2 board. Should work on many OMAP2 systems where 7 * Modified from the original mach-omap/omap2/board-generic.c did by Paul
10 * the bootloader passes the board-specific data to the kernel. 8 * to support the OMAP2+ device tree boards with an unique board file.
11 * Do not put any board specific code to this file; create a new machine
12 * type if you need custom low-level initializations.
13 * 9 *
14 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
17 */ 13 */
18#include <linux/gpio.h> 14
19#include <linux/kernel.h> 15#include <linux/io.h>
20#include <linux/init.h> 16#include <linux/of_platform.h>
21#include <linux/device.h> 17#include <linux/irqdomain.h>
18#include <linux/i2c/twl.h>
22 19
23#include <mach/hardware.h> 20#include <mach/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27 22
28#include <plat/usb.h>
29#include <plat/board.h> 23#include <plat/board.h>
30#include <plat/common.h> 24#include <plat/common.h>
25#include <mach/omap4-common.h>
26#include "common-board-devices.h"
31 27
32static struct omap_board_config_kernel generic_config[] = { 28/*
29 * XXX: Still needed to boot until the i2c & twl driver is adapted to
30 * device-tree
31 */
32static struct twl4030_platform_data sdp4430_twldata = {
33 .irq_base = TWL6030_IRQ_BASE,
34 .irq_end = TWL6030_IRQ_END,
33}; 35};
34 36
35static void __init omap_generic_init_early(void) 37static void __init omap4_i2c_init(void)
36{ 38{
37 omap2_init_common_infrastructure(); 39 omap4_pmic_init("twl6030", &sdp4430_twldata);
38} 40}
39 41
42static struct twl4030_platform_data beagle_twldata = {
43 .irq_base = TWL4030_IRQ_BASE,
44 .irq_end = TWL4030_IRQ_END,
45};
46
47static void __init omap3_i2c_init(void)
48{
49 omap3_pmic_init("twl4030", &beagle_twldata);
50}
51
52static struct of_device_id omap_dt_match_table[] __initdata = {
53 { .compatible = "simple-bus", },
54 { .compatible = "ti,omap-infra", },
55 { }
56};
57
58static struct of_device_id intc_match[] __initdata = {
59 { .compatible = "ti,omap3-intc", },
60 { .compatible = "arm,cortex-a9-gic", },
61 { }
62};
63
40static void __init omap_generic_init(void) 64static void __init omap_generic_init(void)
41{ 65{
66 struct device_node *node = of_find_matching_node(NULL, intc_match);
67 if (node)
68 irq_domain_add_simple(node, 0);
69
42 omap_serial_init(); 70 omap_serial_init();
43 omap_sdrc_init(NULL, NULL); 71 omap_sdrc_init(NULL, NULL);
44 omap_board_config = generic_config; 72
45 omap_board_config_size = ARRAY_SIZE(generic_config); 73 of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
74}
75
76static void __init omap4_init(void)
77{
78 omap4_i2c_init();
79 omap_generic_init();
46} 80}
47 81
48static void __init omap_generic_map_io(void) 82static void __init omap3_init(void)
49{ 83{
50 if (cpu_is_omap242x()) { 84 omap3_i2c_init();
51 omap2_set_globals_242x(); 85 omap_generic_init();
52 omap242x_map_common_io();
53 } else if (cpu_is_omap243x()) {
54 omap2_set_globals_243x();
55 omap243x_map_common_io();
56 } else if (cpu_is_omap34xx()) {
57 omap2_set_globals_3xxx();
58 omap34xx_map_common_io();
59 } else if (cpu_is_omap44xx()) {
60 omap2_set_globals_443x();
61 omap44xx_map_common_io();
62 }
63} 86}
64 87
65/* XXX This machine entry name should be updated */ 88#if defined(CONFIG_SOC_OMAP2420)
66MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") 89static const char *omap242x_boards_compat[] __initdata = {
67 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 90 "ti,omap2420",
91 NULL,
92};
93
94DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
68 .atag_offset = 0x100, 95 .atag_offset = 0x100,
69 .reserve = omap_reserve, 96 .reserve = omap_reserve,
70 .map_io = omap_generic_map_io, 97 .map_io = omap242x_map_io,
71 .init_early = omap_generic_init_early, 98 .init_early = omap2420_init_early,
72 .init_irq = omap2_init_irq, 99 .init_irq = omap2_init_irq,
73 .init_machine = omap_generic_init, 100 .init_machine = omap_generic_init,
74 .timer = &omap2_timer, 101 .timer = &omap2_timer,
102 .dt_compat = omap242x_boards_compat,
103MACHINE_END
104#endif
105
106#if defined(CONFIG_SOC_OMAP2430)
107static const char *omap243x_boards_compat[] __initdata = {
108 "ti,omap2430",
109 NULL,
110};
111
112DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
113 .atag_offset = 0x100,
114 .reserve = omap_reserve,
115 .map_io = omap243x_map_io,
116 .init_early = omap2430_init_early,
117 .init_irq = omap2_init_irq,
118 .init_machine = omap_generic_init,
119 .timer = &omap2_timer,
120 .dt_compat = omap243x_boards_compat,
121MACHINE_END
122#endif
123
124#if defined(CONFIG_ARCH_OMAP3)
125static const char *omap3_boards_compat[] __initdata = {
126 "ti,omap3",
127 NULL,
128};
129
130DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
131 .atag_offset = 0x100,
132 .reserve = omap_reserve,
133 .map_io = omap3_map_io,
134 .init_early = omap3430_init_early,
135 .init_irq = omap3_init_irq,
136 .init_machine = omap3_init,
137 .timer = &omap3_timer,
138 .dt_compat = omap3_boards_compat,
139MACHINE_END
140#endif
141
142#if defined(CONFIG_ARCH_OMAP4)
143static const char *omap4_boards_compat[] __initdata = {
144 "ti,omap4",
145 NULL,
146};
147
148DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
149 .atag_offset = 0x100,
150 .reserve = omap_reserve,
151 .map_io = omap4_map_io,
152 .init_early = omap4430_init_early,
153 .init_irq = gic_init_irq,
154 .init_machine = omap4_init,
155 .timer = &omap4_timer,
156 .dt_compat = omap4_boards_compat,
75MACHINE_END 157MACHINE_END
158#endif
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 474a7e2cb638..70261bcda3f9 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -444,11 +444,6 @@ static struct platform_device keys_gpio = {
444 }, 444 },
445}; 445};
446 446
447static void __init omap3_beagle_init_early(void)
448{
449 omap2_init_common_infrastructure();
450}
451
452static struct platform_device *omap3_beagle_devices[] __initdata = { 447static struct platform_device *omap3_beagle_devices[] __initdata = {
453 &leds_gpio, 448 &leds_gpio,
454 &keys_gpio, 449 &keys_gpio,
@@ -486,8 +481,8 @@ static void __init beagle_opp_init(void)
486 if (cpu_is_omap3630()) { 481 if (cpu_is_omap3630()) {
487 struct device *mpu_dev, *iva_dev; 482 struct device *mpu_dev, *iva_dev;
488 483
489 mpu_dev = omap2_get_mpuss_device(); 484 mpu_dev = omap_device_get_by_hwmod_name("mpu");
490 iva_dev = omap2_get_iva_device(); 485 iva_dev = omap_device_get_by_hwmod_name("iva");
491 486
492 if (!mpu_dev || !iva_dev) { 487 if (!mpu_dev || !iva_dev) {
493 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n", 488 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
@@ -555,7 +550,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
555 .atag_offset = 0x100, 550 .atag_offset = 0x100,
556 .reserve = omap_reserve, 551 .reserve = omap_reserve,
557 .map_io = omap3_map_io, 552 .map_io = omap3_map_io,
558 .init_early = omap3_beagle_init_early, 553 .init_early = omap3_init_early,
559 .init_irq = omap3_init_irq, 554 .init_irq = omap3_init_irq,
560 .init_machine = omap3_beagle_init, 555 .init_machine = omap3_beagle_init,
561 .timer = &omap3_secure_timer, 556 .timer = &omap3_secure_timer,
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index e26c79cb6ce9..e6ee8842285c 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -37,7 +37,6 @@ static void __init ti8168_evm_init(void)
37 37
38static void __init ti8168_evm_map_io(void) 38static void __init ti8168_evm_map_io(void)
39{ 39{
40 omap2_set_globals_ti816x();
41 omapti816x_map_common_io(); 40 omapti816x_map_common_io();
42} 41}
43 42
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index de61f15c48e2..110e5b9db145 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -45,11 +45,11 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
45static struct omap_globals omap242x_globals = { 45static struct omap_globals omap242x_globals = {
46 .class = OMAP242X_CLASS, 46 .class = OMAP242X_CLASS,
47 .tap = OMAP2_L4_IO_ADDRESS(0x48014000), 47 .tap = OMAP2_L4_IO_ADDRESS(0x48014000),
48 .sdrc = OMAP2420_SDRC_BASE, 48 .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
49 .sms = OMAP2420_SMS_BASE, 49 .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
50 .ctrl = OMAP242X_CTRL_BASE, 50 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
51 .prm = OMAP2420_PRM_BASE, 51 .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
52 .cm = OMAP2420_CM_BASE, 52 .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
53}; 53};
54 54
55void __init omap2_set_globals_242x(void) 55void __init omap2_set_globals_242x(void)
@@ -59,7 +59,6 @@ void __init omap2_set_globals_242x(void)
59 59
60void __init omap242x_map_io(void) 60void __init omap242x_map_io(void)
61{ 61{
62 omap2_set_globals_242x();
63 omap242x_map_common_io(); 62 omap242x_map_common_io();
64} 63}
65#endif 64#endif
@@ -69,11 +68,11 @@ void __init omap242x_map_io(void)
69static struct omap_globals omap243x_globals = { 68static struct omap_globals omap243x_globals = {
70 .class = OMAP243X_CLASS, 69 .class = OMAP243X_CLASS,
71 .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), 70 .tap = OMAP2_L4_IO_ADDRESS(0x4900a000),
72 .sdrc = OMAP243X_SDRC_BASE, 71 .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
73 .sms = OMAP243X_SMS_BASE, 72 .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
74 .ctrl = OMAP243X_CTRL_BASE, 73 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
75 .prm = OMAP2430_PRM_BASE, 74 .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
76 .cm = OMAP2430_CM_BASE, 75 .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
77}; 76};
78 77
79void __init omap2_set_globals_243x(void) 78void __init omap2_set_globals_243x(void)
@@ -83,7 +82,6 @@ void __init omap2_set_globals_243x(void)
83 82
84void __init omap243x_map_io(void) 83void __init omap243x_map_io(void)
85{ 84{
86 omap2_set_globals_243x();
87 omap243x_map_common_io(); 85 omap243x_map_common_io();
88} 86}
89#endif 87#endif
@@ -93,11 +91,11 @@ void __init omap243x_map_io(void)
93static struct omap_globals omap3_globals = { 91static struct omap_globals omap3_globals = {
94 .class = OMAP343X_CLASS, 92 .class = OMAP343X_CLASS,
95 .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), 93 .tap = OMAP2_L4_IO_ADDRESS(0x4830A000),
96 .sdrc = OMAP343X_SDRC_BASE, 94 .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
97 .sms = OMAP343X_SMS_BASE, 95 .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
98 .ctrl = OMAP343X_CTRL_BASE, 96 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
99 .prm = OMAP3430_PRM_BASE, 97 .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
100 .cm = OMAP3430_CM_BASE, 98 .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
101}; 99};
102 100
103void __init omap2_set_globals_3xxx(void) 101void __init omap2_set_globals_3xxx(void)
@@ -107,7 +105,6 @@ void __init omap2_set_globals_3xxx(void)
107 105
108void __init omap3_map_io(void) 106void __init omap3_map_io(void)
109{ 107{
110 omap2_set_globals_3xxx();
111 omap34xx_map_common_io(); 108 omap34xx_map_common_io();
112} 109}
113 110
@@ -122,9 +119,9 @@ void __init omap3_map_io(void)
122static struct omap_globals ti816x_globals = { 119static struct omap_globals ti816x_globals = {
123 .class = OMAP343X_CLASS, 120 .class = OMAP343X_CLASS,
124 .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), 121 .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
125 .ctrl = TI816X_CTRL_BASE, 122 .ctrl = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
126 .prm = TI816X_PRCM_BASE, 123 .prm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
127 .cm = TI816X_PRCM_BASE, 124 .cm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
128}; 125};
129 126
130void __init omap2_set_globals_ti816x(void) 127void __init omap2_set_globals_ti816x(void)
@@ -137,11 +134,11 @@ void __init omap2_set_globals_ti816x(void)
137static struct omap_globals omap4_globals = { 134static struct omap_globals omap4_globals = {
138 .class = OMAP443X_CLASS, 135 .class = OMAP443X_CLASS,
139 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 136 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
140 .ctrl = OMAP443X_SCM_BASE, 137 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
141 .ctrl_pad = OMAP443X_CTRL_BASE, 138 .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
142 .prm = OMAP4430_PRM_BASE, 139 .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
143 .cm = OMAP4430_CM_BASE, 140 .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
144 .cm2 = OMAP4430_CM2_BASE, 141 .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
145}; 142};
146 143
147void __init omap2_set_globals_443x(void) 144void __init omap2_set_globals_443x(void)
@@ -153,7 +150,6 @@ void __init omap2_set_globals_443x(void)
153 150
154void __init omap4_map_io(void) 151void __init omap4_map_io(void)
155{ 152{
156 omap2_set_globals_443x();
157 omap44xx_map_common_io(); 153 omap44xx_map_common_io();
158} 154}
159#endif 155#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index aab884fecc55..e34d27f8c49c 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -149,17 +149,11 @@ static struct omap3_control_regs control_context;
149 149
150void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 150void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
151{ 151{
152 /* Static mapping, never released */ 152 if (omap2_globals->ctrl)
153 if (omap2_globals->ctrl) { 153 omap2_ctrl_base = omap2_globals->ctrl;
154 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
155 WARN_ON(!omap2_ctrl_base);
156 }
157 154
158 /* Static mapping, never released */ 155 if (omap2_globals->ctrl_pad)
159 if (omap2_globals->ctrl_pad) { 156 omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
160 omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
161 WARN_ON(!omap4_ctrl_pad_base);
162 }
163} 157}
164 158
165void __iomem *omap_ctrl_base_get(void) 159void __iomem *omap_ctrl_base_get(void)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 406b56cfedbc..68ec03152d5f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -16,6 +16,7 @@
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/of.h>
19 20
20#include <mach/hardware.h> 21#include <mach/hardware.h>
21#include <mach/irqs.h> 22#include <mach/irqs.h>
@@ -76,6 +77,10 @@ static int __init omap4_l3_init(void)
76 struct platform_device *pdev; 77 struct platform_device *pdev;
77 char oh_name[L3_MODULES_MAX_LEN]; 78 char oh_name[L3_MODULES_MAX_LEN];
78 79
80 /* If dtb is there, the devices will be created dynamically */
81 if (of_have_populated_dt())
82 return -ENODEV;
83
79 /* 84 /*
80 * To avoid code running on other OMAPs in 85 * To avoid code running on other OMAPs in
81 * multi-omap builds 86 * multi-omap builds
@@ -220,14 +225,6 @@ static inline void omap_init_camera(void)
220#endif 225#endif
221} 226}
222 227
223struct omap_device_pm_latency omap_keyboard_latency[] = {
224 {
225 .deactivate_func = omap_device_idle_hwmods,
226 .activate_func = omap_device_enable_hwmods,
227 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
228 },
229};
230
231int __init omap4_keyboard_init(struct omap4_keypad_platform_data 228int __init omap4_keyboard_init(struct omap4_keypad_platform_data
232 *sdp4430_keypad_data, struct omap_board_data *bdata) 229 *sdp4430_keypad_data, struct omap_board_data *bdata)
233{ 230{
@@ -247,9 +244,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
247 keypad_data = sdp4430_keypad_data; 244 keypad_data = sdp4430_keypad_data;
248 245
249 pdev = omap_device_build(name, id, oh, keypad_data, 246 pdev = omap_device_build(name, id, oh, keypad_data,
250 sizeof(struct omap4_keypad_platform_data), 247 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
251 omap_keyboard_latency,
252 ARRAY_SIZE(omap_keyboard_latency), 0);
253 248
254 if (IS_ERR(pdev)) { 249 if (IS_ERR(pdev)) {
255 WARN(1, "Can't build omap_device for %s:%s.\n", 250 WARN(1, "Can't build omap_device for %s:%s.\n",
@@ -262,14 +257,6 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
262} 257}
263 258
264#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 259#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
265static struct omap_device_pm_latency mbox_latencies[] = {
266 [0] = {
267 .activate_func = omap_device_enable_hwmods,
268 .deactivate_func = omap_device_idle_hwmods,
269 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
270 },
271};
272
273static inline void omap_init_mbox(void) 260static inline void omap_init_mbox(void)
274{ 261{
275 struct omap_hwmod *oh; 262 struct omap_hwmod *oh;
@@ -281,8 +268,7 @@ static inline void omap_init_mbox(void)
281 return; 268 return;
282 } 269 }
283 270
284 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, 271 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
285 mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
286 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", 272 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
287 __func__, PTR_ERR(pdev)); 273 __func__, PTR_ERR(pdev));
288} 274}
@@ -365,14 +351,6 @@ static inline void omap_init_mcpdm(void) {}
365 351
366#include <plat/mcspi.h> 352#include <plat/mcspi.h>
367 353
368struct omap_device_pm_latency omap_mcspi_latency[] = {
369 [0] = {
370 .deactivate_func = omap_device_idle_hwmods,
371 .activate_func = omap_device_enable_hwmods,
372 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
373 },
374};
375
376static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) 354static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
377{ 355{
378 struct platform_device *pdev; 356 struct platform_device *pdev;
@@ -403,8 +381,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
403 381
404 spi_num++; 382 spi_num++;
405 pdev = omap_device_build(name, spi_num, oh, pdata, 383 pdev = omap_device_build(name, spi_num, oh, pdata,
406 sizeof(*pdata), omap_mcspi_latency, 384 sizeof(*pdata), NULL, 0, 0);
407 ARRAY_SIZE(omap_mcspi_latency), 0);
408 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", 385 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
409 name, oh->name); 386 name, oh->name);
410 kfree(pdata); 387 kfree(pdata);
@@ -730,14 +707,6 @@ static int __init omap2_init_devices(void)
730arch_initcall(omap2_init_devices); 707arch_initcall(omap2_init_devices);
731 708
732#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) 709#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
733static struct omap_device_pm_latency omap_wdt_latency[] = {
734 [0] = {
735 .deactivate_func = omap_device_idle_hwmods,
736 .activate_func = omap_device_enable_hwmods,
737 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
738 },
739};
740
741static int __init omap_init_wdt(void) 710static int __init omap_init_wdt(void)
742{ 711{
743 int id = -1; 712 int id = -1;
@@ -755,9 +724,7 @@ static int __init omap_init_wdt(void)
755 return -EINVAL; 724 return -EINVAL;
756 } 725 }
757 726
758 pdev = omap_device_build(dev_name, id, oh, NULL, 0, 727 pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
759 omap_wdt_latency,
760 ARRAY_SIZE(omap_wdt_latency), 0);
761 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", 728 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
762 dev_name, oh->name); 729 dev_name, oh->name);
763 return 0; 730 return 0;
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 836f0f7d8c00..4036821a01f3 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -37,14 +37,6 @@ static struct platform_device omap_display_device = {
37 }, 37 },
38}; 38};
39 39
40static struct omap_device_pm_latency omap_dss_latency[] = {
41 [0] = {
42 .deactivate_func = omap_device_idle_hwmods,
43 .activate_func = omap_device_enable_hwmods,
44 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
45 },
46};
47
48struct omap_dss_hwmod_data { 40struct omap_dss_hwmod_data {
49 const char *oh_name; 41 const char *oh_name;
50 const char *dev_name; 42 const char *dev_name;
@@ -165,8 +157,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
165 pdev = omap_device_build(curr_dss_hwmod[i].dev_name, 157 pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
166 curr_dss_hwmod[i].id, oh, &pdata, 158 curr_dss_hwmod[i].id, oh, &pdata,
167 sizeof(struct omap_display_platform_data), 159 sizeof(struct omap_display_platform_data),
168 omap_dss_latency, 160 NULL, 0, 0);
169 ARRAY_SIZE(omap_dss_latency), 0);
170 161
171 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n", 162 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
172 curr_dss_hwmod[i].oh_name)) 163 curr_dss_hwmod[i].oh_name))
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index ae8cb3fb1830..a59a45a0096e 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -87,14 +87,6 @@ static u16 reg_map[] = {
87 [CCDN] = 0xd8, 87 [CCDN] = 0xd8,
88}; 88};
89 89
90static struct omap_device_pm_latency omap2_dma_latency[] = {
91 {
92 .deactivate_func = omap_device_idle_hwmods,
93 .activate_func = omap_device_enable_hwmods,
94 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
95 },
96};
97
98static void __iomem *dma_base; 90static void __iomem *dma_base;
99static inline void dma_write(u32 val, int reg, int lch) 91static inline void dma_write(u32 val, int reg, int lch)
100{ 92{
@@ -258,8 +250,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
258 250
259 p->errata = configure_dma_errata(); 251 p->errata = configure_dma_errata();
260 252
261 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), 253 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
262 omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
263 kfree(p); 254 kfree(p);
264 if (IS_ERR(pdev)) { 255 if (IS_ERR(pdev)) {
265 pr_err("%s: Can't build omap_device for %s:%s.\n", 256 pr_err("%s: Can't build omap_device for %s:%s.\n",
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 652ccc574196..8cbfbc2918ce 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -24,14 +24,6 @@
24#include <plat/omap_hwmod.h> 24#include <plat/omap_hwmod.h>
25#include <plat/omap_device.h> 25#include <plat/omap_device.h>
26 26
27static struct omap_device_pm_latency omap_gpio_latency[] = {
28 [0] = {
29 .deactivate_func = omap_device_idle_hwmods,
30 .activate_func = omap_device_enable_hwmods,
31 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
32 },
33};
34
35static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) 27static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
36{ 28{
37 struct platform_device *pdev; 29 struct platform_device *pdev;
@@ -108,9 +100,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
108 } 100 }
109 101
110 pdev = omap_device_build(name, id - 1, oh, pdata, 102 pdev = omap_device_build(name, id - 1, oh, pdata,
111 sizeof(*pdata), omap_gpio_latency, 103 sizeof(*pdata), NULL, 0, false);
112 ARRAY_SIZE(omap_gpio_latency),
113 false);
114 kfree(pdata); 104 kfree(pdata);
115 105
116 if (IS_ERR(pdev)) { 106 if (IS_ERR(pdev)) {
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 2dc002a388b3..77085847e4e7 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -409,31 +409,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
409 return 0; 409 return 0;
410} 410}
411 411
412static struct omap_device_pm_latency omap_hsmmc_latency[] = {
413 [0] = {
414 .deactivate_func = omap_device_idle_hwmods,
415 .activate_func = omap_device_enable_hwmods,
416 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
417 },
418 /*
419 * XXX There should also be an entry here to power off/on the
420 * MMC regulators/PBIAS cells, etc.
421 */
422};
423
424#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 412#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
425 413
426void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) 414void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
427{ 415{
428 struct omap_hwmod *oh; 416 struct omap_hwmod *oh;
429 struct platform_device *pdev; 417 struct platform_device *pdev;
430 struct omap_device_pm_latency *ohl;
431 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; 418 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
432 struct omap_mmc_platform_data *mmc_data; 419 struct omap_mmc_platform_data *mmc_data;
433 struct omap_mmc_dev_attr *mmc_dev_attr; 420 struct omap_mmc_dev_attr *mmc_dev_attr;
434 char *name; 421 char *name;
435 int l; 422 int l;
436 int ohl_cnt = 0;
437 423
438 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); 424 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
439 if (!mmc_data) { 425 if (!mmc_data) {
@@ -448,8 +434,6 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
448 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); 434 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
449 435
450 name = "omap_hsmmc"; 436 name = "omap_hsmmc";
451 ohl = omap_hsmmc_latency;
452 ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
453 437
454 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, 438 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
455 "mmc%d", ctrl_nr); 439 "mmc%d", ctrl_nr);
@@ -468,7 +452,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
468 } 452 }
469 453
470 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, 454 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
471 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); 455 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
472 if (IS_ERR(pdev)) { 456 if (IS_ERR(pdev)) {
473 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); 457 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
474 kfree(mmc_data->slots[0].name); 458 kfree(mmc_data->slots[0].name);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 0b3ae9d9c3b3..36e21091b06a 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -23,14 +23,6 @@
23#include <plat/omap_hwmod.h> 23#include <plat/omap_hwmod.h>
24#include <plat/omap_device.h> 24#include <plat/omap_device.h>
25 25
26struct omap_device_pm_latency omap_spinlock_latency[] = {
27 {
28 .deactivate_func = omap_device_idle_hwmods,
29 .activate_func = omap_device_enable_hwmods,
30 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
31 }
32};
33
34int __init hwspinlocks_init(void) 26int __init hwspinlocks_init(void)
35{ 27{
36 int retval = 0; 28 int retval = 0;
@@ -48,9 +40,7 @@ int __init hwspinlocks_init(void)
48 if (oh == NULL) 40 if (oh == NULL)
49 return -EINVAL; 41 return -EINVAL;
50 42
51 pdev = omap_device_build(dev_name, 0, oh, NULL, 0, 43 pdev = omap_device_build(dev_name, 0, oh, NULL, 0, NULL, 0, false);
52 omap_spinlock_latency,
53 ARRAY_SIZE(omap_spinlock_latency), false);
54 if (IS_ERR(pdev)) { 44 if (IS_ERR(pdev)) {
55 pr_err("Can't build omap_device for %s:%s\n", dev_name, 45 pr_err("Can't build omap_device for %s:%s\n", dev_name,
56 oh_name); 46 oh_name);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f01273006e4d..a5d8dce2a70b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -34,8 +34,8 @@
34#include "clock2xxx.h" 34#include "clock2xxx.h"
35#include "clock3xxx.h" 35#include "clock3xxx.h"
36#include "clock44xx.h" 36#include "clock44xx.h"
37#include "io.h"
38 37
38#include <plat/common.h>
39#include <plat/omap-pm.h> 39#include <plat/omap-pm.h>
40#include "voltage.h" 40#include "voltage.h"
41#include "powerdomain.h" 41#include "powerdomain.h"
@@ -43,6 +43,7 @@
43#include "clockdomain.h" 43#include "clockdomain.h"
44#include <plat/omap_hwmod.h> 44#include <plat/omap_hwmod.h>
45#include <plat/multi.h> 45#include <plat/multi.h>
46#include <plat/common.h>
46 47
47/* 48/*
48 * The machine specific code may provide the extra mapping besides the 49 * The machine specific code may provide the extra mapping besides the
@@ -239,26 +240,11 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
239}; 240};
240#endif 241#endif
241 242
242static void __init _omap2_map_common_io(void)
243{
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
247 */
248 local_flush_tlb_all();
249 flush_cache_all();
250
251 omap2_check_revision();
252 omap_sram_init();
253 omap_init_consistent_dma_size();
254}
255
256#ifdef CONFIG_SOC_OMAP2420 243#ifdef CONFIG_SOC_OMAP2420
257void __init omap242x_map_common_io(void) 244void __init omap242x_map_common_io(void)
258{ 245{
259 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 246 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
260 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 247 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
261 _omap2_map_common_io();
262} 248}
263#endif 249#endif
264 250
@@ -267,7 +253,6 @@ void __init omap243x_map_common_io(void)
267{ 253{
268 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 254 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
269 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 255 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
270 _omap2_map_common_io();
271} 256}
272#endif 257#endif
273 258
@@ -275,7 +260,6 @@ void __init omap243x_map_common_io(void)
275void __init omap34xx_map_common_io(void) 260void __init omap34xx_map_common_io(void)
276{ 261{
277 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 262 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
278 _omap2_map_common_io();
279} 263}
280#endif 264#endif
281 265
@@ -283,7 +267,6 @@ void __init omap34xx_map_common_io(void)
283void __init omapti816x_map_common_io(void) 267void __init omapti816x_map_common_io(void)
284{ 268{
285 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); 269 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
286 _omap2_map_common_io();
287} 270}
288#endif 271#endif
289 272
@@ -291,7 +274,6 @@ void __init omapti816x_map_common_io(void)
291void __init omap44xx_map_common_io(void) 274void __init omap44xx_map_common_io(void)
292{ 275{
293 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 276 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
294 _omap2_map_common_io();
295} 277}
296#endif 278#endif
297 279
@@ -337,33 +319,16 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
337/* See irq.c, omap4-common.c and entry-macro.S */ 319/* See irq.c, omap4-common.c and entry-macro.S */
338void __iomem *omap_irq_base; 320void __iomem *omap_irq_base;
339 321
340void __init omap2_init_common_infrastructure(void) 322static void __init omap_common_init_early(void)
341{ 323{
342 u8 postsetup_state; 324 omap2_check_revision();
325 omap_ioremap_init();
326 omap_init_consistent_dma_size();
327}
343 328
344 if (cpu_is_omap242x()) { 329static void __init omap_hwmod_init_postsetup(void)
345 omap2xxx_voltagedomains_init(); 330{
346 omap242x_powerdomains_init(); 331 u8 postsetup_state;
347 omap242x_clockdomains_init();
348 omap2420_hwmod_init();
349 } else if (cpu_is_omap243x()) {
350 omap2xxx_voltagedomains_init();
351 omap243x_powerdomains_init();
352 omap243x_clockdomains_init();
353 omap2430_hwmod_init();
354 } else if (cpu_is_omap34xx()) {
355 omap3xxx_voltagedomains_init();
356 omap3xxx_powerdomains_init();
357 omap3xxx_clockdomains_init();
358 omap3xxx_hwmod_init();
359 } else if (cpu_is_omap44xx()) {
360 omap44xx_voltagedomains_init();
361 omap44xx_powerdomains_init();
362 omap44xx_clockdomains_init();
363 omap44xx_hwmod_init();
364 } else {
365 pr_err("Could not init hwmod data - unknown SoC\n");
366 }
367 332
368 /* Set the default postsetup state for all hwmods */ 333 /* Set the default postsetup state for all hwmods */
369#ifdef CONFIG_PM_RUNTIME 334#ifdef CONFIG_PM_RUNTIME
@@ -392,67 +357,101 @@ void __init omap2_init_common_infrastructure(void)
392 &postsetup_state); 357 &postsetup_state);
393 358
394 omap_pm_if_early_init(); 359 omap_pm_if_early_init();
395
396 if (cpu_is_omap2420())
397 omap2420_clk_init();
398 else if (cpu_is_omap2430())
399 omap2430_clk_init();
400 else if (cpu_is_omap34xx())
401 omap3xxx_clk_init();
402 else if (cpu_is_omap44xx())
403 omap4xxx_clk_init();
404 else
405 pr_err("Could not init clock framework - unknown SoC\n");
406} 360}
407 361
408void __init omap2420_init_early(void) 362void __init omap2420_init_early(void)
409{ 363{
410 omap2_init_common_infrastructure(); 364 omap2_set_globals_242x();
365 omap_common_init_early();
366 omap2xxx_voltagedomains_init();
367 omap242x_powerdomains_init();
368 omap242x_clockdomains_init();
369 omap2420_hwmod_init();
370 omap_hwmod_init_postsetup();
371 omap2420_clk_init();
411} 372}
412 373
413void __init omap2430_init_early(void) 374void __init omap2430_init_early(void)
414{ 375{
415 omap2_init_common_infrastructure(); 376 omap2_set_globals_243x();
377 omap_common_init_early();
378 omap2xxx_voltagedomains_init();
379 omap243x_powerdomains_init();
380 omap243x_clockdomains_init();
381 omap2430_hwmod_init();
382 omap_hwmod_init_postsetup();
383 omap2430_clk_init();
384}
385
386/*
387 * Currently only board-omap3beagle.c should call this because of the
388 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
389 */
390void __init omap3_init_early(void)
391{
392 omap2_set_globals_3xxx();
393 omap_common_init_early();
394 omap3xxx_voltagedomains_init();
395 omap3xxx_powerdomains_init();
396 omap3xxx_clockdomains_init();
397 omap3xxx_hwmod_init();
398 omap_hwmod_init_postsetup();
399 omap3xxx_clk_init();
416} 400}
417 401
418void __init omap3430_init_early(void) 402void __init omap3430_init_early(void)
419{ 403{
420 omap2_init_common_infrastructure(); 404 omap3_init_early();
421} 405}
422 406
423void __init omap35xx_init_early(void) 407void __init omap35xx_init_early(void)
424{ 408{
425 omap2_init_common_infrastructure(); 409 omap3_init_early();
426} 410}
427 411
428void __init omap3630_init_early(void) 412void __init omap3630_init_early(void)
429{ 413{
430 omap2_init_common_infrastructure(); 414 omap3_init_early();
431} 415}
432 416
433void __init am35xx_init_early(void) 417void __init am35xx_init_early(void)
434{ 418{
435 omap2_init_common_infrastructure(); 419 omap3_init_early();
436} 420}
437 421
438void __init ti816x_init_early(void) 422void __init ti816x_init_early(void)
439{ 423{
440 omap2_init_common_infrastructure(); 424 omap2_set_globals_ti816x();
425 omap_common_init_early();
426 omap3xxx_voltagedomains_init();
427 omap3xxx_powerdomains_init();
428 omap3xxx_clockdomains_init();
429 omap3xxx_hwmod_init();
430 omap_hwmod_init_postsetup();
431 omap3xxx_clk_init();
441} 432}
442 433
443void __init omap4430_init_early(void) 434void __init omap4430_init_early(void)
444{ 435{
445 omap2_init_common_infrastructure(); 436 omap2_set_globals_443x();
437 omap_common_init_early();
438 omap44xx_voltagedomains_init();
439 omap44xx_powerdomains_init();
440 omap44xx_clockdomains_init();
441 omap44xx_hwmod_init();
442 omap_hwmod_init_postsetup();
443 omap4xxx_clk_init();
446} 444}
447 445
448void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 446void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
449 struct omap_sdrc_params *sdrc_cs1) 447 struct omap_sdrc_params *sdrc_cs1)
450{ 448{
449 omap_sram_init();
450
451 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 451 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
452 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 452 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
453 _omap2_init_reprogram_sdrc(); 453 _omap2_init_reprogram_sdrc();
454 } 454 }
455
456} 455}
457 456
458/* 457/*
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
index fd230c6cded5..e69de29bb2d1 100644
--- a/arch/arm/mach-omap2/io.h
+++ b/arch/arm/mach-omap2/io.h
@@ -1,7 +0,0 @@
1
2#ifndef __MACH_OMAP2_IO_H__
3#define __MACH_OMAP2_IO_H__
4
5extern int __init omap_sram_init(void);
6
7#endif /* __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 5063f253c4b9..292eee3be15f 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -122,14 +122,6 @@ static int omap3_enable_st_clock(unsigned int id, bool enable)
122 return 0; 122 return 0;
123} 123}
124 124
125struct omap_device_pm_latency omap2_mcbsp_latency[] = {
126 {
127 .deactivate_func = omap_device_idle_hwmods,
128 .activate_func = omap_device_enable_hwmods,
129 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
130 },
131};
132
133static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) 125static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
134{ 126{
135 int id, count = 1; 127 int id, count = 1;
@@ -175,8 +167,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
175 count++; 167 count++;
176 } 168 }
177 pdev = omap_device_build_ss(name, id, oh_device, count, pdata, 169 pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
178 sizeof(*pdata), omap2_mcbsp_latency, 170 sizeof(*pdata), NULL, 0, false);
179 ARRAY_SIZE(omap2_mcbsp_latency), false);
180 kfree(pdata); 171 kfree(pdata);
181 if (IS_ERR(pdev)) { 172 if (IS_ERR(pdev)) {
182 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, 173 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 889464dc7b2d..4412ddb7b3f6 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -102,8 +102,11 @@ void __init smp_init_cpus(void)
102{ 102{
103 unsigned int i, ncores; 103 unsigned int i, ncores;
104 104
105 /* Never released */ 105 /*
106 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256); 106 * Currently we can't call ioremap here because
107 * SoC detection won't work until after init_early.
108 */
109 scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
107 BUG_ON(!scu_base); 110 BUG_ON(!scu_base);
108 111
109 ncores = scu_get_core_count(scu_base); 112 ncores = scu_get_core_count(scu_base);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index 7b9f1909ddb2..c8b1bef92e5a 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -1,25 +1,25 @@
1/* 1/*
2 * OMAP4XXX L3 Interconnect error handling driver 2 * OMAP4XXX L3 Interconnect error handling driver
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com> 6 * Sricharan <r.sricharan@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA 21 * USA
22 */ 22 */
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
@@ -55,12 +55,12 @@
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3) 55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{ 56{
57 57
58 struct omap4_l3 *l3 = _l3; 58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j; 59 int inttype, i, k;
60 int err_src = 0; 60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg; 61 u32 std_err_main, err_reg, clear, masterid;
62 u32 base, slave_addr, clear; 62 void __iomem *base, *l3_targ_base;
63 char *source_name; 63 char *target_name, *master_name = "UN IDENTIFIED";
64 64
65 /* Get the Type of interrupt */ 65 /* Get the Type of interrupt */
66 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; 66 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
@@ -70,43 +70,50 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
70 * Read the regerr register of the clock domain 70 * Read the regerr register of the clock domain
71 * to determine the source 71 * to determine the source
72 */ 72 */
73 base = (u32)l3->l3_base[i]; 73 base = l3->l3_base[i];
74 err_reg = readl(base + l3_flagmux[i] + (inttype << 3)); 74 err_reg = __raw_readl(base + l3_flagmux[i] +
75 + L3_FLAGMUX_REGERR0 + (inttype << 3));
75 76
76 /* Get the corresponding error and analyse */ 77 /* Get the corresponding error and analyse */
77 if (err_reg) { 78 if (err_reg) {
78 /* Identify the source from control status register */ 79 /* Identify the source from control status register */
79 for (j = 0; !(err_reg & (1 << j)); j++) 80 err_src = __ffs(err_reg);
80 ;
81 81
82 err_src = j;
83 /* Read the stderrlog_main_source from clk domain */ 82 /* Read the stderrlog_main_source from clk domain */
84 std_err_main_addr = base + *(l3_targ[i] + err_src); 83 l3_targ_base = base + *(l3_targ[i] + err_src);
85 std_err_main = readl(std_err_main_addr); 84 std_err_main = __raw_readl(l3_targ_base +
85 L3_TARG_STDERRLOG_MAIN);
86 masterid = __raw_readl(l3_targ_base +
87 L3_TARG_STDERRLOG_MSTADDR);
86 88
87 switch (std_err_main & CUSTOM_ERROR) { 89 switch (std_err_main & CUSTOM_ERROR) {
88 case STANDARD_ERROR: 90 case STANDARD_ERROR:
89 source_name = 91 target_name =
90 l3_targ_stderrlog_main_name[i][err_src]; 92 l3_targ_inst_name[i][err_src];
91 93 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
92 slave_addr = std_err_main_addr + 94 target_name,
93 L3_SLAVE_ADDRESS_OFFSET; 95 __raw_readl(l3_targ_base +
94 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", 96 L3_TARG_STDERRLOG_SLVOFSLSB));
95 source_name, readl(slave_addr));
96 /* clear the std error log*/ 97 /* clear the std error log*/
97 clear = std_err_main | CLEAR_STDERR_LOG; 98 clear = std_err_main | CLEAR_STDERR_LOG;
98 writel(clear, std_err_main_addr); 99 writel(clear, l3_targ_base +
100 L3_TARG_STDERRLOG_MAIN);
99 break; 101 break;
100 102
101 case CUSTOM_ERROR: 103 case CUSTOM_ERROR:
102 source_name = 104 target_name =
103 l3_targ_stderrlog_main_name[i][err_src]; 105 l3_targ_inst_name[i][err_src];
104 106 for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
105 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n", 107 if (masterid == l3_masters[k].id)
106 source_name); 108 master_name =
109 l3_masters[k].name;
110 }
111 WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
112 master_name, target_name);
107 /* clear the std error log*/ 113 /* clear the std error log*/
108 clear = std_err_main | CLEAR_STDERR_LOG; 114 clear = std_err_main | CLEAR_STDERR_LOG;
109 writel(clear, std_err_main_addr); 115 writel(clear, l3_targ_base +
116 L3_TARG_STDERRLOG_MAIN);
110 break; 117 break;
111 118
112 default: 119 default:
@@ -120,12 +127,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
120 return IRQ_HANDLED; 127 return IRQ_HANDLED;
121} 128}
122 129
123static int __init omap4_l3_probe(struct platform_device *pdev) 130static int __devinit omap4_l3_probe(struct platform_device *pdev)
124{ 131{
125 static struct omap4_l3 *l3; 132 static struct omap4_l3 *l3;
126 struct resource *res; 133 struct resource *res;
127 int ret; 134 int ret;
128 int irq;
129 135
130 l3 = kzalloc(sizeof(*l3), GFP_KERNEL); 136 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
131 if (!l3) 137 if (!l3)
@@ -177,27 +183,25 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
177 /* 183 /*
178 * Setup interrupt Handlers 184 * Setup interrupt Handlers
179 */ 185 */
180 irq = platform_get_irq(pdev, 0); 186 l3->debug_irq = platform_get_irq(pdev, 0);
181 ret = request_irq(irq, 187 ret = request_irq(l3->debug_irq,
182 l3_interrupt_handler, 188 l3_interrupt_handler,
183 IRQF_DISABLED, "l3-dbg-irq", l3); 189 IRQF_DISABLED, "l3-dbg-irq", l3);
184 if (ret) { 190 if (ret) {
185 pr_crit("L3: request_irq failed to register for 0x%x\n", 191 pr_crit("L3: request_irq failed to register for 0x%x\n",
186 OMAP44XX_IRQ_L3_DBG); 192 OMAP44XX_IRQ_L3_DBG);
187 goto err3; 193 goto err3;
188 } 194 }
189 l3->debug_irq = irq;
190 195
191 irq = platform_get_irq(pdev, 1); 196 l3->app_irq = platform_get_irq(pdev, 1);
192 ret = request_irq(irq, 197 ret = request_irq(l3->app_irq,
193 l3_interrupt_handler, 198 l3_interrupt_handler,
194 IRQF_DISABLED, "l3-app-irq", l3); 199 IRQF_DISABLED, "l3-app-irq", l3);
195 if (ret) { 200 if (ret) {
196 pr_crit("L3: request_irq failed to register for 0x%x\n", 201 pr_crit("L3: request_irq failed to register for 0x%x\n",
197 OMAP44XX_IRQ_L3_APP); 202 OMAP44XX_IRQ_L3_APP);
198 goto err4; 203 goto err4;
199 } 204 }
200 l3->app_irq = irq;
201 205
202 return 0; 206 return 0;
203 207
@@ -214,9 +218,9 @@ err0:
214 return ret; 218 return ret;
215} 219}
216 220
217static int __exit omap4_l3_remove(struct platform_device *pdev) 221static int __devexit omap4_l3_remove(struct platform_device *pdev)
218{ 222{
219 struct omap4_l3 *l3 = platform_get_drvdata(pdev); 223 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
220 224
221 free_irq(l3->app_irq, l3); 225 free_irq(l3->app_irq, l3);
222 free_irq(l3->debug_irq, l3); 226 free_irq(l3->debug_irq, l3);
@@ -228,16 +232,29 @@ static int __exit omap4_l3_remove(struct platform_device *pdev)
228 return 0; 232 return 0;
229} 233}
230 234
235#if defined(CONFIG_OF)
236static const struct of_device_id l3_noc_match[] = {
237 {.compatible = "ti,omap4-l3-noc", },
238 {},
239}
240MODULE_DEVICE_TABLE(of, l3_noc_match);
241#else
242#define l3_noc_match NULL
243#endif
244
231static struct platform_driver omap4_l3_driver = { 245static struct platform_driver omap4_l3_driver = {
232 .remove = __exit_p(omap4_l3_remove), 246 .probe = omap4_l3_probe,
247 .remove = __devexit_p(omap4_l3_remove),
233 .driver = { 248 .driver = {
234 .name = "omap_l3_noc", 249 .name = "omap_l3_noc",
250 .owner = THIS_MODULE,
251 .of_match_table = l3_noc_match,
235 }, 252 },
236}; 253};
237 254
238static int __init omap4_l3_init(void) 255static int __init omap4_l3_init(void)
239{ 256{
240 return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe); 257 return platform_driver_register(&omap4_l3_driver);
241} 258}
242postcore_initcall_sync(omap4_l3_init); 259postcore_initcall_sync(omap4_l3_init);
243 260
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 359b83348aed..90b50984cd2e 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -1,132 +1,162 @@
1 /* 1/*
2 * OMAP4XXX L3 Interconnect error handling driver header 2 * OMAP4XXX L3 Interconnect error handling driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com> 6 * sricharan <r.sricharan@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA 21 * USA
22 */ 22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25 25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3 26#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31) 27#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2 28#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0 29#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0 30#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0 31#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1 32#define L3_DEBUG_ERROR 0x1
39 33
40u32 l3_flagmux[L3_MODULES] = { 34/* L3 TARG register offsets */
41 0x50C, 35#define L3_TARG_STDERRLOG_MAIN 0x48
42 0x100C, 36#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
43 0X020C 37#define L3_TARG_STDERRLOG_MSTADDR 0x68
38#define L3_FLAGMUX_REGERR0 0xc
39
40#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
41
42static u32 l3_flagmux[L3_MODULES] = {
43 0x500,
44 0x1000,
45 0X0200
44}; 46};
45 47
46/* 48/* L3 Target standard Error register offsets */
47 * L3 Target standard Error register offsets 49static u32 l3_targ_inst_clk1[] = {
48 */ 50 0x100, /* DMM1 */
49u32 l3_targ_stderrlog_main_clk1[] = { 51 0x200, /* DMM2 */
50 0x148, /* DMM1 */ 52 0x300, /* ABE */
51 0x248, /* DMM2 */ 53 0x400, /* L4CFG */
52 0x348, /* ABE */ 54 0x600 /* CLK2 PWR DISC */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55}; 55};
56 56
57u32 l3_targ_stderrlog_main_clk2[] = { 57static u32 l3_targ_inst_clk2[] = {
58 0x548, /* CORTEX M3 */ 58 0x500, /* CORTEX M3 */
59 0x348, /* DSS */ 59 0x300, /* DSS */
60 0x148, /* GPMC */ 60 0x100, /* GPMC */
61 0x448, /* ISS */ 61 0x400, /* ISS */
62 0x748, /* IVAHD */ 62 0x700, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/ 63 0xD00, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/ 64 0x900, /* L4 PER0*/
65 0x248, /* OCMRAM */ 65 0x200, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/ 66 0x100, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */ 67 0x600, /* SGX */
68 0x848, /* SL2 */ 68 0x800, /* SL2 */
69 0x1648, /* C2C */ 69 0x1600, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ 70 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/ 71 0xF00, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/ 72 0xE00, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */ 73 0xC00, /* L4 PER3 */
74 0xA48, /* L4 PER1*/ 74 0xA00, /* L4 PER1*/
75 0xB48 /* L4 PER2*/ 75 0xB00 /* L4 PER2*/
76}; 76};
77 77
78u32 l3_targ_stderrlog_main_clk3[] = { 78static u32 l3_targ_inst_clk3[] = {
79 0x0148 /* EMUSS */ 79 0x0100 /* EMUSS */
80}; 80};
81 81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { 82static struct l3_masters_data {
83 u32 id;
84 char name[10];
85} l3_masters[] = {
86 { 0x0 , "MPU"},
87 { 0x10, "CS_ADP"},
88 { 0x14, "xxx"},
89 { 0x20, "DSP"},
90 { 0x30, "IVAHD"},
91 { 0x40, "ISS"},
92 { 0x44, "DucatiM3"},
93 { 0x48, "FaceDetect"},
94 { 0x50, "SDMA_Rd"},
95 { 0x54, "SDMA_Wr"},
96 { 0x58, "xxx"},
97 { 0x5C, "xxx"},
98 { 0x60, "SGX"},
99 { 0x70, "DSS"},
100 { 0x80, "C2C"},
101 { 0x88, "xxx"},
102 { 0x8C, "xxx"},
103 { 0x90, "HSI"},
104 { 0xA0, "MMC1"},
105 { 0xA4, "MMC2"},
106 { 0xA8, "MMC6"},
107 { 0xB0, "UNIPRO1"},
108 { 0xC0, "USBHOSTHS"},
109 { 0xC4, "USBOTGHS"},
110 { 0xC8, "USBHOSTFS"}
111};
112
113static char *l3_targ_inst_name[L3_MODULES][18] = {
83 { 114 {
84 "DMM1", 115 "DMM1",
85 "DMM2", 116 "DMM2",
86 "ABE", 117 "ABE",
87 "L4CFG", 118 "L4CFG",
88 "CLK2 PWR DISC", 119 "CLK2 PWR DISC",
89 }, 120 },
90 { 121 {
91 "CORTEX M3" , 122 "CORTEX M3" ,
92 "DSS ", 123 "DSS ",
93 "GPMC ", 124 "GPMC ",
94 "ISS ", 125 "ISS ",
95 "IVAHD ", 126 "IVAHD ",
96 "AES1", 127 "AES1",
97 "L4 PER0", 128 "L4 PER0",
98 "OCMRAM ", 129 "OCMRAM ",
99 "GPMC sERROR", 130 "GPMC sERROR",
100 "SGX ", 131 "SGX ",
101 "SL2 ", 132 "SL2 ",
102 "C2C ", 133 "C2C ",
103 "PWR DISC CLK1", 134 "PWR DISC CLK1",
104 "SHA1", 135 "SHA1",
105 "AES2", 136 "AES2",
106 "L4 PER3", 137 "L4 PER3",
107 "L4 PER1", 138 "L4 PER1",
108 "L4 PER2", 139 "L4 PER2",
109 }, 140 },
110 { 141 {
111 "EMUSS", 142 "EMUSS",
112 }, 143 },
113}; 144};
114 145
115u32 *l3_targ[L3_MODULES] = { 146static u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1, 147 l3_targ_inst_clk1,
117 l3_targ_stderrlog_main_clk2, 148 l3_targ_inst_clk2,
118 l3_targ_stderrlog_main_clk3, 149 l3_targ_inst_clk3,
119}; 150};
120 151
121struct omap4_l3 { 152struct omap4_l3 {
122 struct device *dev; 153 struct device *dev;
123 struct clk *ick; 154 struct clk *ick;
124 155
125 /* memory base */ 156 /* memory base */
126 void __iomem *l3_base[4]; 157 void __iomem *l3_base[L3_MODULES];
127 158
128 int debug_irq; 159 int debug_irq;
129 int app_irq; 160 int app_irq;
130}; 161};
131
132#endif 162#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index 873c0e33b512..a05a62f9ee5b 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -1,26 +1,26 @@
1 /* 1/*
2 * OMAP3XXX L3 Interconnect Driver 2 * OMAP3XXX L3 Interconnect Driver
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com> 5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com> 7 * Sricharan <r.sricharan@ti.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA 22 * USA
23 */ 23 */
24 24
25#include <linux/kernel.h> 25#include <linux/kernel.h>
26#include <linux/slab.h> 26#include <linux/slab.h>
@@ -135,7 +135,7 @@ static char *omap3_l3_initiator_string(u8 initid)
135 } 135 }
136} 136}
137 137
138/** 138/*
139 * omap3_l3_block_irq - handles a register block's irq 139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 * 140 * @l3: struct omap3_l3 *
141 * @base: register block base address 141 * @base: register block base address
@@ -150,30 +150,29 @@ static char *omap3_l3_initiator_string(u8 initid)
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, 150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr) 151 u64 error, int error_addr)
152{ 152{
153 u8 code = omap3_l3_decode_error_code(error); 153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error); 154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI; 155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr); 156 u32 address = omap3_l3_decode_addr(error_addr);
157 157
158 WARN(true, "%s seen by %s %s at address %x\n", 158 WARN(true, "%s seen by %s %s at address %x\n",
159 omap3_l3_code_string(code), 159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid), 160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "", 161 multi ? "Multiple Errors" : "", address);
162 address);
163 162
164 return IRQ_HANDLED; 163 return IRQ_HANDLED;
165} 164}
166 165
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) 166static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{ 167{
169 struct omap3_l3 *l3 = _l3; 168 struct omap3_l3 *l3 = _l3;
170 u64 status, clear; 169 u64 status, clear;
171 u64 error; 170 u64 error;
172 u64 error_addr; 171 u64 error_addr;
173 u64 err_source = 0; 172 u64 err_source = 0;
174 void __iomem *base; 173 void __iomem *base;
175 int int_type; 174 int int_type;
176 irqreturn_t ret = IRQ_NONE; 175 irqreturn_t ret = IRQ_NONE;
177 176
178 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; 177 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
179 if (!int_type) { 178 if (!int_type) {
@@ -191,14 +190,12 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
191 } 190 }
192 191
193 /* identify the error source */ 192 /* identify the error source */
194 for (err_source = 0; !(status & (1 << err_source)); err_source++) 193 err_source = __ffs(status);
195 ;
196 194
197 base = l3->rt + *(omap3_l3_bases[int_type] + err_source); 195 base = l3->rt + omap3_l3_bases[int_type][err_source];
198 error = omap3_l3_readll(base, L3_ERROR_LOG); 196 error = omap3_l3_readll(base, L3_ERROR_LOG);
199 if (error) { 197 if (error) {
200 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); 198 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
201
202 ret |= omap3_l3_block_irq(l3, error, error_addr); 199 ret |= omap3_l3_block_irq(l3, error, error_addr);
203 } 200 }
204 201
@@ -215,9 +212,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
215 212
216static int __init omap3_l3_probe(struct platform_device *pdev) 213static int __init omap3_l3_probe(struct platform_device *pdev)
217{ 214{
218 struct omap3_l3 *l3; 215 struct omap3_l3 *l3;
219 struct resource *res; 216 struct resource *res;
220 int ret; 217 int ret;
221 218
222 l3 = kzalloc(sizeof(*l3), GFP_KERNEL); 219 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
223 if (!l3) 220 if (!l3)
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
index ba2ed9a850cc..4f3cebca4179 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -1,26 +1,26 @@
1 /* 1/*
2 * OMAP3XXX L3 Interconnect Driver header 2 * OMAP3XXX L3 Interconnect Driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com> 5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com> 7 * sricharan <r.sricharan@ti.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA 22 * USA
23 */ 23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26 26
@@ -40,7 +40,7 @@
40#define L3_SI_CONTROL 0x020 40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510 41#define L3_SI_FLAG_STATUS_0 0x510
42 42
43const u64 shift = 1; 43static const u64 shift = 1;
44 44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0) 45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1) 46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
@@ -78,32 +78,32 @@ const u64 shift = 1;
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) 78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) 79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80 80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ 81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \ 82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \ 83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \ 84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \ 85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \ 86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \ 87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \ 88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \ 89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \ 90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \ 91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \ 92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \ 93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \ 94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \ 95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \ 96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \ 97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \ 98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \ 99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \ 100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \ 101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \ 102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \ 103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \ 104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \ 105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \ 106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ) 107 | L3_STATUS_0_MAD2DTA_REQ)
108 108
109#define L3_SI_FLAG_STATUS_1 0x530 109#define L3_SI_FLAG_STATUS_1 0x530
@@ -137,19 +137,19 @@ const u64 shift = 1;
137 137
138enum omap3_l3_initiator_id { 138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */ 139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29, 140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */ 141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28, 142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */ 143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27, 144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26, 145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25, 146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24, 147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23, 148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/ 149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22, 150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21, 151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20, 152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */ 153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19, 154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18, 155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
@@ -158,25 +158,25 @@ enum omap3_l3_initiator_id {
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15, 158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14, 159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */ 160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13, 161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */ 162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12, 163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11, 164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10, 165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */ 166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9, 167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */ 168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8, 169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7, 170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */ 171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6, 172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5, 173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4, 174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3, 175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */ 176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2, 177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */ 178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1, 179 OMAP_L3_USBHOST = 1,
180}; 180};
181 181
182enum omap3_l3_code { 182enum omap3_l3_code {
@@ -192,21 +192,21 @@ enum omap3_l3_code {
192}; 192};
193 193
194struct omap3_l3 { 194struct omap3_l3 {
195 struct device *dev; 195 struct device *dev;
196 struct clk *ick; 196 struct clk *ick;
197 197
198 /* memory base*/ 198 /* memory base*/
199 void __iomem *rt; 199 void __iomem *rt;
200 200
201 int debug_irq; 201 int debug_irq;
202 int app_irq; 202 int app_irq;
203 203
204 /* true when and inband functional error occurs */ 204 /* true when and inband functional error occurs */
205 unsigned inband:1; 205 unsigned inband:1;
206}; 206};
207 207
208/* offsets for l3 agents in order with the Flag status register */ 208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = { 209static unsigned int omap3_l3_app_bases[] = {
210 /* MPU IA */ 210 /* MPU IA */
211 0x1400, 211 0x1400,
212 0x1400, 212 0x1400,
@@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
305 0, 305 0,
306}; 306};
307 307
308unsigned int __iomem omap3_l3_debug_bases[] = { 308static unsigned int omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */ 309 /* MPU DATA IA */
310 0x1400, 310 0x1400,
311 /* RESERVED */ 311 /* RESERVED */
@@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
321 /* REST RESERVED */ 321 /* REST RESERVED */
322}; 322};
323 323
324u32 *omap3_l3_bases[] = { 324static u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases, 325 omap3_l3_app_bases,
326 omap3_l3_debug_bases, 326 omap3_l3_debug_bases,
327}; 327};
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 0844e2ecfb4a..2ab7a9e17fe2 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -26,38 +26,7 @@
26 26
27static struct omap_device_pm_latency *pm_lats; 27static struct omap_device_pm_latency *pm_lats;
28 28
29static struct device *mpu_dev; 29static int _init_omap_device(char *name)
30static struct device *iva_dev;
31static struct device *l3_dev;
32static struct device *dsp_dev;
33
34struct device *omap2_get_mpuss_device(void)
35{
36 WARN_ON_ONCE(!mpu_dev);
37 return mpu_dev;
38}
39
40struct device *omap2_get_iva_device(void)
41{
42 WARN_ON_ONCE(!iva_dev);
43 return iva_dev;
44}
45
46struct device *omap2_get_l3_device(void)
47{
48 WARN_ON_ONCE(!l3_dev);
49 return l3_dev;
50}
51
52struct device *omap4_get_dsp_device(void)
53{
54 WARN_ON_ONCE(!dsp_dev);
55 return dsp_dev;
56}
57EXPORT_SYMBOL(omap4_get_dsp_device);
58
59/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
60static int _init_omap_device(char *name, struct device **new_dev)
61{ 30{
62 struct omap_hwmod *oh; 31 struct omap_hwmod *oh;
63 struct platform_device *pdev; 32 struct platform_device *pdev;
@@ -72,8 +41,6 @@ static int _init_omap_device(char *name, struct device **new_dev)
72 __func__, name)) 41 __func__, name))
73 return -ENODEV; 42 return -ENODEV;
74 43
75 *new_dev = &pdev->dev;
76
77 return 0; 44 return 0;
78} 45}
79 46
@@ -82,16 +49,16 @@ static int _init_omap_device(char *name, struct device **new_dev)
82 */ 49 */
83static void omap2_init_processor_devices(void) 50static void omap2_init_processor_devices(void)
84{ 51{
85 _init_omap_device("mpu", &mpu_dev); 52 _init_omap_device("mpu");
86 if (omap3_has_iva()) 53 if (omap3_has_iva())
87 _init_omap_device("iva", &iva_dev); 54 _init_omap_device("iva");
88 55
89 if (cpu_is_omap44xx()) { 56 if (cpu_is_omap44xx()) {
90 _init_omap_device("l3_main_1", &l3_dev); 57 _init_omap_device("l3_main_1");
91 _init_omap_device("dsp", &dsp_dev); 58 _init_omap_device("dsp");
92 _init_omap_device("iva", &iva_dev); 59 _init_omap_device("iva");
93 } else { 60 } else {
94 _init_omap_device("l3_main", &l3_dev); 61 _init_omap_device("l3_main");
95 } 62 }
96} 63}
97 64
@@ -169,18 +136,26 @@ err:
169 * in the opp entry 136 * in the opp entry
170 */ 137 */
171static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, 138static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
172 struct device *dev) 139 const char *oh_name)
173{ 140{
174 struct voltagedomain *voltdm; 141 struct voltagedomain *voltdm;
175 struct clk *clk; 142 struct clk *clk;
176 struct opp *opp; 143 struct opp *opp;
177 unsigned long freq, bootup_volt; 144 unsigned long freq, bootup_volt;
145 struct device *dev;
178 146
179 if (!vdd_name || !clk_name || !dev) { 147 if (!vdd_name || !clk_name || !oh_name) {
180 pr_err("%s: invalid parameters\n", __func__); 148 pr_err("%s: invalid parameters\n", __func__);
181 goto exit; 149 goto exit;
182 } 150 }
183 151
152 dev = omap_device_get_by_hwmod_name(oh_name);
153 if (IS_ERR(dev)) {
154 pr_err("%s: Unable to get dev pointer for hwmod %s\n",
155 __func__, oh_name);
156 goto exit;
157 }
158
184 voltdm = voltdm_lookup(vdd_name); 159 voltdm = voltdm_lookup(vdd_name);
185 if (IS_ERR(voltdm)) { 160 if (IS_ERR(voltdm)) {
186 pr_err("%s: unable to get vdd pointer for vdd_%s\n", 161 pr_err("%s: unable to get vdd pointer for vdd_%s\n",
@@ -224,8 +199,8 @@ static void __init omap3_init_voltages(void)
224 if (!cpu_is_omap34xx()) 199 if (!cpu_is_omap34xx())
225 return; 200 return;
226 201
227 omap2_set_init_voltage("mpu_iva", "dpll1_ck", mpu_dev); 202 omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
228 omap2_set_init_voltage("core", "l3_ick", l3_dev); 203 omap2_set_init_voltage("core", "l3_ick", "l3_main");
229} 204}
230 205
231static void __init omap4_init_voltages(void) 206static void __init omap4_init_voltages(void)
@@ -233,14 +208,15 @@ static void __init omap4_init_voltages(void)
233 if (!cpu_is_omap44xx()) 208 if (!cpu_is_omap44xx())
234 return; 209 return;
235 210
236 omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev); 211 omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
237 omap2_set_init_voltage("core", "l3_div_ck", l3_dev); 212 omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
238 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev); 213 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
239} 214}
240 215
241static int __init omap2_common_pm_init(void) 216static int __init omap2_common_pm_init(void)
242{ 217{
243 omap2_init_processor_devices(); 218 if (!of_have_populated_dt())
219 omap2_init_processor_devices();
244 omap_pm_if_init(); 220 omap_pm_if_init();
245 221
246 return 0; 222 return 0;
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 2e40a5cf0163..8db5f035eb0a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -151,17 +151,10 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
151 151
152void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) 152void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
153{ 153{
154 /* Static mapping, never released */ 154 if (omap2_globals->prm)
155 if (omap2_globals->prm) { 155 prm_base = omap2_globals->prm;
156 prm_base = ioremap(omap2_globals->prm, SZ_8K); 156 if (omap2_globals->cm)
157 WARN_ON(!prm_base); 157 cm_base = omap2_globals->cm;
158 } 158 if (omap2_globals->cm2)
159 if (omap2_globals->cm) { 159 cm2_base = omap2_globals->cm2;
160 cm_base = ioremap(omap2_globals->cm, SZ_8K);
161 WARN_ON(!cm_base);
162 }
163 if (omap2_globals->cm2) {
164 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
165 WARN_ON(!cm2_base);
166 }
167} 160}
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index da6f3a63b5d5..8f2782874771 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -117,15 +117,10 @@ int omap2_sdrc_get_params(unsigned long r,
117 117
118void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) 118void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
119{ 119{
120 /* Static mapping, never released */ 120 if (omap2_globals->sdrc)
121 if (omap2_globals->sdrc) { 121 omap2_sdrc_base = omap2_globals->sdrc;
122 omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K); 122 if (omap2_globals->sms)
123 WARN_ON(!omap2_sdrc_base); 123 omap2_sms_base = omap2_globals->sms;
124 }
125 if (omap2_globals->sms) {
126 omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
127 WARN_ON(!omap2_sms_base);
128 }
129} 124}
130 125
131/** 126/**
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 3d1c1d393f8f..9992dbfdfdb3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -107,28 +107,6 @@ struct omap_uart_state {
107static LIST_HEAD(uart_list); 107static LIST_HEAD(uart_list);
108static u8 num_uarts; 108static u8 num_uarts;
109 109
110static int uart_idle_hwmod(struct omap_device *od)
111{
112 omap_hwmod_idle(od->hwmods[0]);
113
114 return 0;
115}
116
117static int uart_enable_hwmod(struct omap_device *od)
118{
119 omap_hwmod_enable(od->hwmods[0]);
120
121 return 0;
122}
123
124static struct omap_device_pm_latency omap_uart_latency[] = {
125 {
126 .deactivate_func = uart_idle_hwmod,
127 .activate_func = uart_enable_hwmod,
128 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
129 },
130};
131
132static inline unsigned int __serial_read_reg(struct uart_port *up, 110static inline unsigned int __serial_read_reg(struct uart_port *up,
133 int offset) 111 int offset)
134{ 112{
@@ -800,8 +778,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
800 return; 778 return;
801 779
802 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, 780 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
803 omap_uart_latency, 781 NULL, 0, false);
804 ARRAY_SIZE(omap_uart_latency), false);
805 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", 782 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
806 name, oh->name); 783 name, oh->name);
807 784
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index eba9f9a8ab65..9f43fcc05d3e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -31,14 +31,6 @@
31 31
32static bool sr_enable_on_init; 32static bool sr_enable_on_init;
33 33
34static struct omap_device_pm_latency omap_sr_latency[] = {
35 {
36 .deactivate_func = omap_device_idle_hwmods,
37 .activate_func = omap_device_enable_hwmods,
38 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
39 },
40};
41
42/* Read EFUSE values from control registers for OMAP3430 */ 34/* Read EFUSE values from control registers for OMAP3430 */
43static void __init sr_set_nvalues(struct omap_volt_data *volt_data, 35static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
44 struct omap_sr_data *sr_data) 36 struct omap_sr_data *sr_data)
@@ -121,8 +113,7 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
121 sr_data->enable_on_init = sr_enable_on_init; 113 sr_data->enable_on_init = sr_enable_on_init;
122 114
123 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), 115 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
124 omap_sr_latency, 116 NULL, 0, 0);
125 ARRAY_SIZE(omap_sr_latency), 0);
126 if (IS_ERR(pdev)) 117 if (IS_ERR(pdev))
127 pr_warning("%s: Could not build omap_device for %s: %s.\n\n", 118 pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
128 __func__, name, oh->name); 119 __func__, name, oh->name);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1140e98c9773..e49fc7be2229 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -434,7 +434,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
434 int ret = 0; 434 int ret = 0;
435 char *name = "omap_timer"; 435 char *name = "omap_timer";
436 struct dmtimer_platform_data *pdata; 436 struct dmtimer_platform_data *pdata;
437 struct omap_device *od; 437 struct platform_device *pdev;
438 struct omap_timer_capability_dev_attr *timer_dev_attr; 438 struct omap_timer_capability_dev_attr *timer_dev_attr;
439 struct powerdomain *pwrdm; 439 struct powerdomain *pwrdm;
440 440
@@ -476,12 +476,12 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
476#ifdef CONFIG_PM 476#ifdef CONFIG_PM
477 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 477 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
478#endif 478#endif
479 od = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 479 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
480 omap2_dmtimer_latency, 480 omap2_dmtimer_latency,
481 ARRAY_SIZE(omap2_dmtimer_latency), 481 ARRAY_SIZE(omap2_dmtimer_latency),
482 0); 482 0);
483 483
484 if (IS_ERR(od)) { 484 if (IS_ERR(pdev)) {
485 pr_err("%s: Can't build omap_device for %s: %s.\n", 485 pr_err("%s: Can't build omap_device for %s: %s.\n",
486 __func__, name, oh->name); 486 __func__, name, oh->name);
487 ret = -EINVAL; 487 ret = -EINVAL;
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 19e4dac62a8c..47fb5d607630 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -60,14 +60,6 @@ static struct musb_hdrc_platform_data musb_plat = {
60 60
61static u64 musb_dmamask = DMA_BIT_MASK(32); 61static u64 musb_dmamask = DMA_BIT_MASK(32);
62 62
63static struct omap_device_pm_latency omap_musb_latency[] = {
64 {
65 .deactivate_func = omap_device_idle_hwmods,
66 .activate_func = omap_device_enable_hwmods,
67 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
68 },
69};
70
71static void usb_musb_mux_init(struct omap_musb_board_data *board_data) 63static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
72{ 64{
73 switch (board_data->interface_type) { 65 switch (board_data->interface_type) {
@@ -115,7 +107,6 @@ static struct omap_musb_board_data musb_default_board_data = {
115void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) 107void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
116{ 108{
117 struct omap_hwmod *oh; 109 struct omap_hwmod *oh;
118 struct omap_device *od;
119 struct platform_device *pdev; 110 struct platform_device *pdev;
120 struct device *dev; 111 struct device *dev;
121 int bus_id = -1; 112 int bus_id = -1;
@@ -145,22 +136,19 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
145 name = "musb-omap2430"; 136 name = "musb-omap2430";
146 } 137 }
147 138
148 oh = omap_hwmod_lookup(oh_name); 139 oh = omap_hwmod_lookup(oh_name);
149 if (!oh) { 140 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
150 pr_err("Could not look up %s\n", oh_name); 141 __func__, oh_name))
151 return; 142 return;
152 }
153 143
154 od = omap_device_build(name, bus_id, oh, &musb_plat, 144 pdev = omap_device_build(name, bus_id, oh, &musb_plat,
155 sizeof(musb_plat), omap_musb_latency, 145 sizeof(musb_plat), NULL, 0, false);
156 ARRAY_SIZE(omap_musb_latency), false); 146 if (IS_ERR(pdev)) {
157 if (IS_ERR(od)) {
158 pr_err("Could not build omap_device for %s %s\n", 147 pr_err("Could not build omap_device for %s %s\n",
159 name, oh_name); 148 name, oh_name);
160 return; 149 return;
161 } 150 }
162 151
163 pdev = &od->pdev;
164 dev = &pdev->dev; 152 dev = &pdev->dev;
165 get_device(dev); 153 get_device(dev);
166 dev->dma_mask = &musb_dmamask; 154 dev->dma_mask = &musb_dmamask;
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 09:01:16 -0500