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authorLinus Torvalds <torvalds@g5.osdl.org>2006-04-02 16:34:00 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-04-02 16:34:00 -0400
commit1810b6cb162e0c19e0ecbbacbcfd66f578f335ec (patch)
tree810494ca945483bf669a062d445d49d3bfb7d6a7 /arch/arm/mach-omap2
parentef7a4567dc542d8cc563755478464ea928fede41 (diff)
parent9b6553cd01ce3ea7a6a532f7b7e62e3535d6b102 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (27 commits) [ARM] 3433/1: ARM: OMAP: 8/8 Update board files [ARM] 3455/1: ARM: OMAP: 7/8 Misc updates, take 2 [ARM] 3454/1: ARM: OMAP: 6/8 Update framebuffer low-level init code, take 2 [ARM] 3430/1: ARM: OMAP: 5/8 Update PM [ARM] 3429/1: ARM: OMAP: 4/8 Update GPIO [ARM] 3428/1: ARM: OMAP: 3/8 Update pin multiplexing [ARM] 3427/1: ARM: OMAP: 2/8 Update timers [ARM] 3426/1: ARM: OMAP: 1/8 Update clock framework [ARM] 3396/2: AT91RM9200 Platform devices update [ARM] 3395/2: AT91RM9200 Dataflash Card vs MMC selection [ARM] 3393/2: AT91RM9200 LED support [ARM] 3453/1: Poodle: Correctly set the memory size [ARM] 3446/1: i.MX: MMC/SD SDHC controller registration for i.MX/MX1 MX1ADS board [ARM] 3444/1: i.MX: Scatter-gather DMA emulation for i.MX/MX1 [ARM] 3451/1: ep93xx: use the m48t86 rtc driver on the ts72xx platform [ARM] 3450/1: ep93xx: use the ep93xx rtc driver [ARM] 3452/1: [S3C2410] RX3715 - add nand information [ARM] 3449/1: [S3C2410] Anubis - fix NAND timings [ARM] 3448/1: [S3C2410] Settle delay when _enabling_ USB PLL [ARM] 3442/1: [S3C2410] SMDK: NAND device setup ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig3
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/board-apollon.c285
-rw-r--r--arch/arm/mach-omap2/board-h4.c174
-rw-r--r--arch/arm/mach-omap2/clock.c79
-rw-r--r--arch/arm/mach-omap2/clock.h37
-rw-r--r--arch/arm/mach-omap2/devices.c42
-rw-r--r--arch/arm/mach-omap2/io.c21
-rw-r--r--arch/arm/mach-omap2/memory.c102
-rw-r--r--arch/arm/mach-omap2/memory.h34
-rw-r--r--arch/arm/mach-omap2/mux.c45
-rw-r--r--arch/arm/mach-omap2/pm.c149
-rw-r--r--arch/arm/mach-omap2/prcm-regs.h (renamed from arch/arm/mach-omap2/prcm.h)188
-rw-r--r--arch/arm/mach-omap2/prcm.c40
-rw-r--r--arch/arm/mach-omap2/sleep.S144
-rw-r--r--arch/arm/mach-omap2/sram-fn.S4
16 files changed, 1201 insertions, 152 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 578880943cf2..537dd2e6d380 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -20,3 +20,6 @@ config MACH_OMAP_H4
20 bool "OMAP 2420 H4 board" 20 bool "OMAP 2420 H4 board"
21 depends on ARCH_OMAP2 && ARCH_OMAP24XX 21 depends on ARCH_OMAP2 && ARCH_OMAP24XX
22 22
23config MACH_OMAP_APOLLON
24 bool "OMAP 2420 Apollon board"
25 depends on ARCH_OMAP2 && ARCH_OMAP24XX
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 42041166435c..111eaa64258f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,11 +3,15 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o sram-fn.o clock.o mux.o devices.o serial.o 6obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o
7 7
8obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o 8obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
9 9
10# Power Management
11obj-$(CONFIG_PM) += pm.o sleep.o
12
10# Specific board support 13# Specific board support
11obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 14obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
12obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 15obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
16obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
13 17
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
new file mode 100644
index 000000000000..6c6ba172cdf6
--- /dev/null
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -0,0 +1,285 @@
1/*
2 * linux/arch/arm/mach-omap/omap2/board-apollon.c
3 *
4 * Copyright (C) 2005,2006 Samsung Electronics
5 * Author: Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * Modified from mach-omap/omap2/board-h4.c
8 *
9 * Code for apollon OMAP2 board. Should work on many OMAP2 systems where
10 * the bootloader passes the board-specific data to the kernel.
11 * Do not put any board specific code to this file; create a new machine
12 * type if you need custom low-level initializations.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/partitions.h>
24#include <linux/mtd/onenand.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27
28#include <asm/hardware.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/flash.h>
32
33#include <asm/arch/gpio.h>
34#include <asm/arch/mux.h>
35#include <asm/arch/usb.h>
36#include <asm/arch/board.h>
37#include <asm/arch/common.h>
38#include "prcm-regs.h"
39
40/* LED & Switch macros */
41#define LED0_GPIO13 13
42#define LED1_GPIO14 14
43#define LED2_GPIO15 15
44#define SW_ENTER_GPIO16 16
45#define SW_UP_GPIO17 17
46#define SW_DOWN_GPIO58 58
47
48static struct mtd_partition apollon_partitions[] = {
49 {
50 .name = "X-Loader + U-Boot",
51 .offset = 0,
52 .size = SZ_128K,
53 .mask_flags = MTD_WRITEABLE,
54 },
55 {
56 .name = "params",
57 .offset = MTDPART_OFS_APPEND,
58 .size = SZ_128K,
59 },
60 {
61 .name = "kernel",
62 .offset = MTDPART_OFS_APPEND,
63 .size = SZ_2M,
64 },
65 {
66 .name = "rootfs",
67 .offset = MTDPART_OFS_APPEND,
68 .size = SZ_16M,
69 },
70 {
71 .name = "filesystem00",
72 .offset = MTDPART_OFS_APPEND,
73 .size = SZ_32M,
74 },
75 {
76 .name = "filesystem01",
77 .offset = MTDPART_OFS_APPEND,
78 .size = MTDPART_SIZ_FULL,
79 },
80};
81
82static struct flash_platform_data apollon_flash_data = {
83 .parts = apollon_partitions,
84 .nr_parts = ARRAY_SIZE(apollon_partitions),
85};
86
87static struct resource apollon_flash_resource = {
88 .start = APOLLON_CS0_BASE,
89 .end = APOLLON_CS0_BASE + SZ_128K,
90 .flags = IORESOURCE_MEM,
91};
92
93static struct platform_device apollon_onenand_device = {
94 .name = "onenand",
95 .id = -1,
96 .dev = {
97 .platform_data = &apollon_flash_data,
98 },
99 .num_resources = ARRAY_SIZE(&apollon_flash_resource),
100 .resource = &apollon_flash_resource,
101};
102
103static struct resource apollon_smc91x_resources[] = {
104 [0] = {
105 .start = APOLLON_ETHR_START, /* Physical */
106 .end = APOLLON_ETHR_START + 0xf,
107 .flags = IORESOURCE_MEM,
108 },
109 [1] = {
110 .start = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
111 .end = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device apollon_smc91x_device = {
117 .name = "smc91x",
118 .id = -1,
119 .num_resources = ARRAY_SIZE(apollon_smc91x_resources),
120 .resource = apollon_smc91x_resources,
121};
122
123static struct platform_device apollon_lcd_device = {
124 .name = "apollon_lcd",
125 .id = -1,
126};
127
128static struct platform_device *apollon_devices[] __initdata = {
129 &apollon_onenand_device,
130 &apollon_smc91x_device,
131 &apollon_lcd_device,
132};
133
134static inline void __init apollon_init_smc91x(void)
135{
136 /* Make sure CS1 timings are correct */
137 GPMC_CONFIG1_1 = 0x00011203;
138 GPMC_CONFIG2_1 = 0x001f1f01;
139 GPMC_CONFIG3_1 = 0x00080803;
140 GPMC_CONFIG4_1 = 0x1c091c09;
141 GPMC_CONFIG5_1 = 0x041f1f1f;
142 GPMC_CONFIG6_1 = 0x000004c4;
143 GPMC_CONFIG7_1 = 0x00000f40 | (APOLLON_CS1_BASE >> 24);
144 udelay(100);
145
146 omap_cfg_reg(W4__24XX_GPIO74);
147 if (omap_request_gpio(APOLLON_ETHR_GPIO_IRQ) < 0) {
148 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
149 APOLLON_ETHR_GPIO_IRQ);
150 return;
151 }
152 omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
153}
154
155static void __init omap_apollon_init_irq(void)
156{
157 omap2_init_common_hw();
158 omap_init_irq();
159 omap_gpio_init();
160 apollon_init_smc91x();
161}
162
163static struct omap_uart_config apollon_uart_config __initdata = {
164 .enabled_uarts = (1 << 0) | (0 << 1) | (0 << 2),
165};
166
167static struct omap_mmc_config apollon_mmc_config __initdata = {
168 .mmc [0] = {
169 .enabled = 0,
170 .wire4 = 0,
171 .wp_pin = -1,
172 .power_pin = -1,
173 .switch_pin = -1,
174 },
175};
176
177static struct omap_lcd_config apollon_lcd_config __initdata = {
178 .ctrl_name = "internal",
179};
180
181static struct omap_board_config_kernel apollon_config[] = {
182 { OMAP_TAG_UART, &apollon_uart_config },
183 { OMAP_TAG_MMC, &apollon_mmc_config },
184 { OMAP_TAG_LCD, &apollon_lcd_config },
185};
186
187static void __init apollon_led_init(void)
188{
189 /* LED0 - AA10 */
190 omap_cfg_reg(AA10_242X_GPIO13);
191 omap_request_gpio(LED0_GPIO13);
192 omap_set_gpio_direction(LED0_GPIO13, 0);
193 omap_set_gpio_dataout(LED0_GPIO13, 0);
194 /* LED1 - AA6 */
195 omap_cfg_reg(AA6_242X_GPIO14);
196 omap_request_gpio(LED1_GPIO14);
197 omap_set_gpio_direction(LED1_GPIO14, 0);
198 omap_set_gpio_dataout(LED1_GPIO14, 0);
199 /* LED2 - AA4 */
200 omap_cfg_reg(AA4_242X_GPIO15);
201 omap_request_gpio(LED2_GPIO15);
202 omap_set_gpio_direction(LED2_GPIO15, 0);
203 omap_set_gpio_dataout(LED2_GPIO15, 0);
204}
205
206static irqreturn_t apollon_sw_interrupt(int irq, void *ignored, struct pt_regs *regs)
207{
208 static unsigned int led0, led1, led2;
209
210 if (irq == OMAP_GPIO_IRQ(SW_ENTER_GPIO16))
211 omap_set_gpio_dataout(LED0_GPIO13, led0 ^= 1);
212 else if (irq == OMAP_GPIO_IRQ(SW_UP_GPIO17))
213 omap_set_gpio_dataout(LED1_GPIO14, led1 ^= 1);
214 else if (irq == OMAP_GPIO_IRQ(SW_DOWN_GPIO58))
215 omap_set_gpio_dataout(LED2_GPIO15, led2 ^= 1);
216
217 return IRQ_HANDLED;
218}
219
220static void __init apollon_sw_init(void)
221{
222 /* Enter SW - Y11 */
223 omap_cfg_reg(Y11_242X_GPIO16);
224 omap_request_gpio(SW_ENTER_GPIO16);
225 omap_set_gpio_direction(SW_ENTER_GPIO16, 1);
226 /* Up SW - AA12 */
227 omap_cfg_reg(AA12_242X_GPIO17);
228 omap_request_gpio(SW_UP_GPIO17);
229 omap_set_gpio_direction(SW_UP_GPIO17, 1);
230 /* Down SW - AA8 */
231 omap_cfg_reg(AA8_242X_GPIO58);
232 omap_request_gpio(SW_DOWN_GPIO58);
233 omap_set_gpio_direction(SW_DOWN_GPIO58, 1);
234
235 set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQT_RISING);
236 if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt,
237 SA_SHIRQ, "enter sw",
238 &apollon_sw_interrupt))
239 return;
240 set_irq_type(OMAP_GPIO_IRQ(SW_UP_GPIO17), IRQT_RISING);
241 if (request_irq(OMAP_GPIO_IRQ(SW_UP_GPIO17), &apollon_sw_interrupt,
242 SA_SHIRQ, "up sw",
243 &apollon_sw_interrupt))
244 return;
245 set_irq_type(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), IRQT_RISING);
246 if (request_irq(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), &apollon_sw_interrupt,
247 SA_SHIRQ, "down sw",
248 &apollon_sw_interrupt))
249 return;
250}
251
252static void __init omap_apollon_init(void)
253{
254 apollon_led_init();
255 apollon_sw_init();
256
257 /* REVISIT: where's the correct place */
258 omap_cfg_reg(W19_24XX_SYS_NIRQ);
259
260 /*
261 * Make sure the serial ports are muxed on at this point.
262 * You have to mux them off in device drivers later on
263 * if not needed.
264 */
265 platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
266 omap_board_config = apollon_config;
267 omap_board_config_size = ARRAY_SIZE(apollon_config);
268 omap_serial_init();
269}
270
271static void __init omap_apollon_map_io(void)
272{
273 omap2_map_common_io();
274}
275
276MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
277 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
278 .phys_io = 0x48000000,
279 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
280 .boot_params = 0x80000100,
281 .map_io = omap_apollon_map_io,
282 .init_irq = omap_apollon_init_irq,
283 .init_machine = omap_apollon_init,
284 .timer = &omap_timer,
285MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index a300d634d8a5..4933fce766c8 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -17,6 +17,8 @@
17#include <linux/mtd/mtd.h> 17#include <linux/mtd/mtd.h>
18#include <linux/mtd/partitions.h> 18#include <linux/mtd/partitions.h>
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/workqueue.h>
21#include <linux/input.h>
20 22
21#include <asm/hardware.h> 23#include <asm/hardware.h>
22#include <asm/mach-types.h> 24#include <asm/mach-types.h>
@@ -25,15 +27,57 @@
25#include <asm/mach/flash.h> 27#include <asm/mach/flash.h>
26 28
27#include <asm/arch/gpio.h> 29#include <asm/arch/gpio.h>
30#include <asm/arch/gpioexpander.h>
28#include <asm/arch/mux.h> 31#include <asm/arch/mux.h>
29#include <asm/arch/usb.h> 32#include <asm/arch/usb.h>
33#include <asm/arch/irda.h>
30#include <asm/arch/board.h> 34#include <asm/arch/board.h>
31#include <asm/arch/common.h> 35#include <asm/arch/common.h>
32#include <asm/arch/prcm.h> 36#include <asm/arch/keypad.h>
37#include <asm/arch/menelaus.h>
38#include <asm/arch/dma.h>
39#include "prcm-regs.h"
33 40
34#include <asm/io.h> 41#include <asm/io.h>
35#include <asm/delay.h> 42#include <asm/delay.h>
36 43
44static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
45static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
46
47static int h4_keymap[] = {
48 KEY(0, 0, KEY_LEFT),
49 KEY(0, 1, KEY_RIGHT),
50 KEY(0, 2, KEY_A),
51 KEY(0, 3, KEY_B),
52 KEY(0, 4, KEY_C),
53 KEY(1, 0, KEY_DOWN),
54 KEY(1, 1, KEY_UP),
55 KEY(1, 2, KEY_E),
56 KEY(1, 3, KEY_F),
57 KEY(1, 4, KEY_G),
58 KEY(2, 0, KEY_ENTER),
59 KEY(2, 1, KEY_I),
60 KEY(2, 2, KEY_J),
61 KEY(2, 3, KEY_K),
62 KEY(2, 4, KEY_3),
63 KEY(3, 0, KEY_M),
64 KEY(3, 1, KEY_N),
65 KEY(3, 2, KEY_O),
66 KEY(3, 3, KEY_P),
67 KEY(3, 4, KEY_Q),
68 KEY(4, 0, KEY_R),
69 KEY(4, 1, KEY_4),
70 KEY(4, 2, KEY_T),
71 KEY(4, 3, KEY_U),
72 KEY(4, 4, KEY_ENTER),
73 KEY(5, 0, KEY_V),
74 KEY(5, 1, KEY_W),
75 KEY(5, 2, KEY_L),
76 KEY(5, 3, KEY_S),
77 KEY(5, 4, KEY_ENTER),
78 0
79};
80
37static struct mtd_partition h4_partitions[] = { 81static struct mtd_partition h4_partitions[] = {
38 /* bootloader (U-Boot, etc) in first sector */ 82 /* bootloader (U-Boot, etc) in first sector */
39 { 83 {
@@ -108,9 +152,123 @@ static struct platform_device h4_smc91x_device = {
108 .resource = h4_smc91x_resources, 152 .resource = h4_smc91x_resources,
109}; 153};
110 154
155/* Select between the IrDA and aGPS module
156 */
157static int h4_select_irda(struct device *dev, int state)
158{
159 unsigned char expa;
160 int err = 0;
161
162 if ((err = read_gpio_expa(&expa, 0x21))) {
163 printk(KERN_ERR "Error reading from I/O expander\n");
164 return err;
165 }
166
167 /* 'P6' enable/disable IRDA_TX and IRDA_RX */
168 if (state & IR_SEL) { /* IrDa */
169 if ((err = write_gpio_expa(expa | 0x01, 0x21))) {
170 printk(KERN_ERR "Error writing to I/O expander\n");
171 return err;
172 }
173 } else {
174 if ((err = write_gpio_expa(expa & ~0x01, 0x21))) {
175 printk(KERN_ERR "Error writing to I/O expander\n");
176 return err;
177 }
178 }
179 return err;
180}
181
182static void set_trans_mode(void *data)
183{
184 int *mode = data;
185 unsigned char expa;
186 int err = 0;
187
188 if ((err = read_gpio_expa(&expa, 0x20)) != 0) {
189 printk(KERN_ERR "Error reading from I/O expander\n");
190 }
191
192 expa &= ~0x01;
193
194 if (!(*mode & IR_SIRMODE)) { /* MIR/FIR */
195 expa |= 0x01;
196 }
197
198 if ((err = write_gpio_expa(expa, 0x20)) != 0) {
199 printk(KERN_ERR "Error writing to I/O expander\n");
200 }
201}
202
203static int h4_transceiver_mode(struct device *dev, int mode)
204{
205 struct omap_irda_config *irda_config = dev->platform_data;
206
207 cancel_delayed_work(&irda_config->gpio_expa);
208 PREPARE_WORK(&irda_config->gpio_expa, set_trans_mode, &mode);
209 schedule_work(&irda_config->gpio_expa);
210
211 return 0;
212}
213
214static struct omap_irda_config h4_irda_data = {
215 .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
216 .transceiver_mode = h4_transceiver_mode,
217 .select_irda = h4_select_irda,
218 .rx_channel = OMAP24XX_DMA_UART3_RX,
219 .tx_channel = OMAP24XX_DMA_UART3_TX,
220 .dest_start = OMAP_UART3_BASE,
221 .src_start = OMAP_UART3_BASE,
222 .tx_trigger = OMAP24XX_DMA_UART3_TX,
223 .rx_trigger = OMAP24XX_DMA_UART3_RX,
224};
225
226static struct resource h4_irda_resources[] = {
227 [0] = {
228 .start = INT_24XX_UART3_IRQ,
229 .end = INT_24XX_UART3_IRQ,
230 .flags = IORESOURCE_IRQ,
231 },
232};
233
234static struct platform_device h4_irda_device = {
235 .name = "omapirda",
236 .id = -1,
237 .dev = {
238 .platform_data = &h4_irda_data,
239 },
240 .num_resources = 1,
241 .resource = h4_irda_resources,
242};
243
244static struct omap_kp_platform_data h4_kp_data = {
245 .rows = 6,
246 .cols = 7,
247 .keymap = h4_keymap,
248 .rep = 1,
249 .row_gpios = row_gpios,
250 .col_gpios = col_gpios,
251};
252
253static struct platform_device h4_kp_device = {
254 .name = "omap-keypad",
255 .id = -1,
256 .dev = {
257 .platform_data = &h4_kp_data,
258 },
259};
260
261static struct platform_device h4_lcd_device = {
262 .name = "lcd_h4",
263 .id = -1,
264};
265
111static struct platform_device *h4_devices[] __initdata = { 266static struct platform_device *h4_devices[] __initdata = {
112 &h4_smc91x_device, 267 &h4_smc91x_device,
113 &h4_flash_device, 268 &h4_flash_device,
269 &h4_irda_device,
270 &h4_kp_device,
271 &h4_lcd_device,
114}; 272};
115 273
116static inline void __init h4_init_smc91x(void) 274static inline void __init h4_init_smc91x(void)
@@ -157,7 +315,6 @@ static struct omap_mmc_config h4_mmc_config __initdata = {
157}; 315};
158 316
159static struct omap_lcd_config h4_lcd_config __initdata = { 317static struct omap_lcd_config h4_lcd_config __initdata = {
160 .panel_name = "h4",
161 .ctrl_name = "internal", 318 .ctrl_name = "internal",
162}; 319};
163 320
@@ -174,6 +331,19 @@ static void __init omap_h4_init(void)
174 * You have to mux them off in device drivers later on 331 * You have to mux them off in device drivers later on
175 * if not needed. 332 * if not needed.
176 */ 333 */
334#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
335 omap_cfg_reg(K15_24XX_UART3_TX);
336 omap_cfg_reg(K14_24XX_UART3_RX);
337#endif
338
339#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
340 if (omap_has_menelaus()) {
341 row_gpios[5] = 0;
342 col_gpios[2] = 15;
343 col_gpios[6] = 18;
344 }
345#endif
346
177 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); 347 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
178 omap_board_config = h4_config; 348 omap_board_config = h4_config;
179 omap_board_config_size = ARRAY_SIZE(h4_config); 349 omap_board_config_size = ARRAY_SIZE(h4_config);
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 180f675c9064..72eb4bf571ac 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -28,14 +28,14 @@
28 28
29#include <asm/arch/clock.h> 29#include <asm/arch/clock.h>
30#include <asm/arch/sram.h> 30#include <asm/arch/sram.h>
31#include <asm/arch/prcm.h>
32 31
32#include "prcm-regs.h"
33#include "memory.h"
33#include "clock.h" 34#include "clock.h"
34 35
35//#define DOWN_VARIABLE_DPLL 1 /* Experimental */ 36//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
36 37
37static struct prcm_config *curr_prcm_set; 38static struct prcm_config *curr_prcm_set;
38static struct memory_timings mem_timings;
39static u32 curr_perf_level = PRCM_FULL_SPEED; 39static u32 curr_perf_level = PRCM_FULL_SPEED;
40 40
41/*------------------------------------------------------------------------- 41/*-------------------------------------------------------------------------
@@ -54,11 +54,13 @@ static void omap2_sys_clk_recalc(struct clk * clk)
54 54
55static u32 omap2_get_dpll_rate(struct clk * tclk) 55static u32 omap2_get_dpll_rate(struct clk * tclk)
56{ 56{
57 int dpll_clk, dpll_mult, dpll_div, amult; 57 long long dpll_clk;
58 int dpll_mult, dpll_div, amult;
58 59
59 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ 60 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
60 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */ 61 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
61 dpll_clk = (tclk->parent->rate * dpll_mult) / (dpll_div + 1); 62 dpll_clk = (long long)tclk->parent->rate * dpll_mult;
63 do_div(dpll_clk, dpll_div + 1);
62 amult = CM_CLKSEL2_PLL & 0x3; 64 amult = CM_CLKSEL2_PLL & 0x3;
63 dpll_clk *= amult; 65 dpll_clk *= amult;
64 66
@@ -385,75 +387,23 @@ static u32 omap2_dll_force_needed(void)
385 return 0; 387 return 0;
386} 388}
387 389
388static void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
389{
390 unsigned long dll_cnt;
391 u32 fast_dll = 0;
392
393 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
394
395 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
396 * In the case of 2422, its ok to use CS1 instead of CS0.
397 */
398
399#if 0 /* FIXME: Enable after 24xx cpu detection works */
400 ctype = get_cpu_type();
401 if (cpu_is_omap2422())
402 mem_timings.base_cs = 1;
403 else
404#endif
405 mem_timings.base_cs = 0;
406
407 if (mem_timings.m_type != M_DDR)
408 return;
409
410 /* With DDR we need to determine the low frequency DLL value */
411 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
412 mem_timings.dll_mode = M_UNLOCK;
413 else
414 mem_timings.dll_mode = M_LOCK;
415
416 if (mem_timings.base_cs == 0) {
417 fast_dll = SDRC_DLLA_CTRL;
418 dll_cnt = SDRC_DLLA_STATUS & 0xff00;
419 } else {
420 fast_dll = SDRC_DLLB_CTRL;
421 dll_cnt = SDRC_DLLB_STATUS & 0xff00;
422 }
423 if (force_lock_to_unlock_mode) {
424 fast_dll &= ~0xff00;
425 fast_dll |= dll_cnt; /* Current lock mode */
426 }
427 mem_timings.fast_dll_ctrl = fast_dll;
428
429 /* No disruptions, DDR will be offline & C-ABI not followed */
430 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
431 mem_timings.fast_dll_ctrl,
432 mem_timings.base_cs,
433 force_lock_to_unlock_mode);
434 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
435
436 /* Turn status into unlock ctrl */
437 mem_timings.slow_dll_ctrl |=
438 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
439
440 /* 90 degree phase for anything below 133Mhz */
441 mem_timings.slow_dll_ctrl |= (1 << 1);
442}
443
444static u32 omap2_reprogram_sdrc(u32 level, u32 force) 390static u32 omap2_reprogram_sdrc(u32 level, u32 force)
445{ 391{
392 u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
446 u32 prev = curr_perf_level, flags; 393 u32 prev = curr_perf_level, flags;
447 394
448 if ((curr_perf_level == level) && !force) 395 if ((curr_perf_level == level) && !force)
449 return prev; 396 return prev;
450 397
398 m_type = omap2_memory_get_type();
399 slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
400 fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
401
451 if (level == PRCM_HALF_SPEED) { 402 if (level == PRCM_HALF_SPEED) {
452 local_irq_save(flags); 403 local_irq_save(flags);
453 PRCM_VOLTSETUP = 0xffff; 404 PRCM_VOLTSETUP = 0xffff;
454 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED, 405 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
455 mem_timings.slow_dll_ctrl, 406 slow_dll_ctrl, m_type);
456 mem_timings.m_type);
457 curr_perf_level = PRCM_HALF_SPEED; 407 curr_perf_level = PRCM_HALF_SPEED;
458 local_irq_restore(flags); 408 local_irq_restore(flags);
459 } 409 }
@@ -461,8 +411,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force)
461 local_irq_save(flags); 411 local_irq_save(flags);
462 PRCM_VOLTSETUP = 0xffff; 412 PRCM_VOLTSETUP = 0xffff;
463 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED, 413 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
464 mem_timings.fast_dll_ctrl, 414 fast_dll_ctrl, m_type);
465 mem_timings.m_type);
466 curr_perf_level = PRCM_FULL_SPEED; 415 curr_perf_level = PRCM_FULL_SPEED;
467 local_irq_restore(flags); 416 local_irq_restore(flags);
468 } 417 }
@@ -650,7 +599,7 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
650 case 13: /* dss2 */ 599 case 13: /* dss2 */
651 mask = 0x1; break; 600 mask = 0x1; break;
652 case 25: /* usb */ 601 case 25: /* usb */
653 mask = 0xf; break; 602 mask = 0x7; break;
654 } 603 }
655 } 604 }
656 605
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6cab20b1d3c1..6c78d471fab7 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -33,20 +33,6 @@ static u32 omap2_clksel_get_divisor(struct clk *clk);
33#define RATE_IN_242X (1 << 0) 33#define RATE_IN_242X (1 << 0)
34#define RATE_IN_243X (1 << 1) 34#define RATE_IN_243X (1 << 1)
35 35
36/* Memory timings */
37#define M_DDR 1
38#define M_LOCK_CTRL (1 << 2)
39#define M_UNLOCK 0
40#define M_LOCK 1
41
42struct memory_timings {
43 u32 m_type; /* ddr = 1, sdr = 0 */
44 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
45 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
46 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
47 u32 base_cs; /* base chip select to use for calculations */
48};
49
50/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 36/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
51 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
52 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM 38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
@@ -731,6 +717,16 @@ static struct clk sys_clkout2 = {
731 .recalc = &omap2_clksel_recalc, 717 .recalc = &omap2_clksel_recalc,
732}; 718};
733 719
720static struct clk emul_ck = {
721 .name = "emul_ck",
722 .parent = &func_54m_ck,
723 .flags = CLOCK_IN_OMAP242X,
724 .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
725 .enable_bit = 0,
726 .recalc = &omap2_propagate_rate,
727
728};
729
734/* 730/*
735 * MPU clock domain 731 * MPU clock domain
736 * Clocks: 732 * Clocks:
@@ -1702,7 +1698,8 @@ static struct clk hdq_fck = {
1702}; 1698};
1703 1699
1704static struct clk i2c2_ick = { 1700static struct clk i2c2_ick = {
1705 .name = "i2c2_ick", 1701 .name = "i2c_ick",
1702 .id = 2,
1706 .parent = &l4_ck, 1703 .parent = &l4_ck,
1707 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1704 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1708 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1705 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1711,7 +1708,8 @@ static struct clk i2c2_ick = {
1711}; 1708};
1712 1709
1713static struct clk i2c2_fck = { 1710static struct clk i2c2_fck = {
1714 .name = "i2c2_fck", 1711 .name = "i2c_fck",
1712 .id = 2,
1715 .parent = &func_12m_ck, 1713 .parent = &func_12m_ck,
1716 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1717 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1715 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1729,7 +1727,8 @@ static struct clk i2chs2_fck = {
1729}; 1727};
1730 1728
1731static struct clk i2c1_ick = { 1729static struct clk i2c1_ick = {
1732 .name = "i2c1_ick", 1730 .name = "i2c_ick",
1731 .id = 1,
1733 .parent = &l4_ck, 1732 .parent = &l4_ck,
1734 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1733 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1735 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1734 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1738,7 +1737,8 @@ static struct clk i2c1_ick = {
1738}; 1737};
1739 1738
1740static struct clk i2c1_fck = { 1739static struct clk i2c1_fck = {
1741 .name = "i2c1_fck", 1740 .name = "i2c_fck",
1741 .id = 1,
1742 .parent = &func_12m_ck, 1742 .parent = &func_12m_ck,
1743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1744 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1971,6 +1971,7 @@ static struct clk *onchip_clks[] = {
1971 &wdt1_osc_ck, 1971 &wdt1_osc_ck,
1972 &sys_clkout, 1972 &sys_clkout,
1973 &sys_clkout2, 1973 &sys_clkout2,
1974 &emul_ck,
1974 /* mpu domain clocks */ 1975 /* mpu domain clocks */
1975 &mpu_ck, 1976 &mpu_ck,
1976 /* dsp domain clocks */ 1977 /* dsp domain clocks */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7181edb89352..def9e5370edf 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -74,6 +74,47 @@ static void omap_init_i2c(void) {}
74 74
75#endif 75#endif
76 76
77#if defined(CONFIG_OMAP_STI)
78
79#define OMAP2_STI_BASE IO_ADDRESS(0x48068000)
80#define OMAP2_STI_CHANNEL_BASE 0x54000000
81#define OMAP2_STI_IRQ 4
82
83static struct resource sti_resources[] = {
84 {
85 .start = OMAP2_STI_BASE,
86 .end = OMAP2_STI_BASE + 0x7ff,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .start = OMAP2_STI_CHANNEL_BASE,
91 .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
92 .flags = IORESOURCE_MEM,
93 },
94 {
95 .start = OMAP2_STI_IRQ,
96 .flags = IORESOURCE_IRQ,
97 }
98};
99
100static struct platform_device sti_device = {
101 .name = "sti",
102 .id = -1,
103 .dev = {
104 .release = omap_nop_release,
105 },
106 .num_resources = ARRAY_SIZE(sti_resources),
107 .resource = sti_resources,
108};
109
110static inline void omap_init_sti(void)
111{
112 platform_device_register(&sti_device);
113}
114#else
115static inline void omap_init_sti(void) {}
116#endif
117
77/*-------------------------------------------------------------------------*/ 118/*-------------------------------------------------------------------------*/
78 119
79static int __init omap2_init_devices(void) 120static int __init omap2_init_devices(void)
@@ -82,6 +123,7 @@ static int __init omap2_init_devices(void)
82 * in alphabetical order so they're easier to sort through. 123 * in alphabetical order so they're easier to sort through.
83 */ 124 */
84 omap_init_i2c(); 125 omap_init_i2c();
126 omap_init_sti();
85 127
86 return 0; 128 return 0;
87} 129}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8ea67bf196a5..7d5711611f2f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -16,9 +16,13 @@
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h> 17#include <linux/init.h>
18 18
19#include <asm/mach/map.h> 19#include <asm/tlb.h>
20#include <asm/io.h> 20#include <asm/io.h>
21
22#include <asm/mach/map.h>
23
21#include <asm/arch/mux.h> 24#include <asm/arch/mux.h>
25#include <asm/arch/omapfb.h>
22 26
23extern void omap_sram_init(void); 27extern void omap_sram_init(void);
24extern int omap2_clk_init(void); 28extern int omap2_clk_init(void);
@@ -43,11 +47,24 @@ static struct map_desc omap2_io_desc[] __initdata = {
43 } 47 }
44}; 48};
45 49
46void __init omap_map_common_io(void) 50void __init omap2_map_common_io(void)
47{ 51{
48 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc)); 52 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc));
53
54 /* Normally devicemaps_init() would flush caches and tlb after
55 * mdesc->map_io(), but we must also do it here because of the CPU
56 * revision check below.
57 */
58 local_flush_tlb_all();
59 flush_cache_all();
60
49 omap2_check_revision(); 61 omap2_check_revision();
50 omap_sram_init(); 62 omap_sram_init();
63 omapfb_reserve_mem();
64}
65
66void __init omap2_init_common_hw(void)
67{
51 omap2_mux_init(); 68 omap2_mux_init();
52 omap2_clk_init(); 69 omap2_clk_init();
53} 70}
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
new file mode 100644
index 000000000000..1d925d69fc35
--- /dev/null
+++ b/arch/arm/mach-omap2/memory.c
@@ -0,0 +1,102 @@
1/*
2 * linux/arch/arm/mach-omap2/memory.c
3 *
4 * Memory timing related functions for OMAP24XX
5 *
6 * Copyright (C) 2005 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/list.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25
26#include <asm/io.h>
27
28#include <asm/arch/clock.h>
29#include <asm/arch/sram.h>
30
31#include "prcm-regs.h"
32#include "memory.h"
33
34static struct memory_timings mem_timings;
35
36u32 omap2_memory_get_slow_dll_ctrl(void)
37{
38 return mem_timings.slow_dll_ctrl;
39}
40
41u32 omap2_memory_get_fast_dll_ctrl(void)
42{
43 return mem_timings.fast_dll_ctrl;
44}
45
46u32 omap2_memory_get_type(void)
47{
48 return mem_timings.m_type;
49}
50
51void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
52{
53 unsigned long dll_cnt;
54 u32 fast_dll = 0;
55
56 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
57
58 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
59 * In the case of 2422, its ok to use CS1 instead of CS0.
60 */
61 if (cpu_is_omap2422())
62 mem_timings.base_cs = 1;
63 else
64 mem_timings.base_cs = 0;
65
66 if (mem_timings.m_type != M_DDR)
67 return;
68
69 /* With DDR we need to determine the low frequency DLL value */
70 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
71 mem_timings.dll_mode = M_UNLOCK;
72 else
73 mem_timings.dll_mode = M_LOCK;
74
75 if (mem_timings.base_cs == 0) {
76 fast_dll = SDRC_DLLA_CTRL;
77 dll_cnt = SDRC_DLLA_STATUS & 0xff00;
78 } else {
79 fast_dll = SDRC_DLLB_CTRL;
80 dll_cnt = SDRC_DLLB_STATUS & 0xff00;
81 }
82 if (force_lock_to_unlock_mode) {
83 fast_dll &= ~0xff00;
84 fast_dll |= dll_cnt; /* Current lock mode */
85 }
86 /* set fast timings with DLL filter disabled */
87 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
88
89 /* No disruptions, DDR will be offline & C-ABI not followed */
90 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
91 mem_timings.fast_dll_ctrl,
92 mem_timings.base_cs,
93 force_lock_to_unlock_mode);
94 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
95
96 /* Turn status into unlock ctrl */
97 mem_timings.slow_dll_ctrl |=
98 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
99
100 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
101 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
102}
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
new file mode 100644
index 000000000000..d212eea83a05
--- /dev/null
+++ b/arch/arm/mach-omap2/memory.h
@@ -0,0 +1,34 @@
1/*
2 * linux/arch/arm/mach-omap2/memory.h
3 *
4 * Interface for memory timing related functions for OMAP24XX
5 *
6 * Copyright (C) 2005 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17/* Memory timings */
18#define M_DDR 1
19#define M_LOCK_CTRL (1 << 2)
20#define M_UNLOCK 0
21#define M_LOCK 1
22
23struct memory_timings {
24 u32 m_type; /* ddr = 1, sdr = 0 */
25 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
26 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
27 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
28 u32 base_cs; /* base chip select to use for calculations */
29};
30
31extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
32extern u32 omap2_memory_get_slow_dll_ctrl(void);
33extern u32 omap2_memory_get_fast_dll_ctrl(void);
34extern u32 omap2_memory_get_type(void);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ea4654815dd1..1197dc38c20a 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -50,9 +50,54 @@ MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1)
50/* Menelaus interrupt */ 50/* Menelaus interrupt */
51MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1) 51MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
52 52
53/* 24xx clocks */
54MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
55
56/* 24xx McBSP */
57MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
58MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
59MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
60MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
61
53/* 24xx GPIO */ 62/* 24xx GPIO */
63MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
64MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
65MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
66MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
67MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
68MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
69MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
54MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) 70MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
71MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
55MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) 72MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
73MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
74
75/* TSC IRQ */
76MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
77
78/* UART3 */
79MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
80MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
81
82/* Keypad GPIO*/
83MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)
84MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1)
85MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1)
86MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1)
87MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1)
88MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1)
89MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1)
90MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1)
91MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1)
92MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1)
93MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1)
94MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1)
95MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1)
96
97/* 24xx Menelaus Keypad GPIO */
98MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1)
99MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1)
100MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
56 101
57}; 102};
58 103
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
new file mode 100644
index 000000000000..562168fa2b16
--- /dev/null
+++ b/arch/arm/mach-omap2/pm.c
@@ -0,0 +1,149 @@
1/*
2 * linux/arch/arm/mach-omap2/pm.c
3 *
4 * OMAP2 Power Management Routines
5 *
6 * Copyright (C) 2006 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2005 Texas Instruments, Inc.
10 * Richard Woodruff <r-woodruff2@ti.com>
11 *
12 * Based on pm.c for omap1
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/pm.h>
20#include <linux/sched.h>
21#include <linux/proc_fs.h>
22#include <linux/pm.h>
23#include <linux/interrupt.h>
24#include <linux/sysfs.h>
25#include <linux/module.h>
26
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/atomic.h>
30#include <asm/mach/time.h>
31#include <asm/mach/irq.h>
32#include <asm/mach-types.h>
33
34#include <asm/arch/irqs.h>
35#include <asm/arch/clock.h>
36#include <asm/arch/sram.h>
37#include <asm/arch/pm.h>
38
39static struct clk *vclk;
40static void (*omap2_sram_idle)(void);
41static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
42static void (*saved_idle)(void);
43
44void omap2_pm_idle(void)
45{
46 local_irq_disable();
47 local_fiq_disable();
48 if (need_resched()) {
49 local_fiq_enable();
50 local_irq_enable();
51 return;
52 }
53
54 /*
55 * Since an interrupt may set up a timer, we don't want to
56 * reprogram the hardware timer with interrupts enabled.
57 * Re-enable interrupts only after returning from idle.
58 */
59 timer_dyn_reprogram();
60
61 omap2_sram_idle();
62 local_fiq_enable();
63 local_irq_enable();
64}
65
66static int omap2_pm_prepare(suspend_state_t state)
67{
68 int error = 0;
69
70 /* We cannot sleep in idle until we have resumed */
71 saved_idle = pm_idle;
72 pm_idle = NULL;
73
74 switch (state)
75 {
76 case PM_SUSPEND_STANDBY:
77 case PM_SUSPEND_MEM:
78 break;
79
80 case PM_SUSPEND_DISK:
81 return -ENOTSUPP;
82
83 default:
84 return -EINVAL;
85 }
86
87 return error;
88}
89
90static int omap2_pm_enter(suspend_state_t state)
91{
92 switch (state)
93 {
94 case PM_SUSPEND_STANDBY:
95 case PM_SUSPEND_MEM:
96 /* FIXME: Add suspend */
97 break;
98
99 case PM_SUSPEND_DISK:
100 return -ENOTSUPP;
101
102 default:
103 return -EINVAL;
104 }
105
106 return 0;
107}
108
109static int omap2_pm_finish(suspend_state_t state)
110{
111 pm_idle = saved_idle;
112 return 0;
113}
114
115static struct pm_ops omap_pm_ops = {
116 .pm_disk_mode = 0,
117 .prepare = omap2_pm_prepare,
118 .enter = omap2_pm_enter,
119 .finish = omap2_pm_finish,
120};
121
122int __init omap2_pm_init(void)
123{
124 printk("Power Management for TI OMAP.\n");
125
126 vclk = clk_get(NULL, "virt_prcm_set");
127 if (IS_ERR(vclk)) {
128 printk(KERN_ERR "Could not get PM vclk\n");
129 return -ENODEV;
130 }
131
132 /*
133 * We copy the assembler sleep/wakeup routines to SRAM.
134 * These routines need to be in SRAM as that's the only
135 * memory the MPU can see when it wakes up.
136 */
137 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
138 omap24xx_idle_loop_suspend_sz);
139
140 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
141 omap24xx_cpu_suspend_sz);
142
143 pm_set_ops(&omap_pm_ops);
144 pm_idle = omap2_pm_idle;
145
146 return 0;
147}
148
149__initcall(omap2_pm_init);
diff --git a/arch/arm/mach-omap2/prcm.h b/arch/arm/mach-omap2/prcm-regs.h
index 2eb89b936c83..22ac7be4f782 100644
--- a/arch/arm/mach-omap2/prcm.h
+++ b/arch/arm/mach-omap2/prcm-regs.h
@@ -1,5 +1,7 @@
1/* 1/*
2 * prcm.h - Access definations for use in OMAP24XX clock and power management 2 * linux/arch/arm/mach-omap2/prcm-reg.h
3 *
4 * OMAP24XX Power Reset and Clock Management (PRCM) registers
3 * 5 *
4 * Copyright (C) 2005 Texas Instruments, Inc. 6 * Copyright (C) 2005 Texas Instruments, Inc.
5 * 7 *
@@ -18,8 +20,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 21 */
20 22
21#ifndef __ASM_ARM_ARCH_DPM_PRCM_H 23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
22#define __ASM_ARM_ARCH_DPM_PRCM_H 24#define __ARCH_ARM_MACH_OMAP2_PRCM_H
23 25
24/* SET_PERFORMANCE_LEVEL PARAMETERS */ 26/* SET_PERFORMANCE_LEVEL PARAMETERS */
25#define PRCM_HALF_SPEED 1 27#define PRCM_HALF_SPEED 1
@@ -159,54 +161,63 @@
159#define CM_FCLKEN_MDM PRCM_REG32(0xC00) 161#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
160#define CM_ICLKEN_MDM PRCM_REG32(0xC10) 162#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
161#define CM_IDLEST_MDM PRCM_REG32(0xC20) 163#define CM_IDLEST_MDM PRCM_REG32(0xC20)
164#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
162#define CM_CLKSEL_MDM PRCM_REG32(0xC40) 165#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
163 166#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
164/* FIXME: Move to header for 2430 */ 167#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
165#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000) 168#define RM_RSTST_MDM PRCM_REG32(0xC58)
169#define PM_WKEN_MDM PRCM_REG32(0xCA0)
170#define PM_WKST_MDM PRCM_REG32(0xCB0)
171#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
172#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
173#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
174
175#define OMAP24XX_L4_IO_BASE 0x48000000
176
177#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
166#define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) 178#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
167 179
168#define GPMC_BASE (OMAP24XX_GPMC_BASE) 180#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
169#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset)) 181#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))
170 182
171#define GPT1_BASE (OMAP24XX_GPT1) 183/* FIXME: Move these to timer code */
184#define GPT1_BASE (0x48028000)
172#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) 185#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
173 186
174/* Misc sysconfig */ 187/* Misc sysconfig */
175#define DISPC_SYSCONFIG DISP_REG32(0x410) 188#define DISPC_SYSCONFIG DISP_REG32(0x410)
176#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000) 189#define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000)
177#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) 190#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
178#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10) 191#define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10)
179 192#define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
180//#define DSP_MMU_SYSCONFIG 0x5A000010 193
181#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10) 194#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10)
182//#define IVA_MMU_SYSCONFIG 0x5D000010 195#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C)
183//#define DSP_DMA_SYSCONFIG 0x00FCC02C 196#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C)
184#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
185#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
186#define GPMC_SYSCONFIG GPMC_REG32(0x010) 197#define GPMC_SYSCONFIG GPMC_REG32(0x010)
187#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010) 198#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
188#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054) 199#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
189#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054) 200#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
190#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054) 201#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
191//#define IVA_SYSCONFIG 0x5C060010 202#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10)
192#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10) 203#define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000)
193#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10) 204#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10)
194#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010) 205#define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010)
195//#define VLYNQ_SYSCONFIG 0x67FFFE10
196 206
197/* rkw - good cannidates for PM_ to start what nm was trying */ 207/* rkw - good cannidates for PM_ to start what nm was trying */
198#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) 208#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000)
199#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) 209#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000)
200#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) 210#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000)
201#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) 211#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000)
202#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) 212#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000)
203#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) 213#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000)
204#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) 214#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000)
205#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) 215#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000)
206#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) 216#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000)
207#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) 217#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000)
208#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) 218#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000)
209 219
220/* FIXME: Move these to timer code */
210#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) 221#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
211#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) 222#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
212#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) 223#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
@@ -220,12 +231,18 @@
220#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) 231#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
221#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) 232#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
222 233
223#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1))) 234/* FIXME: Move these to gpio code */
235#define OMAP24XX_GPIO_BASE 0x48018000
236#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
237
238#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10))
239#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10))
240#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10))
241#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10))
224 242
225#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10)) 243#if defined(CONFIG_ARCH_OMAP243X)
226#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10)) 244#define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10))
227#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10)) 245#endif
228#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
229 246
230/* GP TIMER 1 */ 247/* GP TIMER 1 */
231#define GPTIMER1_TISTAT GPT1_REG32(0x014) 248#define GPTIMER1_TISTAT GPT1_REG32(0x014)
@@ -243,15 +260,15 @@
243#define GPTIMER1_TCAR2 GPT1_REG32(0x044) 260#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
244 261
245/* rkw -- base fix up please... */ 262/* rkw -- base fix up please... */
246#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018) 263#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
247 264
248/* SDRC */ 265/* SDRC */
249#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060) 266#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
250#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064) 267#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
251#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068) 268#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
252#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C) 269#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
253#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070) 270#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
254#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084) 271#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
255 272
256/* GPIO 1 */ 273/* GPIO 1 */
257#define GPIO1_BASE GPIOX_BASE(1) 274#define GPIO1_BASE GPIOX_BASE(1)
@@ -278,6 +295,8 @@
278#define GPIO2_DATAIN GPIO2_REG32(0x038) 295#define GPIO2_DATAIN GPIO2_REG32(0x038)
279#define GPIO2_OE GPIO2_REG32(0x034) 296#define GPIO2_OE GPIO2_REG32(0x034)
280#define GPIO2_DATAOUT GPIO2_REG32(0x03C) 297#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
298#define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050)
299#define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054)
281 300
282/* GPIO 3 */ 301/* GPIO 3 */
283#define GPIO3_BASE GPIOX_BASE(3) 302#define GPIO3_BASE GPIOX_BASE(3)
@@ -294,6 +313,8 @@
294#define GPIO3_DATAOUT GPIO3_REG32(0x03C) 313#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
295#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) 314#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
296#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) 315#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
316#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
317#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
297 318
298/* GPIO 4 */ 319/* GPIO 4 */
299#define GPIO4_BASE GPIOX_BASE(4) 320#define GPIO4_BASE GPIOX_BASE(4)
@@ -311,10 +332,26 @@
311#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) 332#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
312#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) 333#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
313 334
335#if defined(CONFIG_ARCH_OMAP243X)
336/* GPIO 5 */
337#define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset)))
338#define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C)
339#define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018)
340#define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C)
341#define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028)
342#define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020)
343#define GPIO5_RISINGDETECT GPIO5_REG32(0x048)
344#define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C)
345#define GPIO5_DATAIN GPIO5_REG32(0x038)
346#define GPIO5_OE GPIO5_REG32(0x034)
347#define GPIO5_DATAOUT GPIO5_REG32(0x03C)
348#define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050)
349#define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054)
350#endif
314 351
315/* IO CONFIG */ 352/* IO CONFIG */
316#define CONTROL_BASE (OMAP24XX_CTRL_BASE) 353#define OMAP24XX_CTRL_BASE (L4_24XX_BASE)
317#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset)) 354#define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset))
318 355
319#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) 356#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
320#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) 357#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
@@ -322,15 +359,18 @@
322#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) 359#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
323#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) 360#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
324#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) 361#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
325#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) 362#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */
326#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) 363#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
327#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) 364#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
365#define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */
366#define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */
328 367
329/* CONTROL */ 368/* CONTROL */
330#define CONTROL_DEVCONF CONTROL_REG32(0x274) 369#define CONTROL_DEVCONF CONTROL_REG32(0x274)
370#define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8)
331 371
332/* INTERRUPT CONTROLLER */ 372/* INTERRUPT CONTROLLER */
333#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000) 373#define INTC_BASE ((L4_24XX_BASE) + 0xfe000)
334#define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) 374#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
335 375
336#define INTC1_U_BASE INTC_REG32(0x000) 376#define INTC1_U_BASE INTC_REG32(0x000)
@@ -348,10 +388,12 @@
348#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) 388#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
349#define INTC_SIR_IRQ INTC_REG32(0x040) 389#define INTC_SIR_IRQ INTC_REG32(0x040)
350#define INTC_CONTROL INTC_REG32(0x048) 390#define INTC_CONTROL INTC_REG32(0x048)
351#define INTC_ILR11 INTC_REG32(0x12C) 391#define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */
392#define INTC_ILR30 INTC_REG32(0x178)
393#define INTC_ILR31 INTC_REG32(0x17C)
352#define INTC_ILR32 INTC_REG32(0x180) 394#define INTC_ILR32 INTC_REG32(0x180)
353#define INTC_ILR37 INTC_REG32(0x194) 395#define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */
354#define INTC_SYSCONFIG INTC_REG32(0x010) 396#define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */
355 397
356/* RAM FIREWALL */ 398/* RAM FIREWALL */
357#define RAMFW_BASE (0x68005000) 399#define RAMFW_BASE (0x68005000)
@@ -373,6 +415,24 @@
373#define GPMC_CONFIG6_0 GPMC_REG32(0x074) 415#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
374#define GPMC_CONFIG7_0 GPMC_REG32(0x078) 416#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
375 417
418/* GPMC CS1 */
419#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
420#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
421#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
422#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
423#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
424#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
425#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
426
427/* GPMC CS3 */
428#define GPMC_CONFIG1_3 GPMC_REG32(0x0F0)
429#define GPMC_CONFIG2_3 GPMC_REG32(0x0F4)
430#define GPMC_CONFIG3_3 GPMC_REG32(0x0F8)
431#define GPMC_CONFIG4_3 GPMC_REG32(0x0FC)
432#define GPMC_CONFIG5_3 GPMC_REG32(0x100)
433#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
434#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
435
376/* DSS */ 436/* DSS */
377#define DSS_CONTROL DISP_REG32(0x040) 437#define DSS_CONTROL DISP_REG32(0x040)
378#define DISPC_CONTROL DISP_REG32(0x440) 438#define DISPC_CONTROL DISP_REG32(0x440)
@@ -405,11 +465,15 @@
405#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) 465#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
406#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) 466#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
407 467
408/* Wake up define for board */ 468/* HSUSB Suspend */
409#define GPIO97 (1 << 1) 469#define HSUSB_CTRL __REG8(0x480AC001)
410#define GPIO88 (1 << 24) 470#define USBOTG_POWER __REG32(0x480AC000)
471
472/* HS MMC */
473#define MMCHS1_SYSCONFIG __REG32(0x4809C010)
474#define MMCHS2_SYSCONFIG __REG32(0x480b4010)
411 475
412#endif /* __ASSEMBLER__ */ 476#endif /* __ASSEMBLER__ */
413 477
414#endif 478#endif
415 479
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
new file mode 100644
index 000000000000..8893479dc7e0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm.c
@@ -0,0 +1,40 @@
1/*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/config.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20
21#include "prcm-regs.h"
22
23u32 omap_prcm_get_reset_sources(void)
24{
25 return RM_RSTST_WKUP & 0x7f;
26}
27EXPORT_SYMBOL(omap_prcm_get_reset_sources);
28
29/* Resets clock rates and reboots the system. Only called from system.h */
30void omap_prcm_arch_reset(char mode)
31{
32 u32 rate;
33 struct clk *vclk, *sclk;
34
35 vclk = clk_get(NULL, "virt_prcm_set");
36 sclk = clk_get(NULL, "sys_ck");
37 rate = clk_get_rate(sclk);
38 clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
39 RM_RSTCTRL_WKUP |= 2;
40}
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S
new file mode 100644
index 000000000000..00299cbeb911
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep.S
@@ -0,0 +1,144 @@
1/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2004
5 * Texas Instruments, <www.ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <linux/config.h>
25#include <linux/linkage.h>
26#include <asm/assembler.h>
27#include <asm/arch/io.h>
28#include <asm/arch/pm.h>
29
30#define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10)
31#define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
32#define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
33#define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
34#define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
35#define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
36#define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
37
38#define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60)
39#define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
40#define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
41#define A_SDRC0_V (0xC0000000)
42#define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
43
44 .text
45
46/*
47 * Forces OMAP into idle state
48 *
49 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
50 * for normal idles.
51 *
52 * Note: This code get's copied to internal SRAM at boot. When the OMAP
53 * wakes up it continues execution at the point it went to sleep.
54 */
55ENTRY(omap24xx_idle_loop_suspend)
56 stmfd sp!, {r0, lr} @ save registers on stack
57 mov r0, #0 @ clear for mcr setup
58 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
59 ldmfd sp!, {r0, pc} @ restore regs and return
60
61ENTRY(omap24xx_idle_loop_suspend_sz)
62 .word . - omap24xx_idle_loop_suspend
63
64/*
65 * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
66 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
67 * SDRC.
68 *
69 * Input:
70 * R0 : DLL ctrl value pre-Sleep
71 * R1 : Processor+Revision
72 * 2420: 0x21 = 242xES1, 0x26 = 242xES2.2
73 * 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
74 *
75 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
76 * when we get called, but the DLL probably isn't. We will wait a bit more in
77 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
78 * if in unlocked mode.
79 *
80 * For less than 242x-ES2.2 upon wake from a sleep mode where the external
81 * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
82 * clock can pass into the PRCM can cause problems at DSP and IVA.
83 * To work around this the code will switch to the 32kHz source prior to sleep.
84 * Post sleep we will shift back to using the DPLL. Apparently,
85 * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
86 * 3x12MHz + 3x32kHz clocks for a full switch.
87 *
88 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
89 * at wake
90 */
91ENTRY(omap24xx_cpu_suspend)
92 stmfd sp!, {r0 - r12, lr} @ save registers on stack
93 mov r3, #0x0 @ clear for mrc call
94 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
95 nop
96 nop
97 ldr r3, A_SDRC_POWER @ addr of sdrc power
98 ldr r4, [r3] @ value of sdrc power
99 orr r4, r4, #0x40 @ enable self refresh on idle req
100 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
101 str r4, [r3] @ make it so
102 mov r2, #0
103 nop
104 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
105 nop
106loop:
107 subs r5, r5, #0x1 @ awake, wait just a bit
108 bne loop
109
110 /* The DPLL has on before we take the DDR out of self refresh */
111 bic r4, r4, #0x40 @ now clear self refresh bit.
112 str r4, [r3] @ put vlaue back.
113 ldr r4, A_SDRC0 @ make a clock happen
114 ldr r4, [r4]
115 nop @ start auto refresh only after clk ok
116 movs r0, r0 @ see if DDR or SDR
117 ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
118 strne r0, [r1] @ rewrite DLLA to force DLL reload
119 addne r1, r1, #0x8 @ move to DLLB
120 strne r0, [r1] @ rewrite DLLB to force DLL reload
121
122 mov r5, #0x1000
123loop2:
124 subs r5, r5, #0x1
125 bne loop2
126 /* resume*/
127 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
128
129A_SDRC_POWER:
130 .word A_SDRC_POWER_V
131A_SDRC0:
132 .word A_SDRC0_V
133A_CM_CLKSEL2_PLL_S:
134 .word A_CM_CLKSEL2_PLL_V
135A_CM_CLKEN_PLL:
136 .word A_CM_CLKEN_PLL_V
137A_SDRC_DLLA_CTRL_S:
138 .word A_SDRC_DLLA_CTRL_V
139A_SDRC_MANUAL_S:
140 .word A_SDRC_MANUAL_V
141
142ENTRY(omap24xx_cpu_suspend_sz)
143 .word . - omap24xx_cpu_suspend
144
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index 2a869e203342..d261e4ff4d9b 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/sram.S 2 * linux/arch/arm/mach-omap2/sram.S
3 * 3 *
4 * Omap2 specific functions that need to be run in internal SRAM 4 * Omap2 specific functions that need to be run in internal SRAM
5 * 5 *
@@ -28,7 +28,7 @@
28#include <asm/arch/io.h> 28#include <asm/arch/io.h>
29#include <asm/hardware.h> 29#include <asm/hardware.h>
30 30
31#include <asm/arch/prcm.h> 31#include "prcm-regs.h"
32 32
33#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010) 33#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
34 34
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 02:34:01 -0500