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authorTony Lindgren <tony@atomide.com>2010-07-05 09:31:36 -0400
committerTony Lindgren <tony@atomide.com>2010-07-05 09:31:36 -0400
commitfc44046167f08f3887e9685efc95f817a5ff45a1 (patch)
tree1a5379e44db9d9abd090ed82846898bd4d2719d6 /arch/arm/mach-omap2
parentac1c94fb85a07f6777a1becf9b793e30ebbaaa2b (diff)
omap: mux: Add data for 2420
Add data for 2420. Big thanks to Paul Walmsley <paul@pwsan.com> for generating usable mux data out of TRMs. Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig6
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/mux.h8
-rw-r--r--arch/arm/mach-omap2/mux2420.c688
-rw-r--r--arch/arm/mach-omap2/mux2420.h282
5 files changed, 985 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b31b6f123122..d3932d3a1166 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -17,6 +17,12 @@ config ARCH_OMAP3430
17 depends on ARCH_OMAP3 17 depends on ARCH_OMAP3
18 select ARCH_OMAP_OTG 18 select ARCH_OMAP_OTG
19 19
20config OMAP_PACKAGE_ZAF
21 bool
22
23config OMAP_PACKAGE_ZAC
24 bool
25
20config OMAP_PACKAGE_CBC 26config OMAP_PACKAGE_CBC
21 bool 27 bool
22 28
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 3b384188e28e..911781c81063 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -36,6 +36,7 @@ AFLAGS_sram243x.o :=-Wa,-march=armv6
36AFLAGS_sram34xx.o :=-Wa,-march=armv7-a 36AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
37 37
38# Pin multiplexing 38# Pin multiplexing
39obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
39obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o 40obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
40 41
41# SMS/SDRC 42# SMS/SDRC
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 937a8ca02e12..e14cd4dc9a4d 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -7,6 +7,7 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9 9
10#include "mux2420.h"
10#include "mux34xx.h" 11#include "mux34xx.h"
11 12
12#define OMAP_MUX_TERMINATOR 0xffff 13#define OMAP_MUX_TERMINATOR 0xffff
@@ -173,6 +174,13 @@ void omap_mux_write(u16 val, u16 mux_offset);
173void omap_mux_write_array(struct omap_board_mux *board_mux); 174void omap_mux_write_array(struct omap_board_mux *board_mux);
174 175
175/** 176/**
177 * omap2420_mux_init() - initialize mux system with board specific set
178 * @board_mux: Board specific mux table
179 * @flags: OMAP package type used for the board
180 */
181int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
182
183/**
176 * omap3_mux_init() - initialize mux system with board specific set 184 * omap3_mux_init() - initialize mux system with board specific set
177 * @board_mux: Board specific mux table 185 * @board_mux: Board specific mux table
178 * @flags: OMAP package type used for the board 186 * @flags: OMAP package type used for the board
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
new file mode 100644
index 000000000000..fdb04a7eb8aa
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -0,0 +1,688 @@
1/*
2 * Copyright (C) 2010 Nokia
3 * Copyright (C) 2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP2420_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap2420
42 */
43static struct omap_mux __initdata omap2420_muxmodes[] = {
44 _OMAP2420_MUXENTRY(CAM_D0, 54,
45 "cam_d0", "hw_dbg2", "sti_dout", "gpio_54",
46 NULL, NULL, "etk_d2", NULL),
47 _OMAP2420_MUXENTRY(CAM_D1, 53,
48 "cam_d1", "hw_dbg3", "sti_din", "gpio_53",
49 NULL, NULL, "etk_d3", NULL),
50 _OMAP2420_MUXENTRY(CAM_D2, 52,
51 "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52",
52 NULL, NULL, "etk_d4", NULL),
53 _OMAP2420_MUXENTRY(CAM_D3, 51,
54 "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51",
55 NULL, NULL, "etk_d5", NULL),
56 _OMAP2420_MUXENTRY(CAM_D4, 50,
57 "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50",
58 NULL, NULL, "etk_d6", NULL),
59 _OMAP2420_MUXENTRY(CAM_D5, 49,
60 "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49",
61 NULL, NULL, "etk_d7", NULL),
62 _OMAP2420_MUXENTRY(CAM_D6, 0,
63 "cam_d6", "hw_dbg8", NULL, NULL,
64 NULL, NULL, "etk_d8", NULL),
65 _OMAP2420_MUXENTRY(CAM_D7, 0,
66 "cam_d7", "hw_dbg9", NULL, NULL,
67 NULL, NULL, "etk_d9", NULL),
68 _OMAP2420_MUXENTRY(CAM_D8, 54,
69 "cam_d8", "hw_dbg10", NULL, "gpio_54",
70 NULL, NULL, "etk_d10", NULL),
71 _OMAP2420_MUXENTRY(CAM_D9, 53,
72 "cam_d9", "hw_dbg11", NULL, "gpio_53",
73 NULL, NULL, "etk_d11", NULL),
74 _OMAP2420_MUXENTRY(CAM_HS, 55,
75 "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55",
76 NULL, NULL, "etk_d1", NULL),
77 _OMAP2420_MUXENTRY(CAM_LCLK, 57,
78 "cam_lclk", NULL, "mcbsp_clks", "gpio_57",
79 NULL, NULL, "etk_c1", NULL),
80 _OMAP2420_MUXENTRY(CAM_VS, 56,
81 "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56",
82 NULL, NULL, "etk_d0", NULL),
83 _OMAP2420_MUXENTRY(CAM_XCLK, 0,
84 "cam_xclk", NULL, "sti_clk", NULL,
85 NULL, NULL, "etk_c2", NULL),
86 _OMAP2420_MUXENTRY(DSS_ACBIAS, 48,
87 "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
88 NULL, NULL, NULL, NULL),
89 _OMAP2420_MUXENTRY(DSS_DATA10, 40,
90 "dss_data10", NULL, NULL, "gpio_40",
91 NULL, NULL, NULL, NULL),
92 _OMAP2420_MUXENTRY(DSS_DATA11, 41,
93 "dss_data11", NULL, NULL, "gpio_41",
94 NULL, NULL, NULL, NULL),
95 _OMAP2420_MUXENTRY(DSS_DATA12, 42,
96 "dss_data12", NULL, NULL, "gpio_42",
97 NULL, NULL, NULL, NULL),
98 _OMAP2420_MUXENTRY(DSS_DATA13, 43,
99 "dss_data13", NULL, NULL, "gpio_43",
100 NULL, NULL, NULL, NULL),
101 _OMAP2420_MUXENTRY(DSS_DATA14, 44,
102 "dss_data14", NULL, NULL, "gpio_44",
103 NULL, NULL, NULL, NULL),
104 _OMAP2420_MUXENTRY(DSS_DATA15, 45,
105 "dss_data15", NULL, NULL, "gpio_45",
106 NULL, NULL, NULL, NULL),
107 _OMAP2420_MUXENTRY(DSS_DATA16, 46,
108 "dss_data16", NULL, NULL, "gpio_46",
109 NULL, NULL, NULL, NULL),
110 _OMAP2420_MUXENTRY(DSS_DATA17, 47,
111 "dss_data17", NULL, NULL, "gpio_47",
112 NULL, NULL, NULL, NULL),
113 _OMAP2420_MUXENTRY(DSS_DATA8, 38,
114 "dss_data8", NULL, NULL, "gpio_38",
115 NULL, NULL, NULL, NULL),
116 _OMAP2420_MUXENTRY(DSS_DATA9, 39,
117 "dss_data9", NULL, NULL, "gpio_39",
118 NULL, NULL, NULL, NULL),
119 _OMAP2420_MUXENTRY(EAC_AC_DIN, 115,
120 "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115",
121 NULL, NULL, NULL, NULL),
122 _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116,
123 "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116",
124 NULL, NULL, NULL, NULL),
125 _OMAP2420_MUXENTRY(EAC_AC_FS, 114,
126 "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114",
127 NULL, NULL, NULL, NULL),
128 _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117,
129 "eac_ac_mclk", NULL, NULL, "gpio_117",
130 NULL, NULL, NULL, NULL),
131 _OMAP2420_MUXENTRY(EAC_AC_RST, 118,
132 "eac_ac_rst", "eac_bt_din", NULL, "gpio_118",
133 NULL, NULL, NULL, NULL),
134 _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113,
135 "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113",
136 NULL, NULL, NULL, NULL),
137 _OMAP2420_MUXENTRY(EAC_BT_DIN, 73,
138 "eac_bt_din", NULL, NULL, "gpio_73",
139 NULL, NULL, "etk_d9", NULL),
140 _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74,
141 "eac_bt_dout", NULL, "sti_clk", "gpio_74",
142 NULL, NULL, "etk_d8", NULL),
143 _OMAP2420_MUXENTRY(EAC_BT_FS, 72,
144 "eac_bt_fs", NULL, NULL, "gpio_72",
145 NULL, NULL, "etk_d10", NULL),
146 _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71,
147 "eac_bt_sclk", NULL, NULL, "gpio_71",
148 NULL, NULL, "etk_d11", NULL),
149 _OMAP2420_MUXENTRY(GPIO_119, 119,
150 "gpio_119", NULL, "sti_din", "gpio_119",
151 NULL, "sys_boot0", "etk_d12", NULL),
152 _OMAP2420_MUXENTRY(GPIO_120, 120,
153 "gpio_120", NULL, "sti_dout", "gpio_120",
154 "cam_d9", "sys_boot1", "etk_d13", NULL),
155 _OMAP2420_MUXENTRY(GPIO_121, 121,
156 "gpio_121", NULL, NULL, "gpio_121",
157 "jtag_emu2", "sys_boot2", "etk_d14", NULL),
158 _OMAP2420_MUXENTRY(GPIO_122, 122,
159 "gpio_122", NULL, NULL, "gpio_122",
160 "jtag_emu3", "sys_boot3", "etk_d15", NULL),
161 _OMAP2420_MUXENTRY(GPIO_124, 124,
162 "gpio_124", NULL, NULL, "gpio_124",
163 NULL, "sys_boot5", NULL, NULL),
164 _OMAP2420_MUXENTRY(GPIO_125, 125,
165 "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125",
166 NULL, NULL, NULL, NULL),
167 _OMAP2420_MUXENTRY(GPIO_36, 36,
168 "gpio_36", NULL, NULL, "gpio_36",
169 NULL, "sys_boot4", NULL, NULL),
170 _OMAP2420_MUXENTRY(GPIO_62, 62,
171 "gpio_62", "uart1_rx", "usb1_dat", "gpio_62",
172 NULL, NULL, NULL, NULL),
173 _OMAP2420_MUXENTRY(GPIO_6, 6,
174 "gpio_6", "tv_detpulse", NULL, "gpio_6",
175 NULL, NULL, NULL, NULL),
176 _OMAP2420_MUXENTRY(GPMC_A10, 3,
177 "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3",
178 NULL, NULL, NULL, NULL),
179 _OMAP2420_MUXENTRY(GPMC_A1, 12,
180 "gpmc_a1", "dss_data18", NULL, "gpio_12",
181 NULL, NULL, NULL, NULL),
182 _OMAP2420_MUXENTRY(GPMC_A2, 11,
183 "gpmc_a2", "dss_data19", NULL, "gpio_11",
184 NULL, NULL, NULL, NULL),
185 _OMAP2420_MUXENTRY(GPMC_A3, 10,
186 "gpmc_a3", "dss_data20", NULL, "gpio_10",
187 NULL, NULL, NULL, NULL),
188 _OMAP2420_MUXENTRY(GPMC_A4, 9,
189 "gpmc_a4", "dss_data21", NULL, "gpio_9",
190 NULL, NULL, NULL, NULL),
191 _OMAP2420_MUXENTRY(GPMC_A5, 8,
192 "gpmc_a5", "dss_data22", NULL, "gpio_8",
193 NULL, NULL, NULL, NULL),
194 _OMAP2420_MUXENTRY(GPMC_A6, 7,
195 "gpmc_a6", "dss_data23", NULL, "gpio_7",
196 NULL, NULL, NULL, NULL),
197 _OMAP2420_MUXENTRY(GPMC_A7, 6,
198 "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6",
199 NULL, NULL, NULL, NULL),
200 _OMAP2420_MUXENTRY(GPMC_A8, 5,
201 "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5",
202 NULL, NULL, NULL, NULL),
203 _OMAP2420_MUXENTRY(GPMC_A9, 4,
204 "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4",
205 NULL, NULL, NULL, NULL),
206 _OMAP2420_MUXENTRY(GPMC_CLK, 21,
207 "gpmc_clk", NULL, NULL, "gpio_21",
208 NULL, NULL, NULL, NULL),
209 _OMAP2420_MUXENTRY(GPMC_D10, 18,
210 "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18",
211 NULL, NULL, NULL, NULL),
212 _OMAP2420_MUXENTRY(GPMC_D11, 17,
213 "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17",
214 NULL, NULL, NULL, NULL),
215 _OMAP2420_MUXENTRY(GPMC_D12, 16,
216 "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16",
217 NULL, NULL, NULL, NULL),
218 _OMAP2420_MUXENTRY(GPMC_D13, 15,
219 "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15",
220 NULL, NULL, NULL, NULL),
221 _OMAP2420_MUXENTRY(GPMC_D14, 14,
222 "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14",
223 NULL, NULL, NULL, NULL),
224 _OMAP2420_MUXENTRY(GPMC_D15, 13,
225 "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13",
226 NULL, NULL, NULL, NULL),
227 _OMAP2420_MUXENTRY(GPMC_D8, 20,
228 "gpmc_d8", NULL, NULL, "gpio_20",
229 NULL, NULL, NULL, NULL),
230 _OMAP2420_MUXENTRY(GPMC_D9, 19,
231 "gpmc_d9", "ssi2_wake", NULL, "gpio_19",
232 NULL, NULL, NULL, NULL),
233 _OMAP2420_MUXENTRY(GPMC_NBE0, 29,
234 "gpmc_nbe0", NULL, NULL, "gpio_29",
235 NULL, NULL, NULL, NULL),
236 _OMAP2420_MUXENTRY(GPMC_NBE1, 30,
237 "gpmc_nbe1", NULL, NULL, "gpio_30",
238 NULL, NULL, NULL, NULL),
239 _OMAP2420_MUXENTRY(GPMC_NCS1, 22,
240 "gpmc_ncs1", NULL, NULL, "gpio_22",
241 NULL, NULL, NULL, NULL),
242 _OMAP2420_MUXENTRY(GPMC_NCS2, 23,
243 "gpmc_ncs2", NULL, NULL, "gpio_23",
244 NULL, NULL, NULL, NULL),
245 _OMAP2420_MUXENTRY(GPMC_NCS3, 24,
246 "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
247 NULL, NULL, NULL, NULL),
248 _OMAP2420_MUXENTRY(GPMC_NCS4, 25,
249 "gpmc_ncs4", NULL, NULL, "gpio_25",
250 NULL, NULL, NULL, NULL),
251 _OMAP2420_MUXENTRY(GPMC_NCS5, 26,
252 "gpmc_ncs5", NULL, NULL, "gpio_26",
253 NULL, NULL, NULL, NULL),
254 _OMAP2420_MUXENTRY(GPMC_NCS6, 27,
255 "gpmc_ncs6", NULL, NULL, "gpio_27",
256 NULL, NULL, NULL, NULL),
257 _OMAP2420_MUXENTRY(GPMC_NCS7, 28,
258 "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL,
259 NULL, NULL, NULL, NULL),
260 _OMAP2420_MUXENTRY(GPMC_NWP, 31,
261 "gpmc_nwp", NULL, NULL, "gpio_31",
262 NULL, NULL, NULL, NULL),
263 _OMAP2420_MUXENTRY(GPMC_WAIT1, 33,
264 "gpmc_wait1", NULL, NULL, "gpio_33",
265 NULL, NULL, NULL, NULL),
266 _OMAP2420_MUXENTRY(GPMC_WAIT2, 34,
267 "gpmc_wait2", NULL, NULL, "gpio_34",
268 NULL, NULL, NULL, NULL),
269 _OMAP2420_MUXENTRY(GPMC_WAIT3, 35,
270 "gpmc_wait3", NULL, NULL, "gpio_35",
271 NULL, NULL, NULL, NULL),
272 _OMAP2420_MUXENTRY(HDQ_SIO, 101,
273 "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
274 NULL, NULL, NULL, NULL),
275 _OMAP2420_MUXENTRY(I2C2_SCL, 99,
276 "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99",
277 NULL, NULL, NULL, NULL),
278 _OMAP2420_MUXENTRY(I2C2_SDA, 100,
279 "i2c2_sda", NULL, "spi2_ncs1", "gpio_100",
280 NULL, NULL, NULL, NULL),
281 _OMAP2420_MUXENTRY(JTAG_EMU0, 127,
282 "jtag_emu0", NULL, NULL, "gpio_127",
283 NULL, NULL, NULL, NULL),
284 _OMAP2420_MUXENTRY(JTAG_EMU1, 126,
285 "jtag_emu1", NULL, NULL, "gpio_126",
286 NULL, NULL, NULL, NULL),
287 _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92,
288 "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92",
289 NULL, NULL, NULL, NULL),
290 _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98,
291 "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98",
292 NULL, NULL, NULL, NULL),
293 _OMAP2420_MUXENTRY(MCBSP1_DR, 95,
294 "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95",
295 NULL, NULL, NULL, NULL),
296 _OMAP2420_MUXENTRY(MCBSP1_DX, 94,
297 "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94",
298 NULL, NULL, NULL, NULL),
299 _OMAP2420_MUXENTRY(MCBSP1_FSR, 93,
300 "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93",
301 "spi2_ncs1", NULL, NULL, NULL),
302 _OMAP2420_MUXENTRY(MCBSP1_FSX, 97,
303 "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
304 NULL, NULL, NULL, NULL),
305 _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12,
306 "mcbsp2_clkx", NULL, "dss_data23", "gpio_12",
307 NULL, NULL, NULL, NULL),
308 _OMAP2420_MUXENTRY(MCBSP2_DR, 11,
309 "mcbsp2_dr", NULL, "dss_data22", "gpio_11",
310 NULL, NULL, NULL, NULL),
311 _OMAP2420_MUXENTRY(MCBSP_CLKS, 96,
312 "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96",
313 NULL, NULL, NULL, NULL),
314 _OMAP2420_MUXENTRY(MMC_CLKI, 59,
315 "sdmmc_clki", "ms_clki", NULL, "gpio_59",
316 NULL, NULL, NULL, NULL),
317 _OMAP2420_MUXENTRY(MMC_CLKO, 0,
318 "sdmmc_clko", "ms_clko", NULL, NULL,
319 NULL, NULL, NULL, NULL),
320 _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8,
321 "sdmmc_cmd_dir", NULL, NULL, "gpio_8",
322 NULL, NULL, NULL, NULL),
323 _OMAP2420_MUXENTRY(MMC_CMD, 0,
324 "sdmmc_cmd", "ms_bs", NULL, NULL,
325 NULL, NULL, NULL, NULL),
326 _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7,
327 "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7",
328 NULL, NULL, NULL, NULL),
329 _OMAP2420_MUXENTRY(MMC_DAT0, 0,
330 "sdmmc_dat0", "ms_dat0", NULL, NULL,
331 NULL, NULL, NULL, NULL),
332 _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78,
333 "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78",
334 NULL, NULL, NULL, NULL),
335 _OMAP2420_MUXENTRY(MMC_DAT1, 75,
336 "sdmmc_dat1", "ms_dat1", NULL, "gpio_75",
337 NULL, NULL, NULL, NULL),
338 _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79,
339 "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79",
340 NULL, NULL, NULL, NULL),
341 _OMAP2420_MUXENTRY(MMC_DAT2, 76,
342 "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76",
343 NULL, NULL, NULL, NULL),
344 _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80,
345 "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80",
346 NULL, NULL, NULL, NULL),
347 _OMAP2420_MUXENTRY(MMC_DAT3, 77,
348 "sdmmc_dat3", "ms_dat3", NULL, "gpio_77",
349 NULL, NULL, NULL, NULL),
350 _OMAP2420_MUXENTRY(SDRC_A12, 2,
351 "sdrc_a12", NULL, NULL, "gpio_2",
352 NULL, NULL, NULL, NULL),
353 _OMAP2420_MUXENTRY(SDRC_A13, 1,
354 "sdrc_a13", NULL, NULL, "gpio_1",
355 NULL, NULL, NULL, NULL),
356 _OMAP2420_MUXENTRY(SDRC_A14, 0,
357 "sdrc_a14", NULL, NULL, "gpio_0",
358 NULL, NULL, NULL, NULL),
359 _OMAP2420_MUXENTRY(SDRC_CKE1, 38,
360 "sdrc_cke1", NULL, NULL, "gpio_38",
361 NULL, NULL, NULL, NULL),
362 _OMAP2420_MUXENTRY(SDRC_NCS1, 37,
363 "sdrc_ncs1", NULL, NULL, "gpio_37",
364 NULL, NULL, NULL, NULL),
365 _OMAP2420_MUXENTRY(SPI1_CLK, 81,
366 "spi1_clk", NULL, NULL, "gpio_81",
367 NULL, NULL, NULL, NULL),
368 _OMAP2420_MUXENTRY(SPI1_NCS0, 84,
369 "spi1_ncs0", NULL, NULL, "gpio_84",
370 NULL, NULL, NULL, NULL),
371 _OMAP2420_MUXENTRY(SPI1_NCS1, 85,
372 "spi1_ncs1", NULL, NULL, "gpio_85",
373 NULL, NULL, NULL, NULL),
374 _OMAP2420_MUXENTRY(SPI1_NCS2, 86,
375 "spi1_ncs2", NULL, NULL, "gpio_86",
376 NULL, NULL, NULL, NULL),
377 _OMAP2420_MUXENTRY(SPI1_NCS3, 87,
378 "spi1_ncs3", NULL, NULL, "gpio_87",
379 NULL, NULL, NULL, NULL),
380 _OMAP2420_MUXENTRY(SPI1_SIMO, 82,
381 "spi1_simo", NULL, NULL, "gpio_82",
382 NULL, NULL, NULL, NULL),
383 _OMAP2420_MUXENTRY(SPI1_SOMI, 83,
384 "spi1_somi", NULL, NULL, "gpio_83",
385 NULL, NULL, NULL, NULL),
386 _OMAP2420_MUXENTRY(SPI2_CLK, 88,
387 "spi2_clk", NULL, NULL, "gpio_88",
388 NULL, NULL, NULL, NULL),
389 _OMAP2420_MUXENTRY(SPI2_NCS0, 91,
390 "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91",
391 NULL, NULL, NULL, NULL),
392 _OMAP2420_MUXENTRY(SPI2_SIMO, 89,
393 "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
394 NULL, NULL, NULL, NULL),
395 _OMAP2420_MUXENTRY(SPI2_SOMI, 90,
396 "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
397 NULL, NULL, NULL, NULL),
398 _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63,
399 "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63",
400 NULL, NULL, NULL, NULL),
401 _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59,
402 "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
403 NULL, NULL, NULL, NULL),
404 _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64,
405 "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64",
406 NULL, NULL, NULL, NULL),
407 _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25,
408 "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25",
409 NULL, NULL, NULL, NULL),
410 _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65,
411 "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65",
412 NULL, NULL, NULL, NULL),
413 _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61,
414 "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
415 NULL, NULL, NULL, NULL),
416 _OMAP2420_MUXENTRY(SSI1_WAKE, 66,
417 "ssi1_wake", "eac_md_fs", NULL, "gpio_66",
418 NULL, NULL, NULL, NULL),
419 _OMAP2420_MUXENTRY(SYS_CLKOUT, 123,
420 "sys_clkout", NULL, NULL, "gpio_123",
421 NULL, NULL, NULL, NULL),
422 _OMAP2420_MUXENTRY(SYS_CLKREQ, 52,
423 "sys_clkreq", NULL, NULL, "gpio_52",
424 NULL, NULL, NULL, NULL),
425 _OMAP2420_MUXENTRY(SYS_NIRQ, 60,
426 "sys_nirq", NULL, NULL, "gpio_60",
427 NULL, NULL, NULL, NULL),
428 _OMAP2420_MUXENTRY(UART1_CTS, 32,
429 "uart1_cts", NULL, "dss_data18", "gpio_32",
430 NULL, NULL, NULL, NULL),
431 _OMAP2420_MUXENTRY(UART1_RTS, 8,
432 "uart1_rts", NULL, "dss_data19", "gpio_8",
433 NULL, NULL, NULL, NULL),
434 _OMAP2420_MUXENTRY(UART1_RX, 10,
435 "uart1_rx", NULL, "dss_data21", "gpio_10",
436 NULL, NULL, NULL, NULL),
437 _OMAP2420_MUXENTRY(UART1_TX, 9,
438 "uart1_tx", NULL, "dss_data20", "gpio_9",
439 NULL, NULL, NULL, NULL),
440 _OMAP2420_MUXENTRY(UART2_CTS, 67,
441 "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
442 NULL, NULL, NULL, NULL),
443 _OMAP2420_MUXENTRY(UART2_RTS, 68,
444 "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
445 NULL, NULL, NULL, NULL),
446 _OMAP2420_MUXENTRY(UART2_RX, 70,
447 "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
448 NULL, NULL, NULL, NULL),
449 _OMAP2420_MUXENTRY(UART2_TX, 69,
450 "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
451 NULL, NULL, NULL, NULL),
452 _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102,
453 "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
454 NULL, NULL, NULL, NULL),
455 _OMAP2420_MUXENTRY(UART3_RTS_SD, 103,
456 "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
457 NULL, NULL, NULL, NULL),
458 _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105,
459 "uart3_rx_irrx", NULL, NULL, "gpio_105",
460 NULL, NULL, NULL, NULL),
461 _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104,
462 "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
463 NULL, NULL, NULL, NULL),
464 _OMAP2420_MUXENTRY(USB0_DAT, 112,
465 "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112",
466 "uart2_tx", NULL, NULL, NULL),
467 _OMAP2420_MUXENTRY(USB0_PUEN, 106,
468 "usb0_puen", "mcbsp2_dx", NULL, "gpio_106",
469 NULL, NULL, NULL, NULL),
470 _OMAP2420_MUXENTRY(USB0_RCV, 109,
471 "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109",
472 "uart2_cts", NULL, NULL, NULL),
473 _OMAP2420_MUXENTRY(USB0_SE0, 111,
474 "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111",
475 "uart2_rx", NULL, NULL, NULL),
476 _OMAP2420_MUXENTRY(USB0_TXEN, 110,
477 "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110",
478 NULL, NULL, NULL, NULL),
479 _OMAP2420_MUXENTRY(USB0_VM, 108,
480 "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108",
481 "uart2_rx", NULL, NULL, NULL),
482 _OMAP2420_MUXENTRY(USB0_VP, 107,
483 "usb0_vp", "mcbsp2_dr", NULL, "gpio_107",
484 NULL, NULL, NULL, NULL),
485 _OMAP2420_MUXENTRY(VLYNQ_CLK, 13,
486 "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13",
487 NULL, NULL, NULL, NULL),
488 _OMAP2420_MUXENTRY(VLYNQ_NLA, 58,
489 "vlynq_nla", NULL, NULL, "gpio_58",
490 "cam_d6", NULL, NULL, NULL),
491 _OMAP2420_MUXENTRY(VLYNQ_RX0, 15,
492 "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15",
493 "cam_d7", NULL, NULL, NULL),
494 _OMAP2420_MUXENTRY(VLYNQ_RX1, 14,
495 "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14",
496 "cam_d8", NULL, NULL, NULL),
497 _OMAP2420_MUXENTRY(VLYNQ_TX0, 17,
498 "vlynq_tx0", "usb2_txen", NULL, "gpio_17",
499 NULL, NULL, NULL, NULL),
500 _OMAP2420_MUXENTRY(VLYNQ_TX1, 16,
501 "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16",
502 NULL, NULL, NULL, NULL),
503 { .reg_offset = OMAP_MUX_TERMINATOR },
504};
505
506/*
507 * Balls for 447-pin POP package
508 */
509#ifdef CONFIG_DEBUG_FS
510struct omap_ball __initdata omap2420_pop_ball[] = {
511 _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
512 _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
513 _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
514 _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL),
515 _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL),
516 _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL),
517 _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL),
518 _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL),
519 _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL),
520 _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL),
521 _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL),
522 _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL),
523 _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL),
524 _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL),
525 _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL),
526 _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL),
527 _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL),
528 _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL),
529 _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL),
530 _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL),
531 _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL),
532 _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL),
533 _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL),
534 _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL),
535 _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL),
536 _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL),
537 _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL),
538 _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL),
539 _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL),
540 _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL),
541 _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL),
542 _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL),
543 _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL),
544 _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL),
545 _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL),
546 _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL),
547 _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL),
548 _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL),
549 _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL),
550 _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL),
551 _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL),
552 _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL),
553 _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL),
554 _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL),
555 _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL),
556 _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL),
557 _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL),
558 _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL),
559 _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL),
560 _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL),
561 _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL),
562 _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL),
563 _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL),
564 _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL),
565 _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"),
566 _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"),
567 _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"),
568 _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"),
569 _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"),
570 _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"),
571 _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"),
572 _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"),
573 _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"),
574 _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"),
575 _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL),
576 _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"),
577 _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL),
578 _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL),
579 _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL),
580 _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL),
581 _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL),
582 _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL),
583 _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"),
584 _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"),
585 _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL),
586 _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL),
587 _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL),
588 _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL),
589 _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL),
590 _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL),
591 _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL),
592 _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL),
593 _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL),
594 _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL),
595 _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL),
596 _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL),
597 _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL),
598 _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL),
599 _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL),
600 _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL),
601 _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL),
602 _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL),
603 _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL),
604 _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL),
605 _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL),
606 _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL),
607 _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL),
608 _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL),
609 _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL),
610 _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL),
611 _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL),
612 _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL),
613 _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"),
614 _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"),
615 _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"),
616 _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"),
617 _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"),
618 _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL),
619 _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL),
620 _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL),
621 _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL),
622 _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL),
623 _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL),
624 _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL),
625 _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL),
626 _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL),
627 _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL),
628 _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL),
629 _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL),
630 _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL),
631 _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL),
632 _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL),
633 _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL),
634 _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL),
635 _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL),
636 _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL),
637 _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL),
638 _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL),
639 _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL),
640 _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL),
641 _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL),
642 _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL),
643 _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL),
644 _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL),
645 _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL),
646 _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL),
647 _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL),
648 _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL),
649 _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
650 _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
651 _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL),
652 _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL),
653 _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL),
654 _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL),
655 _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL),
656 _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL),
657 _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL),
658 _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL),
659 _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL),
660 _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL),
661 _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL),
662 _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL),
663 _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL),
664 { .reg_offset = OMAP_MUX_TERMINATOR },
665};
666#else
667#define omap2420_pop_ball NULL
668#endif
669
670int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
671{
672 struct omap_ball *package_balls = NULL;
673
674 switch (flags & OMAP_PACKAGE_MASK) {
675 case OMAP_PACKAGE_ZAC:
676 package_balls = omap2420_pop_ball;
677 break;
678 case OMAP_PACKAGE_ZAF:
679 /* REVISIT: Please add data */
680 default:
681 pr_warning("mux: No ball data available for omap2420 package\n");
682 }
683
684 return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE,
685 OMAP2420_CONTROL_PADCONF_MUX_SIZE,
686 omap2420_muxmodes, NULL, board_subset,
687 package_balls);
688}
diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h
new file mode 100644
index 000000000000..0f555aa847b5
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2420.h
@@ -0,0 +1,282 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU
11
12#define OMAP2420_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x48000030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 8-bits wide.
24 */
25#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000
26#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001
27#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002
28#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003
29#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004
30#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005
31#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006
32#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007
33#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008
34#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009
35#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a
36#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b
37#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c
38#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d
39#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e
40#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f
41#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010
42#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021
43#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022
44#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023
45#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024
46#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025
47#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026
48#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027
49#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028
50#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029
51#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a
52#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b
53#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c
54#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d
55#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e
56#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f
57#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030
58#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031
59#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032
60#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033
61#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034
62#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035
63#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036
64#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037
65#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038
66#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039
67#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a
68#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b
69#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c
70#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d
71#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e
72#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f
73#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040
74#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041
75#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042
76#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043
77#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044
78#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045
79#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046
80#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047
81#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048
82#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049
83#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
84#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b
85#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c
86#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d
87#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e
88#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f
89#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050
90#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051
91#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052
92#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053
93#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054
94#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055
95#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056
96#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057
97#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058
98#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059
99#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a
100#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b
101#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c
102#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d
103#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e
104#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f
105#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060
106#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061
107#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062
108#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063
109#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064
110#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065
111#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066
112#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067
113#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068
114#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069
115#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a
116#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b
117#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c
118#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d
119#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e
120#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f
121#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070
122#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071
123#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072
124#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073
125#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074
126#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075
127#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076
128#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077
129#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078
130#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079
131#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a
132#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f
133#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080
134#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081
135#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082
136#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083
137#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084
138#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085
139#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086
140#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087
141#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088
142#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089
143#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a
144#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b
145#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c
146#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d
147#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e
148#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f
149#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090
150#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091
151#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092
152#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093
153#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094
154#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095
155#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096
156#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097
157#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098
158#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099
159#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a
160#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b
161#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c
162#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d
163#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e
164#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f
165#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0
166#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1
167#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2
168#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3
169#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4
170#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5
171#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6
172#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7
173#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8
174#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9
175#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa
176#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab
177#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac
178#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad
179#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae
180#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af
181#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0
182#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1
183#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2
184#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3
185#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4
186#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5
187#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6
188#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7
189#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8
190#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9
191#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba
192#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb
193#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc
194#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd
195#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be
196#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf
197#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0
198#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1
199#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2
200#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3
201#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4
202#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5
203#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6
204#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7
205#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8
206#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9
207#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca
208#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb
209#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc
210#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd
211#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce
212#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf
213#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0
214#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1
215#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2
216#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3
217#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4
218#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5
219#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6
220#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7
221#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8
222#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9
223#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da
224#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db
225#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc
226#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd
227#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de
228#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df
229#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0
230#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1
231#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2
232#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3
233#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4
234#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5
235#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6
236#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7
237#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8
238#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9
239#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea
240#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb
241#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec
242#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed
243#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee
244#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef
245#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0
246#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1
247#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2
248#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3
249#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4
250#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5
251#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6
252#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7
253#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8
254#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9
255#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa
256#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb
257#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc
258#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd
259#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe
260#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff
261#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100
262#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101
263#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102
264#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103
265#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104
266#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105
267#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106
268#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107
269#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108
270#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109
271#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a
272#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b
273#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c
274#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d
275#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e
276#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f
277#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110
278#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111
279#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112
280
281#define OMAP2420_CONTROL_PADCONF_MUX_SIZE \
282 (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 00:05:25 -0500