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authorPaul Walmsley <paul@pwsan.com>2011-02-25 17:51:02 -0500
committerPaul Walmsley <paul@pwsan.com>2011-03-07 22:19:39 -0500
commita1fed577ddc0ca0ec7cf5e5ee033fe3df4192ebd (patch)
treec75e097dcdedff201bd86c0ab3b4c272b207e266 /arch/arm/mach-omap2
parent4ef70c0694bf428d9f1d4722edaffa1dc5fa39e1 (diff)
OMAP2xxx: clock: fix parents for L3-derived clocks
Several clocks are listed as having the core L4 clock as their parent, when they are actually derived from the L3 clock. Fix these. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c2
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c6
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 68c03691e56a..693a0a84c33d 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1614,7 +1614,7 @@ static struct clk sdma_fck = {
1614static struct clk sdma_ick = { 1614static struct clk sdma_ick = {
1615 .name = "sdma_ick", 1615 .name = "sdma_ick",
1616 .ops = &clkops_omap2_iclk_idle_only, 1616 .ops = &clkops_omap2_iclk_idle_only,
1617 .parent = &l4_ck, 1617 .parent = &core_l3_ck,
1618 .clkdm_name = "core_l3_clkdm", 1618 .clkdm_name = "core_l3_clkdm",
1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1620 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, 1620 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 34daed9cd56f..f00f52ebfeaf 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1652,7 +1652,7 @@ static struct clk sdma_fck = {
1652static struct clk sdma_ick = { 1652static struct clk sdma_ick = {
1653 .name = "sdma_ick", 1653 .name = "sdma_ick",
1654 .ops = &clkops_omap2_iclk_idle_only, 1654 .ops = &clkops_omap2_iclk_idle_only,
1655 .parent = &l4_ck, 1655 .parent = &core_l3_ck,
1656 .clkdm_name = "core_l3_clkdm", 1656 .clkdm_name = "core_l3_clkdm",
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1658 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, 1658 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
@@ -1662,9 +1662,9 @@ static struct clk sdma_ick = {
1662static struct clk sdrc_ick = { 1662static struct clk sdrc_ick = {
1663 .name = "sdrc_ick", 1663 .name = "sdrc_ick",
1664 .ops = &clkops_omap2_iclk_idle_only, 1664 .ops = &clkops_omap2_iclk_idle_only,
1665 .parent = &l4_ck, 1665 .parent = &core_l3_ck,
1666 .flags = ENABLE_ON_INIT, 1666 .flags = ENABLE_ON_INIT,
1667 .clkdm_name = "core_l4_clkdm", 1667 .clkdm_name = "core_l3_clkdm",
1668 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1668 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1669 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 1669 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1670 .recalc = &followparent_recalc, 1670 .recalc = &followparent_recalc,