Merge tag 'omap-devel-pm-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm

From: Tony Lindgren <tony@atomide.com>:

Here are some omap PM changes that reimplement omap PRCM I/O chain
code for wake-ups, and improve idle latencies for cpuidle.

* tag 'omap-devel-pm-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
  ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
  ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
  ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
  ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
  ARM: OMAP3: PM: call pre/post transition per powerdomain
  ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
  ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
  ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
  ARM: OMAP3+: PRM: Enable IO wake up
  ARM: OMAP4: PRM: Add IO Daisychain support
  ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
  ARM: OMAP3: PM: correct enable/disable of daisy io chain
  ARM: OMAP2+: PRM: fix compile for OMAP4-only build

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

11 files changed, 216 insertions, 107 deletions

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 207bc1c7759f..e6ae3fe5cdc6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -77,20 +77,6 @@ static struct omap3_idle_statedata omap3_idle_data[] = {
 
 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
 
-static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
-                                struct clockdomain *clkdm)
-{
-        clkdm_allow_idle(clkdm);
-        return 0;
-}
-
-static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
-                                struct clockdomain *clkdm)
-{
-        clkdm_deny_idle(clkdm);
-        return 0;
-}
-
 static int __omap3_enter_idle(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index)
@@ -108,8 +94,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 
         /* Deny idle for C1 */
         if (index == 0) {
-                pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
-                pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
+                clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
+                clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
         }
 
         /*
@@ -131,8 +117,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 
         /* Re-allow idle for C1 */
         if (index == 0) {
-                pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
-                pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
+                clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
+                clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
         }
 
 return_sleep_time:
@@ -178,7 +164,7 @@ static int next_valid_state(struct cpuidle_device *dev,
         u32 mpu_deepest_state = PWRDM_POWER_RET;
         u32 core_deepest_state = PWRDM_POWER_RET;
         int idx;
-        int next_index = -1;
+        int next_index = 0; /* C1 is the default value */
 
         if (enable_off_mode) {
                 mpu_deepest_state = PWRDM_POWER_OFF;
@@ -209,12 +195,6 @@ static int next_valid_state(struct cpuidle_device *dev,
                 }
         }
 
-        /*
-         * C1 is always valid.
-         * So, no need to check for 'next_index == -1' outside
-         * this loop.
-         */
-
         return next_index;
 }
 
@@ -228,23 +208,22 @@ static int next_valid_state(struct cpuidle_device *dev,
  * the device to the specified or a safer state.
  */
 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
+                               struct cpuidle_driver *drv,
                                int index)
 {
         int new_state_idx;
-        u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
+        u32 core_next_state, per_next_state = 0, per_saved_state = 0;
         struct omap3_idle_statedata *cx;
         int ret;
 
         /*
-         * Prevent idle completely if CAM is active.
+         * Use only C1 if CAM is active.
          * CAM does not have wakeup capability in OMAP3.
          */
-        cam_state = pwrdm_read_pwrst(cam_pd);
-        if (cam_state == PWRDM_POWER_ON) {
+        if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
                 new_state_idx = drv->safe_state_index;
-                goto select_state;
-        }
+        else
+                new_state_idx = next_valid_state(dev, drv, index);
 
         /*
          * FIXME: we currently manage device-specific idle states
@@ -254,24 +233,28 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
          *        its own code.
          */
 
-        /*
-         * Prevent PER off if CORE is not in retention or off as this
-         * would disable PER wakeups completely.
-         */
-        cx = &omap3_idle_data[index];
+        /* Program PER state */
+        cx = &omap3_idle_data[new_state_idx];
         core_next_state = cx->core_state;
         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
-        if ((per_next_state == PWRDM_POWER_OFF) &&
-            (core_next_state > PWRDM_POWER_RET))
-                per_next_state = PWRDM_POWER_RET;
+        if (new_state_idx == 0) {
+                /* In C1 do not allow PER state lower than CORE state */
+                if (per_next_state < core_next_state)
+                        per_next_state = core_next_state;
+        } else {
+                /*
+                 * Prevent PER OFF if CORE is not in RETention or OFF as this
+                 * would disable PER wakeups completely.
+                 */
+                if ((per_next_state == PWRDM_POWER_OFF) &&
+                    (core_next_state > PWRDM_POWER_RET))
+                        per_next_state = PWRDM_POWER_RET;
+        }
 
         /* Are we changing PER target state? */
         if (per_next_state != per_saved_state)
                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 
-        new_state_idx = next_valid_state(dev, drv, index);
-
-select_state:
         ret = omap3_enter_idle(dev, drv, new_state_idx);
 
         /* Restore original PER state if it was modified */
@@ -288,7 +271,7 @@ struct cpuidle_driver omap3_idle_driver = {
         .owner =        THIS_MODULE,
         .states = {
                 {
-                        .enter            = omap3_enter_idle,
+                        .enter            = omap3_enter_idle_bm,
                         .exit_latency     = 2 + 2,
                         .target_residency = 5,
                         .flags            = CPUIDLE_FLAG_TIME_VALID,
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 13670aa84e58..e35a86bf4e1d 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -255,7 +255,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
                 return -ENXIO;
         }
 
-        pwrdm_pre_transition();
+        pwrdm_pre_transition(NULL);
 
         /*
          * Check MPUSS next state and save interrupt controller if needed.
@@ -287,7 +287,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
         wakeup_cpu = smp_processor_id();
         set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
 
-        pwrdm_post_transition();
+        pwrdm_post_transition(NULL);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 773193670ea2..09f44d56e026 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -153,6 +153,7 @@
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
+#include "pm.h"
 
 /* Maximum microseconds to wait for OMAP module to softreset */
 #define MAX_MODULE_SOFTRESET_WAIT       10000
@@ -172,6 +173,9 @@ static LIST_HEAD(omap_hwmod_list);
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
+/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
+static DEFINE_SPINLOCK(io_chain_lock);
+
 /*
  * linkspace: ptr to a buffer that struct omap_hwmod_link records are
  * allocated from - used to reduce the number of small memory
@@ -1738,6 +1742,32 @@ static int _reset(struct omap_hwmod *oh)
 }
 
 /**
+ * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
+ *
+ * Call the appropriate PRM function to clear any logged I/O chain
+ * wakeups and to reconfigure the chain.  This apparently needs to be
+ * done upon every mux change.  Since hwmods can be concurrently
+ * enabled and idled, hold a spinlock around the I/O chain
+ * reconfiguration sequence.  No return value.
+ *
+ * XXX When the PRM code is moved to drivers, this function can be removed,
+ * as the PRM infrastructure should abstract this.
+ */
+static void _reconfigure_io_chain(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&io_chain_lock, flags);
+
+        if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl())
+                omap3xxx_prm_reconfigure_io_chain();
+        else if (cpu_is_omap44xx())
+                omap44xx_prm_reconfigure_io_chain();
+
+        spin_unlock_irqrestore(&io_chain_lock, flags);
+}
+
+/**
  * _enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -1793,8 +1823,10 @@ static int _enable(struct omap_hwmod *oh)
         /* Mux pins for device runtime if populated */
         if (oh->mux && (!oh->mux->enabled ||
                         ((oh->_state == _HWMOD_STATE_IDLE) &&
-                         oh->mux->pads_dynamic)))
+                         oh->mux->pads_dynamic))) {
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+                _reconfigure_io_chain();
+        }
 
         _add_initiator_dep(oh, mpu_oh);
 
@@ -1883,8 +1915,10 @@ static int _idle(struct omap_hwmod *oh)
                 clkdm_hwmod_disable(oh->clkdm, oh);
 
         /* Mux pins for device idle if populated */
-        if (oh->mux && oh->mux->pads_dynamic)
+        if (oh->mux && oh->mux->pads_dynamic) {
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+                _reconfigure_io_chain();
+        }
 
         oh->_state = _HWMOD_STATE_IDLE;
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3a595e899724..e63fdd02c6f5 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -70,34 +70,6 @@ void (*omap3_do_wfi_sram)(void);
 
 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
-static struct powerdomain *cam_pwrdm;
-
-static void omap3_enable_io_chain(void)
-{
-        int timeout = 0;
-
-        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-                                   PM_WKEN);
-        /* Do a readback to assure write has been done */
-        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-
-        while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
-                 OMAP3430_ST_IO_CHAIN_MASK)) {
-                timeout++;
-                if (timeout > 1000) {
-                        pr_err("Wake up daisy chain activation failed.\n");
-                        return;
-                }
-                omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
-                                           WKUP_MOD, PM_WKEN);
-        }
-}
-
-static void omap3_disable_io_chain(void)
-{
-        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-                                     PM_WKEN);
-}
 
 static void omap3_core_save_context(void)
 {
@@ -299,24 +271,22 @@ void omap_sram_idle(void)
         /* Enable IO-PAD and IO-CHAIN wakeups */
         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-        if (omap3_has_io_wakeup() &&
-            (per_next_state < PWRDM_POWER_ON ||
-             core_next_state < PWRDM_POWER_ON)) {
-                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
-                if (omap3_has_io_chain_ctrl())
-                        omap3_enable_io_chain();
-        }
 
-        pwrdm_pre_transition();
+        if (mpu_next_state < PWRDM_POWER_ON) {
+                pwrdm_pre_transition(mpu_pwrdm);
+                pwrdm_pre_transition(neon_pwrdm);
+        }
 
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
+                pwrdm_pre_transition(per_pwrdm);
                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
                 omap2_gpio_prepare_for_idle(per_going_off);
         }
 
         /* CORE */
         if (core_next_state < PWRDM_POWER_ON) {
+                pwrdm_pre_transition(core_pwrdm);
                 if (core_next_state == PWRDM_POWER_OFF) {
                         omap3_core_save_context();
                         omap3_cm_save_context();
@@ -369,26 +339,20 @@ void omap_sram_idle(void)
                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                                OMAP3430_GR_MOD,
                                                OMAP3_PRM_VOLTCTRL_OFFSET);
+                pwrdm_post_transition(core_pwrdm);
         }
         omap3_intc_resume_idle();
 
-        pwrdm_post_transition();
-
         /* PER */
-        if (per_next_state < PWRDM_POWER_ON)
+        if (per_next_state < PWRDM_POWER_ON) {
                 omap2_gpio_resume_after_idle();
-
-        /* Disable IO-PAD and IO-CHAIN wakeup */
-        if (omap3_has_io_wakeup() &&
-            (per_next_state < PWRDM_POWER_ON ||
-             core_next_state < PWRDM_POWER_ON)) {
-                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
-                                             PM_WKEN);
-                if (omap3_has_io_chain_ctrl())
-                        omap3_disable_io_chain();
+                pwrdm_post_transition(per_pwrdm);
         }
 
-        clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
+        if (mpu_next_state < PWRDM_POWER_ON) {
+                pwrdm_post_transition(mpu_pwrdm);
+                pwrdm_post_transition(neon_pwrdm);
+        }
 }
 
 static void omap3_pm_idle(void)
@@ -749,7 +713,6 @@ int __init omap3_pm_init(void)
         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
         per_pwrdm = pwrdm_lookup("per_pwrdm");
         core_pwrdm = pwrdm_lookup("core_pwrdm");
-        cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 
         neon_clkdm = clkdm_lookup("neon_clkdm");
         mpu_clkdm = clkdm_lookup("mpu_clkdm");
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96114901b932..eefe179045e6 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -981,15 +981,23 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
         return ret;
 }
 
-int pwrdm_pre_transition(void)
+int pwrdm_pre_transition(struct powerdomain *pwrdm)
 {
-        pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
+        if (pwrdm)
+                _pwrdm_pre_transition_cb(pwrdm, NULL);
+        else
+                pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
+
         return 0;
 }
 
-int pwrdm_post_transition(void)
+int pwrdm_post_transition(struct powerdomain *pwrdm)
 {
-        pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
+        if (pwrdm)
+                _pwrdm_post_transition_cb(pwrdm, NULL);
+        else
+                pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8f88d65c46ea..a6a4604801ad 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -213,8 +213,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
 int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_pre_transition(void);
-int pwrdm_post_transition(void);
+int pwrdm_pre_transition(struct powerdomain *pwrdm);
+int pwrdm_post_transition(struct powerdomain *pwrdm);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6da3ba483ad1..fca23cbea708 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -410,6 +410,14 @@
  */
 #define MAX_MODULE_HARDRESET_WAIT               10000
 
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last
+ * pad of the I/O ring after asserting WUCLKIN high.  Tero measured
+ * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
+ * microseconds on OMAP4, so this timeout may be too high.
+ */
+#define MAX_IOPAD_LATCH_TIME                    100
+
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 21cb74003a56..a0309dea6794 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -302,11 +302,59 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
                                 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 }
 
+/**
+ * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
+ * return value.
+ */
+void omap3xxx_prm_reconfigure_io_chain(void)
+{
+        int i = 0;
+
+        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKEN);
+
+        omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+                          OMAP3430_ST_IO_CHAIN_MASK,
+                          MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+
+        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                     PM_WKEN);
+
+        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKST);
+
+        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+}
+
+/**
+ * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O
+ * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
+ * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
+ * No return value.
+ */
+static void __init omap3xxx_prm_enable_io_wakeup(void)
+{
+        if (omap3_has_io_wakeup())
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                           PM_WKEN);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
         int ret = 0;
 
         if (cpu_is_omap34xx()) {
+                omap3xxx_prm_enable_io_wakeup();
                 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
                 if (!ret)
                         irq_set_status_flags(omap_prcm_event_to_irq("io"),
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a19dc5f..a8c946f318ab 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -303,6 +303,8 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
 
+#endif  /* CONFIG_ARCH_OMAP4 */
+
 /* OMAP3-specific VP functions */
 u32 omap3_prm_vp_check_txdone(u8 vp_id);
 void omap3_prm_vp_clear_txdone(u8 vp_id);
@@ -315,14 +317,14 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
+extern void omap3xxx_prm_reconfigure_io_chain(void);
+
 /* PRM interrupt-related functions */
 extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
 extern void omap3xxx_prm_ocp_barrier(void);
 extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
 extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 
-#endif  /* CONFIG_ARCH_OMAP4 */
-
 #endif
 
 /*
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index f106d21ff581..bb727c2d9337 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -233,10 +233,71 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 }
 
+/**
+ * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
+ * No return value. XXX Are the final two steps necessary?
+ */
+void omap44xx_prm_reconfigure_io_chain(void)
+{
+        int i = 0;
+
+        /* Trigger WUCLKIN enable */
+        omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
+                                    OMAP4430_WUCLK_CTRL_MASK,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_IO_PMCTRL_OFFSET);
+        omap_test_timeout(
+                (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                           OMAP4_PRM_IO_PMCTRL_OFFSET) &
+                   OMAP4430_WUCLK_STATUS_MASK) >>
+                  OMAP4430_WUCLK_STATUS_SHIFT) == 1),
+                MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+
+        /* Trigger WUCLKIN disable */
+        omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_IO_PMCTRL_OFFSET);
+        omap_test_timeout(
+                (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                           OMAP4_PRM_IO_PMCTRL_OFFSET) &
+                   OMAP4430_WUCLK_STATUS_MASK) >>
+                  OMAP4430_WUCLK_STATUS_SHIFT) == 0),
+                MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line deassertion timed out\n");
+
+        return;
+}
+
+/**
+ * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O wakeups
+ * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
+ * omap44xx_prm_reconfigure_io_chain() must be called.  No return value.
+ */
+static void __init omap44xx_prm_enable_io_wakeup(void)
+{
+        omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+                                    OMAP4430_GLOBAL_WUEN_MASK,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_IO_PMCTRL_OFFSET);
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
-        if (cpu_is_omap44xx())
+        if (cpu_is_omap44xx()) {
+                omap44xx_prm_enable_io_wakeup();
                 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+        }
         return 0;
 }
 subsys_initcall(omap4xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7978092946db..ee72ae6bd8c9 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -763,6 +763,8 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
+extern void omap44xx_prm_reconfigure_io_chain(void);
+
 /* PRM interrupt-related functions */
 extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
 extern void omap44xx_prm_ocp_barrier(void);