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authorTony Lindgren <tony@atomide.com>2009-05-25 14:26:42 -0400
committerTony Lindgren <tony@atomide.com>2009-05-25 14:26:42 -0400
commit8e3bd351d1d2505e17d0b10c17bf8d7655eb9faf (patch)
treec1efd26ff3761d7f83984f51fd68e13cd686b1e5 /arch/arm/mach-omap2
parenta4ab0d836bbdbbfdb892135a92b339107530b710 (diff)
ARM: OMAP2/3: Remove OMAP_PRM_REGADDR and OMAP2_PRM_BASE
Remove OMAP_PRM_REGADDR and use processor specific defines instead. Also fold in a patch from Kevin Hilman to add _OFFSET #defines for the PRCM registers to be used with the prm_[read|write]_* macros. These are used extensively in the forthcoming OMAP PM support. Also remove now unused OMAP2_PRM_BASE. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clock.c4
-rw-r--r--arch/arm/mach-omap2/clock24xx.c21
-rw-r--r--arch/arm/mach-omap2/clock24xx.h9
-rw-r--r--arch/arm/mach-omap2/cm.h1
-rw-r--r--arch/arm/mach-omap2/prm.h205
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c5
-rw-r--r--arch/arm/mach-omap2/sram242x.S6
-rw-r--r--arch/arm/mach-omap2/sram243x.S6
8 files changed, 160 insertions, 97 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4247a1534411..dd37483f3d18 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -91,9 +91,9 @@ static void _omap2xxx_clk_commit(struct clk *clk)
91 return; 91 return;
92 92
93 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, 93 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
94 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); 94 OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
95 /* OCP barrier */ 95 /* OCP barrier */
96 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); 96 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
97} 97}
98 98
99/* 99/*
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index e4cef333e291..c442fe9f998a 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -233,6 +233,8 @@ static struct prcm_config *curr_prcm_set;
233static struct clk *vclk; 233static struct clk *vclk;
234static struct clk *sclk; 234static struct clk *sclk;
235 235
236static void __iomem *prcm_clksrc_ctrl;
237
236/*------------------------------------------------------------------------- 238/*-------------------------------------------------------------------------
237 * Omap24xx specific clock functions 239 * Omap24xx specific clock functions
238 *-------------------------------------------------------------------------*/ 240 *-------------------------------------------------------------------------*/
@@ -269,10 +271,9 @@ static int omap2_enable_osc_ck(struct clk *clk)
269{ 271{
270 u32 pcc; 272 u32 pcc;
271 273
272 pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); 274 pcc = __raw_readl(prcm_clksrc_ctrl);
273 275
274 __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, 276 __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
275 OMAP24XX_PRCM_CLKSRC_CTRL);
276 277
277 return 0; 278 return 0;
278} 279}
@@ -281,10 +282,9 @@ static void omap2_disable_osc_ck(struct clk *clk)
281{ 282{
282 u32 pcc; 283 u32 pcc;
283 284
284 pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); 285 pcc = __raw_readl(prcm_clksrc_ctrl);
285 286
286 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, 287 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
287 OMAP24XX_PRCM_CLKSRC_CTRL);
288} 288}
289 289
290static const struct clkops clkops_oscck = { 290static const struct clkops clkops_oscck = {
@@ -654,7 +654,7 @@ static u32 omap2_get_sysclkdiv(void)
654{ 654{
655 u32 div; 655 u32 div;
656 656
657 div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); 657 div = __raw_readl(prcm_clksrc_ctrl);
658 div &= OMAP_SYSCLKDIV_MASK; 658 div &= OMAP_SYSCLKDIV_MASK;
659 div >>= OMAP_SYSCLKDIV_SHIFT; 659 div >>= OMAP_SYSCLKDIV_SHIFT;
660 660
@@ -714,10 +714,13 @@ int __init omap2_clk_init(void)
714 struct omap_clk *c; 714 struct omap_clk *c;
715 u32 clkrate; 715 u32 clkrate;
716 716
717 if (cpu_is_omap242x()) 717 if (cpu_is_omap242x()) {
718 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
718 cpu_mask = RATE_IN_242X; 719 cpu_mask = RATE_IN_242X;
719 else if (cpu_is_omap2430()) 720 } else if (cpu_is_omap2430()) {
721 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
720 cpu_mask = RATE_IN_243X; 722 cpu_mask = RATE_IN_243X;
723 }
721 724
722 clk_init(&omap2_clk_functions); 725 clk_init(&omap2_clk_functions);
723 726
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 88c5acb40fcf..f0e4480b4ebe 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,6 +24,15 @@
24#include "cm-regbits-24xx.h" 24#include "cm-regbits-24xx.h"
25#include "sdrc.h" 25#include "sdrc.h"
26 26
27/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
28#ifdef CONFIG_ARCH_OMAP2420
29#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
30#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
31#else
32#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
33#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
34#endif
35
27static unsigned long omap2_table_mpu_recalc(struct clk *clk); 36static unsigned long omap2_table_mpu_recalc(struct clk *clk);
28static int omap2_select_table_rate(struct clk *clk, unsigned long rate); 37static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); 38static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 65fdf78c91e1..efc082a1d271 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -38,6 +38,7 @@
38#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) 38#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010)
39#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) 39#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c)
40 40
41#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
41#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 42#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
42 43
43/* 44/*
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 826d326b8062..7c8e0c42b05d 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -16,17 +16,12 @@
16 16
17#include "prcm-common.h" 17#include "prcm-common.h"
18 18
19#ifndef __ASSEMBLER__
20#define OMAP_PRM_REGADDR(module, reg) \
21 IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
22#else
23#define OMAP2420_PRM_REGADDR(module, reg) \ 19#define OMAP2420_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) 20 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
25#define OMAP2430_PRM_REGADDR(module, reg) \ 21#define OMAP2430_PRM_REGADDR(module, reg) \
26 IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) 22 IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
27#define OMAP34XX_PRM_REGADDR(module, reg) \ 23#define OMAP34XX_PRM_REGADDR(module, reg) \
28 IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 24 IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
29#endif
30 25
31/* 26/*
32 * Architecture-specific global PRM registers 27 * Architecture-specific global PRM registers
@@ -38,80 +33,132 @@
38 * 33 *
39 */ 34 */
40 35
41/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */ 36#define OMAP2_PRCM_REVISION_OFFSET 0x0000
42#define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050 37#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
43#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080 38#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
44 39#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
45/* 242x GR_MOD registers, use these only for assembly code */ 40
46#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ 41#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
47 OMAP24XX_PRCM_VOLTCTRL_OFFSET) 42#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
48#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ 43#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
49 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) 44#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
50 45
51/* 243x GR_MOD registers, use these only for assembly code */ 46#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
52#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ 47#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
53 OMAP24XX_PRCM_VOLTCTRL_OFFSET) 48#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
54#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ 49#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
55 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) 50#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
56 51#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
57/* These will disappear */ 52#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
58#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) 53#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
59#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) 54#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
60 55#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
61#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) 56#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
62#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) 57#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
63 58#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
64#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) 59#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
65#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) 60#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
66#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) 61#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
67#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) 62#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
68#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) 63#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
69#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) 64#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
70#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) 65#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
71#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) 66
72#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) 67#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
73 68#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
74#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) 69
75#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) 70#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
76 71#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
77#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) 72
78#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) 73#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
79 74#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
80 75#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
81#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) 76#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
82#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) 77#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
83#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) 78#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
84#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) 79#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
85#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) 80#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
86#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) 81#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
87#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) 82#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
88#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) 83
89#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) 84#define OMAP3_PRM_REVISION_OFFSET 0x0004
90#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) 85#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
91#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) 86#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
92#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) 87#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
93#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) 88
94#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) 89#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
95#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) 90#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
96#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) 91#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
97#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) 92#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
98#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) 93
99#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) 94
100#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) 95#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
101#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) 96#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
102#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) 97#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
103#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) 98#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
104#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) 99#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
105#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) 100#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
106#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) 101#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
107#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) 102#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
108#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) 103#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
109#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) 104#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
110#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) 105#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
111#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) 106#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
112 107#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
113#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) 108#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
114#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 109#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
110#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
111#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
112#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
113#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
114#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
115#define OMAP3_PRM_RSTST_OFFSET 0x0058
116#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
117#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
118#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
119#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
120#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
121#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
122#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
123#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
124#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
125#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
126#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
127#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
128#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
129#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
130#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
131#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
132#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
133#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
134#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
135#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
136#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
137#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
138#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
139#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
140#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
141#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
142#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
143#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
144#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
145#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
146#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
147#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
148#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
149#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
150#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
151#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
152#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
153#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
154#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
155#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
156#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
157
158#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
159#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
160#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
161#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
115 162
116/* 163/*
117 * Module specific PRM registers from PRM_BASE + domain offset 164 * Module specific PRM registers from PRM_BASE + domain offset
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 0afdad5ae9fb..feaec7eaf6bd 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -99,7 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
99 m_type = omap2xxx_sdrc_get_type(); 99 m_type = omap2xxx_sdrc_get_type();
100 100
101 local_irq_save(flags); 101 local_irq_save(flags);
102 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); 102 if (cpu_is_omap2420())
103 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
104 else
105 __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
103 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); 106 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
104 curr_perf_level = level; 107 curr_perf_level = level;
105 local_irq_restore(flags); 108 local_irq_restore(flags);
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index cbb893042487..bb299851116d 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -124,7 +124,7 @@ omap242x_sdi_cm_clksel2_pll:
124omap242x_sdi_sdrc_dlla_ctrl: 124omap242x_sdi_sdrc_dlla_ctrl:
125 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 125 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
126omap242x_sdi_prcm_voltctrl: 126omap242x_sdi_prcm_voltctrl:
127 .word OMAP242X_PRCM_VOLTCTRL 127 .word OMAP2420_PRCM_VOLTCTRL
128prcm_mask_val: 128prcm_mask_val:
129 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
130omap242x_sdi_timer_32ksynct_cr: 130omap242x_sdi_timer_32ksynct_cr:
@@ -220,7 +220,7 @@ omap242x_srs_sdrc_dlla_ctrl:
220omap242x_srs_sdrc_rfr_ctrl: 220omap242x_srs_sdrc_rfr_ctrl:
221 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) 221 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
222omap242x_srs_prcm_voltctrl: 222omap242x_srs_prcm_voltctrl:
223 .word OMAP242X_PRCM_VOLTCTRL 223 .word OMAP2420_PRCM_VOLTCTRL
224ddr_prcm_mask_val: 224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
226omap242x_srs_timer_32ksynct: 226omap242x_srs_timer_32ksynct:
@@ -305,7 +305,7 @@ wait_dll_lock:
305 ldmfd sp!, {r0-r12, pc} @ restore regs and return 305 ldmfd sp!, {r0-r12, pc} @ restore regs and return
306 306
307omap242x_ssp_set_config: 307omap242x_ssp_set_config:
308 .word OMAP242X_PRCM_CLKCFG_CTRL 308 .word OMAP2420_PRCM_CLKCFG_CTRL
309omap242x_ssp_pll_ctl: 309omap242x_ssp_pll_ctl:
310 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN) 310 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
311omap242x_ssp_pll_stat: 311omap242x_ssp_pll_stat:
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index 054b0f357aca..9955abcaeb31 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -124,7 +124,7 @@ omap243x_sdi_cm_clksel2_pll:
124omap243x_sdi_sdrc_dlla_ctrl: 124omap243x_sdi_sdrc_dlla_ctrl:
125 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL) 125 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
126omap243x_sdi_prcm_voltctrl: 126omap243x_sdi_prcm_voltctrl:
127 .word OMAP243X_PRCM_VOLTCTRL 127 .word OMAP2430_PRCM_VOLTCTRL
128prcm_mask_val: 128prcm_mask_val:
129 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
130omap243x_sdi_timer_32ksynct_cr: 130omap243x_sdi_timer_32ksynct_cr:
@@ -220,7 +220,7 @@ omap243x_srs_sdrc_dlla_ctrl:
220omap243x_srs_sdrc_rfr_ctrl: 220omap243x_srs_sdrc_rfr_ctrl:
221 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0) 221 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
222omap243x_srs_prcm_voltctrl: 222omap243x_srs_prcm_voltctrl:
223 .word OMAP243X_PRCM_VOLTCTRL 223 .word OMAP2430_PRCM_VOLTCTRL
224ddr_prcm_mask_val: 224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
226omap243x_srs_timer_32ksynct: 226omap243x_srs_timer_32ksynct:
@@ -305,7 +305,7 @@ wait_dll_lock:
305 ldmfd sp!, {r0-r12, pc} @ restore regs and return 305 ldmfd sp!, {r0-r12, pc} @ restore regs and return
306 306
307omap243x_ssp_set_config: 307omap243x_ssp_set_config:
308 .word OMAP243X_PRCM_CLKCFG_CTRL 308 .word OMAP2430_PRCM_CLKCFG_CTRL
309omap243x_ssp_pll_ctl: 309omap243x_ssp_pll_ctl:
310 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN) 310 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
311omap243x_ssp_pll_stat: 311omap243x_ssp_pll_stat: