diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-09-03 13:14:00 -0400 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-09-03 13:14:00 -0400 |
commit | 08e3d5f28d4d696dc559898676019cbd36501025 (patch) | |
tree | a867a3b8a7b7361c98ab296754f99b8982e87305 /arch/arm/mach-omap2 | |
parent | 19f4d3a90bf2815cb97b66e603b5e0311d234458 (diff) |
OMAP3 clock: remove superfluous calls to omap2_init_clk_clkdm
omap2_init_clk_clkdm() is called as part of the chip architecture-specific
initialization code, so calling it again from the struct clk init pointer
just wastes cycles.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.h | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 9a823c341b7b..c8119781e00a 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -1156,7 +1156,6 @@ static struct clk gfx_cg1_ck = { | |||
1156 | .name = "gfx_cg1_ck", | 1156 | .name = "gfx_cg1_ck", |
1157 | .ops = &clkops_omap2_dflt_wait, | 1157 | .ops = &clkops_omap2_dflt_wait, |
1158 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1158 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
1159 | .init = &omap2_init_clk_clkdm, | ||
1160 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1159 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1161 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | 1160 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
1162 | .clkdm_name = "gfx_3430es1_clkdm", | 1161 | .clkdm_name = "gfx_3430es1_clkdm", |
@@ -1167,7 +1166,6 @@ static struct clk gfx_cg2_ck = { | |||
1167 | .name = "gfx_cg2_ck", | 1166 | .name = "gfx_cg2_ck", |
1168 | .ops = &clkops_omap2_dflt_wait, | 1167 | .ops = &clkops_omap2_dflt_wait, |
1169 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1168 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
1170 | .init = &omap2_init_clk_clkdm, | ||
1171 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1169 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1172 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | 1170 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
1173 | .clkdm_name = "gfx_3430es1_clkdm", | 1171 | .clkdm_name = "gfx_3430es1_clkdm", |
@@ -1211,7 +1209,6 @@ static struct clk sgx_ick = { | |||
1211 | .name = "sgx_ick", | 1209 | .name = "sgx_ick", |
1212 | .ops = &clkops_omap2_dflt_wait, | 1210 | .ops = &clkops_omap2_dflt_wait, |
1213 | .parent = &l3_ick, | 1211 | .parent = &l3_ick, |
1214 | .init = &omap2_init_clk_clkdm, | ||
1215 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | 1212 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
1216 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, | 1213 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, |
1217 | .clkdm_name = "sgx_clkdm", | 1214 | .clkdm_name = "sgx_clkdm", |
@@ -1224,7 +1221,6 @@ static struct clk d2d_26m_fck = { | |||
1224 | .name = "d2d_26m_fck", | 1221 | .name = "d2d_26m_fck", |
1225 | .ops = &clkops_omap2_dflt_wait, | 1222 | .ops = &clkops_omap2_dflt_wait, |
1226 | .parent = &sys_ck, | 1223 | .parent = &sys_ck, |
1227 | .init = &omap2_init_clk_clkdm, | ||
1228 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1224 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1229 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | 1225 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
1230 | .clkdm_name = "d2d_clkdm", | 1226 | .clkdm_name = "d2d_clkdm", |
@@ -1235,7 +1231,6 @@ static struct clk modem_fck = { | |||
1235 | .name = "modem_fck", | 1231 | .name = "modem_fck", |
1236 | .ops = &clkops_omap2_dflt_wait, | 1232 | .ops = &clkops_omap2_dflt_wait, |
1237 | .parent = &sys_ck, | 1233 | .parent = &sys_ck, |
1238 | .init = &omap2_init_clk_clkdm, | ||
1239 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1234 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1240 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, | 1235 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, |
1241 | .clkdm_name = "d2d_clkdm", | 1236 | .clkdm_name = "d2d_clkdm", |
@@ -1623,7 +1618,6 @@ static struct clk core_l3_ick = { | |||
1623 | .name = "core_l3_ick", | 1618 | .name = "core_l3_ick", |
1624 | .ops = &clkops_null, | 1619 | .ops = &clkops_null, |
1625 | .parent = &l3_ick, | 1620 | .parent = &l3_ick, |
1626 | .init = &omap2_init_clk_clkdm, | ||
1627 | .clkdm_name = "core_l3_clkdm", | 1621 | .clkdm_name = "core_l3_clkdm", |
1628 | .recalc = &followparent_recalc, | 1622 | .recalc = &followparent_recalc, |
1629 | }; | 1623 | }; |
@@ -1692,7 +1686,6 @@ static struct clk core_l4_ick = { | |||
1692 | .name = "core_l4_ick", | 1686 | .name = "core_l4_ick", |
1693 | .ops = &clkops_null, | 1687 | .ops = &clkops_null, |
1694 | .parent = &l4_ick, | 1688 | .parent = &l4_ick, |
1695 | .init = &omap2_init_clk_clkdm, | ||
1696 | .clkdm_name = "core_l4_clkdm", | 1689 | .clkdm_name = "core_l4_clkdm", |
1697 | .recalc = &followparent_recalc, | 1690 | .recalc = &followparent_recalc, |
1698 | }; | 1691 | }; |
@@ -2090,7 +2083,6 @@ static struct clk dss_tv_fck = { | |||
2090 | .name = "dss_tv_fck", | 2083 | .name = "dss_tv_fck", |
2091 | .ops = &clkops_omap2_dflt, | 2084 | .ops = &clkops_omap2_dflt, |
2092 | .parent = &omap_54m_fck, | 2085 | .parent = &omap_54m_fck, |
2093 | .init = &omap2_init_clk_clkdm, | ||
2094 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2086 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2095 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2087 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
2096 | .clkdm_name = "dss_clkdm", | 2088 | .clkdm_name = "dss_clkdm", |
@@ -2101,7 +2093,6 @@ static struct clk dss_96m_fck = { | |||
2101 | .name = "dss_96m_fck", | 2093 | .name = "dss_96m_fck", |
2102 | .ops = &clkops_omap2_dflt, | 2094 | .ops = &clkops_omap2_dflt, |
2103 | .parent = &omap_96m_fck, | 2095 | .parent = &omap_96m_fck, |
2104 | .init = &omap2_init_clk_clkdm, | ||
2105 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2096 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2106 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2097 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
2107 | .clkdm_name = "dss_clkdm", | 2098 | .clkdm_name = "dss_clkdm", |
@@ -2112,7 +2103,6 @@ static struct clk dss2_alwon_fck = { | |||
2112 | .name = "dss2_alwon_fck", | 2103 | .name = "dss2_alwon_fck", |
2113 | .ops = &clkops_omap2_dflt, | 2104 | .ops = &clkops_omap2_dflt, |
2114 | .parent = &sys_ck, | 2105 | .parent = &sys_ck, |
2115 | .init = &omap2_init_clk_clkdm, | ||
2116 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2106 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2117 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | 2107 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
2118 | .clkdm_name = "dss_clkdm", | 2108 | .clkdm_name = "dss_clkdm", |
@@ -2124,7 +2114,6 @@ static struct clk dss_ick_3430es1 = { | |||
2124 | .name = "dss_ick", | 2114 | .name = "dss_ick", |
2125 | .ops = &clkops_omap2_dflt, | 2115 | .ops = &clkops_omap2_dflt, |
2126 | .parent = &l4_ick, | 2116 | .parent = &l4_ick, |
2127 | .init = &omap2_init_clk_clkdm, | ||
2128 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2117 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2129 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2118 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
2130 | .clkdm_name = "dss_clkdm", | 2119 | .clkdm_name = "dss_clkdm", |
@@ -2136,7 +2125,6 @@ static struct clk dss_ick_3430es2 = { | |||
2136 | .name = "dss_ick", | 2125 | .name = "dss_ick", |
2137 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2126 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
2138 | .parent = &l4_ick, | 2127 | .parent = &l4_ick, |
2139 | .init = &omap2_init_clk_clkdm, | ||
2140 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2128 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2141 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2129 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
2142 | .clkdm_name = "dss_clkdm", | 2130 | .clkdm_name = "dss_clkdm", |
@@ -2160,7 +2148,6 @@ static struct clk cam_ick = { | |||
2160 | .name = "cam_ick", | 2148 | .name = "cam_ick", |
2161 | .ops = &clkops_omap2_dflt, | 2149 | .ops = &clkops_omap2_dflt, |
2162 | .parent = &l4_ick, | 2150 | .parent = &l4_ick, |
2163 | .init = &omap2_init_clk_clkdm, | ||
2164 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | 2151 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2165 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2152 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
2166 | .clkdm_name = "cam_clkdm", | 2153 | .clkdm_name = "cam_clkdm", |
@@ -2171,7 +2158,6 @@ static struct clk csi2_96m_fck = { | |||
2171 | .name = "csi2_96m_fck", | 2158 | .name = "csi2_96m_fck", |
2172 | .ops = &clkops_omap2_dflt, | 2159 | .ops = &clkops_omap2_dflt, |
2173 | .parent = &core_96m_fck, | 2160 | .parent = &core_96m_fck, |
2174 | .init = &omap2_init_clk_clkdm, | ||
2175 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | 2161 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
2176 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | 2162 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, |
2177 | .clkdm_name = "cam_clkdm", | 2163 | .clkdm_name = "cam_clkdm", |
@@ -2184,7 +2170,6 @@ static struct clk usbhost_120m_fck = { | |||
2184 | .name = "usbhost_120m_fck", | 2170 | .name = "usbhost_120m_fck", |
2185 | .ops = &clkops_omap2_dflt, | 2171 | .ops = &clkops_omap2_dflt, |
2186 | .parent = &dpll5_m2_ck, | 2172 | .parent = &dpll5_m2_ck, |
2187 | .init = &omap2_init_clk_clkdm, | ||
2188 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2173 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2189 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | 2174 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
2190 | .clkdm_name = "usbhost_clkdm", | 2175 | .clkdm_name = "usbhost_clkdm", |
@@ -2195,7 +2180,6 @@ static struct clk usbhost_48m_fck = { | |||
2195 | .name = "usbhost_48m_fck", | 2180 | .name = "usbhost_48m_fck", |
2196 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2181 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
2197 | .parent = &omap_48m_fck, | 2182 | .parent = &omap_48m_fck, |
2198 | .init = &omap2_init_clk_clkdm, | ||
2199 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2183 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2200 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | 2184 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
2201 | .clkdm_name = "usbhost_clkdm", | 2185 | .clkdm_name = "usbhost_clkdm", |
@@ -2207,7 +2191,6 @@ static struct clk usbhost_ick = { | |||
2207 | .name = "usbhost_ick", | 2191 | .name = "usbhost_ick", |
2208 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2192 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
2209 | .parent = &l4_ick, | 2193 | .parent = &l4_ick, |
2210 | .init = &omap2_init_clk_clkdm, | ||
2211 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | 2194 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2212 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | 2195 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
2213 | .clkdm_name = "usbhost_clkdm", | 2196 | .clkdm_name = "usbhost_clkdm", |
@@ -2269,7 +2252,6 @@ static struct clk gpt1_fck = { | |||
2269 | static struct clk wkup_32k_fck = { | 2252 | static struct clk wkup_32k_fck = { |
2270 | .name = "wkup_32k_fck", | 2253 | .name = "wkup_32k_fck", |
2271 | .ops = &clkops_null, | 2254 | .ops = &clkops_null, |
2272 | .init = &omap2_init_clk_clkdm, | ||
2273 | .parent = &omap_32k_fck, | 2255 | .parent = &omap_32k_fck, |
2274 | .clkdm_name = "wkup_clkdm", | 2256 | .clkdm_name = "wkup_clkdm", |
2275 | .recalc = &followparent_recalc, | 2257 | .recalc = &followparent_recalc, |
@@ -2384,7 +2366,6 @@ static struct clk per_96m_fck = { | |||
2384 | .name = "per_96m_fck", | 2366 | .name = "per_96m_fck", |
2385 | .ops = &clkops_null, | 2367 | .ops = &clkops_null, |
2386 | .parent = &omap_96m_alwon_fck, | 2368 | .parent = &omap_96m_alwon_fck, |
2387 | .init = &omap2_init_clk_clkdm, | ||
2388 | .clkdm_name = "per_clkdm", | 2369 | .clkdm_name = "per_clkdm", |
2389 | .recalc = &followparent_recalc, | 2370 | .recalc = &followparent_recalc, |
2390 | }; | 2371 | }; |
@@ -2393,7 +2374,6 @@ static struct clk per_48m_fck = { | |||
2393 | .name = "per_48m_fck", | 2374 | .name = "per_48m_fck", |
2394 | .ops = &clkops_null, | 2375 | .ops = &clkops_null, |
2395 | .parent = &omap_48m_fck, | 2376 | .parent = &omap_48m_fck, |
2396 | .init = &omap2_init_clk_clkdm, | ||
2397 | .clkdm_name = "per_clkdm", | 2377 | .clkdm_name = "per_clkdm", |
2398 | .recalc = &followparent_recalc, | 2378 | .recalc = &followparent_recalc, |
2399 | }; | 2379 | }; |